Display panel

Abstract

The present application provides a display panel, which includes a substrate and an active layer. The active layer includes a channel portion and a doped portion. The doped portion is disposed on opposite sides of the channel portion along a first direction. The channel portion is divided into a middle region and edge regions located on opposite sides of the middle region along a second direction. By making the doping concentration of the channel portion in the edge regions greater than that in the middle region, the difference in threshold voltage between the edge regions and the middle region of the thin-film transistor can be reduced, and the premature turn-on of parasitic channels at the edge regions can be avoided, thereby improving the hump effect.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel. Background Art

[0002] Low-temperature polysilicon thin-film transistors are key components for the active driving and peripheral circuits of display devices such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs).

[0003] Currently, in low-temperature polysilicon thin-film transistors, there is a difference in threshold voltage between the inclined angle regions at both edges of the active layer and the threshold voltage in the middle region of the active layer, resulting in the parasitic channels at the inclined angles of the low-temperature polysilicon thin-film transistors being turned on in advance, leading to the hump effect.

[0004] In summary, the thin-film transistors in the existing display panels have the problem of the hump effect. Therefore, it is necessary to provide a display panel to improve this defect. Summary of the Invention

[0005] Embodiments of the present application provide a display panel, which can reduce the difference in threshold voltage between the inclined angle regions at both edges of the thin-film transistor and the threshold voltage in the middle region, and avoid the parasitic channels at the inclined angles of the thin-film transistor being turned on in advance, thereby improving the hump effect.

[0006] Embodiments of the present application provide a display panel, including:

[0007] A substrate;

[0008] An active layer disposed on the substrate, the active layer including a channel portion and a doping portion, the doping portion being disposed on opposite sides of the channel portion along a first direction;

[0009] Wherein, the channel portion is divided into a middle region and edge regions located on opposite sides of the middle region along a second direction, the doping concentration of the channel portion in the edge regions is greater than that in the middle region, and the first direction intersects the second direction.

[0010] According to an embodiment of the present application, the part of the channel portion in the middle region is an extrinsic semiconductor.

[0011] According to an embodiment of the present application, a first ion is doped in the channel portion, and a second ion is doped in the doping portion, and the electric property of the first ion is opposite to that of the second ion.

[0012] According to an embodiment of the present application, the doping portion is doped with the first ion, and the doping concentration of the first ion in the doping portion is less than the doping concentration of the second ion.

[0013] According to an embodiment of the present application, the doping portion includes a heavily doped portion and a lightly doped portion, and the lightly doped portion is disposed between the heavily doped portion and the channel portion;

[0014] Wherein, the doping concentration of the second ion in the heavily doped portion is greater than the doping concentration of the second ion in the lightly doped portion.

[0015] According to an embodiment of the present application, the lightly doped portion includes a first lightly doped portion and a second lightly doped portion, and the second lightly doped portion is disposed between the first lightly doped portion and the channel portion;

[0016] Wherein, the doping concentration of the second ion in the heavily doped portion is greater than the doping concentration of the second ion in the first lightly doped portion, and the doping concentration of the second ion in the first lightly doped portion is greater than the doping concentration of the second ion in the second lightly doped portion.

[0017] According to an embodiment of the present application, the doping concentration of the first ion in the channel portion in the edge region is less than the doping concentration of the second ion in the second lightly doped portion.

[0018] According to an embodiment of the present application, the thickness of the edge region gradually decreases from one end close to the middle region to the end far from the middle region.

[0019] According to an embodiment of the present application, the active layer includes a first surface, a second surface, and sidewalls that are respectively connected to the first surface and the second surface and are inclined, and the second surface is disposed on the side of the first surface facing away from the substrate;

[0020] Wherein, the sidewalls are disposed in the edge region, the first surface is disposed in the middle region and the edge region, and the second surface is at least disposed in the middle region.

[0021] According to an embodiment of the present application, the included angle between the sidewall and the second surface is between 50 degrees and 80 degrees.

[0022] Advantages of the embodiments of the present application: The embodiments of the present application provide a display panel, which includes a substrate and an active layer. The active layer is disposed on the substrate. The active layer includes a channel portion and a doped portion. The doped portion is disposed on opposite sides of the channel portion along a first direction. The channel portion is divided into a middle region and edge regions located on opposite sides of the middle region along a second direction. By making the doping concentration in the edge regions of the channel portion greater than that in the middle region, the difference in threshold voltage between the edge regions and the middle region of the thin-film transistor can be reduced, and the parasitic channel in the edge regions can be prevented from turning on prematurely, thereby improving the hump effect. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 Planar schematic diagram of the first thin-film transistor provided by the embodiments of the present application;

[0025] Figure 2 Cross-sectional schematic diagram of the first thin-film transistor provided by the embodiments of the present application along the A-A direction;

[0026] Figure 3 Cross-sectional schematic diagram of the first thin-film transistor provided by the embodiments of the present application along the B-B direction;

[0027] Figure 4 Cross-sectional schematic diagram of another thin-film transistor provided by the embodiments of the present application along the B-B direction;

[0028] Figure 5 Planar schematic diagram of the second thin-film transistor provided by the embodiments of the present application;

[0029] Figure 6 Cross-sectional schematic diagram of the second thin-film transistor provided by the embodiments of the present application along the A-A direction;

[0030] Figure 7 Planar schematic diagram of the third thin-film transistor provided by the embodiments of the present application;

[0031] Figure 8 Planar schematic diagram of the active layer of the third thin-film transistor provided by the embodiments of the present application;

[0032] Figure 9 Cross-sectional schematic diagram of the third thin-film transistor provided by the embodiments of the present application along the A-A direction;

[0033] Figures 10a to 10p It is a schematic flow chart of a method for manufacturing a display panel provided by an embodiment of the present application. Detailed implementation manners

[0034] The descriptions of the following embodiments refer to the attached drawings for illustrating specific embodiments in which the present application can be implemented. Directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for explaining and understanding the present application, rather than for limiting the present application. In the drawings, units with similar structures are denoted by the same reference numerals.

[0035] The present application will be further described below with reference to the drawings and specific embodiments.

[0036] An embodiment of the present application provides a display panel, which can reduce the difference between the threshold voltage at the inclined angle of the active layer in the two side edge regions and the threshold voltage in the middle region, and avoid the premature turn-on of the parasitic channel of the thin film transistor at the inclined angle, thereby improving the hump effect.

[0037] An embodiment of the present application provides a display panel, the display panel includes a substrate 10 and a driving circuit layer disposed on the substrate 10, and a plurality of thin film transistors are disposed in the driving circuit layer.

[0038] It should be noted that being disposed on the substrate 10 may refer to being in direct contact with the substrate 10 or being in indirect contact with the substrate 10.

[0039] In an embodiment of the present application, as Figure 2 shown, the display panel may further include a light shielding layer 11 and a buffer layer 12. The light shielding layer 11 is disposed on the substrate 10, the buffer layer 12 is disposed on the substrate 10 and covers the light shielding layer 11, and the driving circuit layer is disposed on the buffer layer 12.

[0040] The driving circuit layer may include, but is not limited to, an active layer 21, a gate insulating layer 22, a first metal layer 23, an interlayer dielectric layer 24, a second metal layer 25, a planarization layer 26, a first electrode layer 27, a passivation layer 28, and a second electrode layer 29 that are sequentially stacked on the substrate 10.

[0041] As Figure 2 shown, the active layer 21 is disposed on a side of the buffer layer 12 away from the substrate 10. The active layer 21 may include a channel portion 210 and a doping portion 211, and the doping portion 211 is disposed on opposite sides of the channel portion 210 along the first direction Y.

[0042] The first metal layer 23 is disposed on a side of the gate insulating layer 22 facing away from the substrate 10. The first metal layer 23 may include a plurality of patterned gates 230. The gates 230 are disposed opposite to the channel portions 210, and a positive projection of the gates 230 on the substrate 10 may overlap with a positive projection of the channel portions 210 on the substrate 10.

[0043] The second metal layer 25 is disposed on a side of the interlayer dielectric layer 24 facing away from the substrate 10. The second metal layer 25 may include a source electrode 251 and a drain electrode 252. The source electrode 251 passes through a via hole in the interlayer dielectric layer 24 and the gate insulating layer 22 to contact one of the doped portions 211 of the active layer 21, and the drain electrode 252 passes through another via hole in the interlayer dielectric layer 24 and the gate insulating layer 22 to contact the other doped portion 211 of the active layer 21.

[0044] The first electrode layer 27 is disposed on a side of the planarization layer 26 facing away from the substrate 10, and the second electrode layer 29 is disposed on a side of the passivation layer 28 facing away from the substrate 10. The second electrode layer 29 may include a plurality of patterned pixel electrodes.

[0045] The display panel provided by the embodiment of the present application is a liquid crystal display panel. The first electrode layer 27 may serve as a common electrode, and an electric field is formed between the pixel electrodes in the second electrode layer 29 to drive the liquid crystal molecules to deflect.

[0046] It should be noted that only the liquid crystal display panel is taken as an example in the embodiment of the present application, and the technical solution of the present application is also applicable to other types of display panels such as an organic light emitting diode display panel, a micro light emitting diode display panel (MicroLED), and a mini light emitting diode display panel (MiniLED).

[0047] As Figure 1 shown, along the second direction X, the channel portions 210 may be divided into an intermediate region CA and edge regions EA. The edge regions EA are located on opposite sides of the intermediate region CA along the second direction X, and the first direction Y intersects with the second direction X.

[0048] In the embodiment of the present application, the first direction Y may refer to a direction from one side channel portion 210 to the other side channel portion 210 in the active layer 21, that is, the channel length direction of the thin film transistor. The second direction X may be perpendicular to the first direction Y, and the second direction X may refer to the channel width direction of the thin film transistor. The third direction Z may be perpendicular to both the first direction Y and the second direction X, and the third direction Z may refer to the thickness direction of the display panel.

[0049] In the embodiment of the present application, the doping types of the channel portion 210 and the doping portion 211 are different, that is, the channel portion 210 is doped with a first ion, the doping portion 211 is doped with a second ion, and the electrical property of the first ion is different from that of the second ion. For example, the channel portion 210 is P-type doped, the first ion is a P-type ion, the doping portion is N-type doped, and the second ion is an N-type ion; or, the channel portion 210 is N-type doped, the first ion is an N-type ion, the doping portion is P-type doped, and the second ion is a P-type ion.

[0050] The doping concentration of the channel portion 210 in the edge region EA is greater than the doping concentration of the channel portion 210 in the middle region CA, that is, the doping concentration of the first ion in the channel portion 210 in the edge region EA is greater than the doping concentration of the first ion in the channel portion 210 in the middle region CA.

[0051] In the embodiment of the present application, the type of the thin film transistor is an N-type thin film transistor, the material of the active layer 21 is silicon, and the form of the silicon is polycrystalline silicon. The channel portion 210 is P-type doped, the first ion may be a boron ion, the doping portion 211 is N-type doped, and the second ion may be a phosphorus ion.

[0052] Taking the N-type thin film transistor in the embodiment of the present application as an example, the thickness of the edge region EA gradually decreases from the end close to the middle region CA to the end far from the middle region CA. The thickness of the gate insulating layer 22 above the active layer 21 in the edge region EA is thinner than the thickness of the gate insulating layer 22 on the middle region CA, so that the threshold voltage of the thin film transistor in the edge region EA has a negative shift. The threshold voltage of the thin film transistor in the edge region EA is more negative than the threshold voltage of the middle region CA, so that the parasitic channel of the thin film transistor in the edge region EA is turned on in advance, resulting in the hump effect. In the embodiment of the present application, by increasing the doping concentration of the channel portion 210 in the edge region EA to be greater than the doping concentration of the channel portion 210 in the middle region CA, the difference between the threshold voltage of the thin film transistor in the edge region EA and the threshold voltage in the middle region CA can be reduced, so that the parasitic channel in the edge region EA can be prevented from being turned on in advance, thereby improving the hump effect.

[0053] In one embodiment, the thin film transistor may also be a P-type thin film transistor. The channel portion 210 is N-type doped. The first ion may be, but is not limited to, a phosphorus ion. The doping portion 211 is P-type doped. The second ion may be, but is not limited to, a boron ion. By increasing the doping concentration of the channel portion 210 in the edge region EA to be greater than the doping concentration of the channel portion 210 in the central region CA, the difference between the threshold voltage of the thin film transistor in the edge region EA and the threshold voltage in the central region CA can be reduced. Similarly, the parasitic channel in the edge region EA can be prevented from turning on prematurely, thereby improving the hump effect.

[0054] Further, the active layer 21 includes a first surface a1, a second surface a2, and sidewalls a3 that are respectively connected to the first surface a1 and the second surface a2 and are inclined. The second surface a2 is disposed on a side of the first surface a1 away from the substrate 10. The sidewalls a3 are disposed in the edge region EA. The first surface a1 is disposed in the central region CA and the edge region EA. The second surface a2 is at least disposed in the central region CA.

[0055] In one embodiment, as Figure 3 shown, the second surface a2 is only disposed in the central region CA. The cross-sectional shape of the active layer 21 in the edge region EA may be a right triangle.

[0056] Further, the angle α between the sidewall a3 and the first surface a1 is between 50 degrees and 80 degrees. In this way, it can be avoided that the threshold voltage of the edge region EA is negatively biased more severely due to the excessive slope of the sidewall a3. At the same time, it can also be avoided that the gate insulating layer 22 is broken due to the excessive sidewall a3.

[0057] Specifically, the angle between the sidewall a3 and the first surface a1 may be, but is not limited to, any one of 50 degrees, 60 degrees, 70 degrees, 80 degrees, etc.

[0058] In one embodiment, as Figure 4 shown, the second surface a2 is disposed in the central region CA and the edge region EA. The cross-sectional shape of the active layer 21 in the edge region EA may be a right trapezoid. By increasing the range of the edge region EA, the accuracy requirements of the related devices for doping treatment can be reduced.

[0059] In one embodiment, the portion of the channel portion 210 in the intermediate region CA is an extrinsic semiconductor, that is, both the intermediate region CA and the edge region EA of the channel portion 210 are doped with a first ion. By doping the intermediate region CA of the channel portion 210, the threshold voltage of the thin film transistor can be adjusted.

[0060] In one embodiment, the doping portion 211 is doped with the first ion, and the doping concentration of the first ion in the doping portion 211 is less than the doping concentration of the second ion. The doping concentration of the first ion in the edge region EA of the doping portion 211 may be greater than or equal to the doping concentration in the intermediate region CA, and the doping concentration of the first ion in the doping portion 211 is approximately equal to the doping concentration of the first ion in the channel portion 210.

[0061] In one embodiment, the channel portion 210 in the intermediate region CA may also be an intrinsic semiconductor, that is, the edge region EA of the channel portion 210 is doped with a first ion, while the intermediate region CA is not doped.

[0062] In one implementation, combined Figure 5 and Figure 6 As shown, the doping portion 211 may include a heavily doped portion NP and a lightly doped portion NM. The lightly doped portion NM is disposed between the heavily doped portion NP and the channel portion 210. The doping concentration of the second ion in the heavily doped portion NP is greater than the doping concentration of the second ion in the lightly doped portion NM. The doping concentration of the second ion in the lightly doped portion NM should be much greater than the doping concentration of the first ion in the edge region EA of the channel portion 210. By dividing the doping portion 211 into the heavily doped portion NP and the lightly doped portion NM, the drain electric field can be reduced and the off-state current can be decreased.

[0063] In the embodiment of the present application, the doping concentration of the second ion in the edge region EA of the heavily doped portion NP is equal to the doping concentration of the second ion in the intermediate region CA of the heavily doped portion NP, and the doping concentration of the second ion in the edge region EA of the lightly doped portion NM is equal to the doping concentration of the second ion in the intermediate region CA of the lightly doped portion NM.

[0064] In one embodiment, combined Figure 7 , Figure 8 and Figure 9As shown, the lightly doped region NM includes a first lightly doped region NM1 and a second lightly doped region NM2. The second lightly doped region NM2 is disposed between the first lightly doped region NM1 and the channel region 210. The doping concentration of the second ions in the heavily doped region NP is greater than the doping concentration of the second ions in the first lightly doped region NM1, and the doping concentration of the second ions in the first lightly doped region NM1 is greater than the doping concentration of the second ions in the second lightly doped region NM2.

[0065] It should be noted that Figures 5 to 6 In the embodiment shown, although the lightly doped region NM can reduce the electric field of the drain 252 and decrease the off-state current, due to the large change in the doping concentration from the heavily doped region NP to the lightly doped region NM, the junction electric field strength is still relatively large. Figures 7 to 9 In the embodiment shown, by providing two lightly doped regions with intermediate concentrations, namely the first lightly doped region NM1 and the second lightly doped region NM2, between the heavily doped region NP and the channel region 210, a graded junction is formed, thereby reducing the junction electric field strength and thus reducing the leakage current.

[0066] The doping concentration of the second ions in the heavily doped region NP in the edge region EA is equal to the doping concentration of the second ions in the heavily doped region NP in the middle region CA. The doping concentration of the second ions in the first lightly doped region NM1 in the edge region EA is equal to the doping concentration of the second ions in the first lightly doped region NM1 in the middle region CA. The doping concentration of the second ions in the second lightly doped region NM2 in the edge region EA is equal to the doping concentration of the second ions in the second lightly doped region NM2 in the middle region CA. The doping concentration of the first ions in the channel region 210 in the edge region EA should be much less than the doping concentration of the second ions in the second lightly doped region NM2.

[0067] According to the display panel provided in the above embodiments of the present application, the embodiments of the present application further provide a method for manufacturing a display panel. The method for manufacturing the display panel can be used to manufacture and form the display panel as described in the above embodiments. The method for manufacturing the display panel includes:

[0068] Step S10: Form an active layer 21 on the substrate 10. The active layer 21 is divided into a middle region CA and edge regions EA located on opposite sides of the middle region CA along the second direction X.

[0069] Step S11: Perform doping treatment on the edge regions EA of the active layer 21; and

[0070] Step S12: Dope the active layer 21 again to form a channel portion 210 and a doped portion 211.

[0071] Combined with Figures 10a to 10d shown, the step S10 includes:

[0072] Step S101: As Figure 10a shown, a light-shielding layer 11 is formed on the substrate 10;

[0073] Step S102: As Figure 10b shown, a buffer layer 12 is formed on the substrate 10, and a semiconductor layer 20 is deposited on the buffer layer 12;

[0074] Step S103: As Figure 10c shown, a photoresist is deposited on the semiconductor layer 20, and the photoresist is patterned to form a first photoresist pattern 3;

[0075] Step S104: As Figure 10d shown, the semiconductor layer 20 is patterned to form an active layer 21.

[0076] It should be noted that Figures 10a to 10c , and Figures 10h to 10p are all cross-sectional views of the display panel along the A-A direction, Figures 10d to 10g and at the same time, cross-sectional views of the display panel along two directions A-A and B-B are schematically shown.

[0077] As Figure 10e shown in the cross-sectional view in the B-B direction, the active layer 21 can be divided into an intermediate region CA and edge regions EA located on opposite sides of the intermediate region CA along the second direction X. The edge regions EA have inclined sidewalls. The first photoresist pattern 3 shields the intermediate region CA and exposes the edge regions EA.

[0078] In the embodiment of the present application, the thin-film transistor of the display panel is an N-type thin-film transistor. In step S11, doping the edge region EA of the active layer 21 can dope a first ion in the edge region EA of the active layer 21. The first ion can be a boron ion, and the doping dose for doping the edge region EA can be, but is not limited to, 2×10 12 / cm 2 .

[0079] Combined with Figures 10f to 10j shown, step S12 can include:

[0080] Step S121: As Figure 10f shown, remove the first photoresist pattern 3;

[0081] Step S122: As Figure 10g shown, perform a full-surface doping on the active layer 21;

[0082] Step S123: As Figure 10h shown, dope opposite ends of the active layer 21 to form heavily doped regions NP, and cover other parts of the active layer 21 with a photoresist pattern (not shown in the figure).

[0083] Step S124: As Figure 10i shown. Sequentially form a gate insulating layer 22, a first metal layer 23, and a second photoresist pattern 4 on the active layer 21. The first metal layer 23 and the second photoresist pattern 4 partially cover the active layer 21. Dope the part of the active layer 21 not covered by the second photoresist pattern 4 and the first metal layer 23 to form a first lightly doped region NM1 and a channel region 210. The first lightly doped region NM1, the second lightly doped region NM2, and the heavily doped region NP together constitute a doped region 211;

[0084] Step S125: As Figure 10j shown, etch the first metal layer 23, remove the first photoresist pattern 3, and dope the part of the active layer 21 not covered by the first metal layer 23 to form a second lightly doped region NM2.

[0085] Specifically, in step S122, when performing a full-surface doping on the active layer 21, that is, both the middle region CA and the edge region EA are doped. The doping type is P-type doping, that is, both the middle region CA and the edge region EA of the active layer 21 are doped with a first ion, and the first ion can be boron ions. In step S122, the doping dose for doping the active layer 21 can be but is not limited to 2×10 12 / cm 2 .

[0086] In step S123, perform N-type doping on opposite ends of the active layer 21. Both opposite ends of the active layer 21 are doped with a second ion, and the second ion can be but is not limited to phosphorus ions. The doping dose for forming the heavily doped region NP can be but is not limited to 4×10 14 / cm 2 .

[0087] In step S124, perform N-type doping on the part of the active layer 21 not covered by the second photoresist pattern 4 and the first metal layer 23. The part of the active layer 21 not covered by the second photoresist pattern 4 and the first metal layer 23 is doped with a second ion. The doping dose for forming the first lightly doped region NM1 can be but is not limited to 5×10 13 / cm 2 。

[0088] In step S125, the portion of the active layer 21 not covered by the first metal layer 23 is doped with N-type impurities. The portion of the active layer 21 not covered by the first metal layer 23 is doped with a second ion. The doping dose for forming the second lightly doped portion NM2 may be, but is not limited to, 1×10 13 / cm 2 。

[0089] During the process from step S11 to S12, the edge region EA of the channel portion 210 is doped twice through step S11 and step S122. The total doping dose of the edge region EA of the channel portion 210 is 4×10 12 / cm 2 The middle region CA of the channel portion 210 is doped only once in step S122. The total doping dose of the middle region CA of the channel portion 210 is 2×10 12 / cm 2 In this way, the doping concentration of the first ions in the edge region EA of the channel portion 210 can be made greater than the doping concentration of the first ions in the middle region CA.

[0090] Compared with a conventional N-type thin film transistor in the prior art, the doping dose of the heavily doped portion is 4×10 14 / cm 2 The doping dose of the lightly doped portion is 1×10 13 / cm 2 The doping dose of the channel portion is 2×10 12 / cm 2 In the embodiment of the present application, the doping dose of the edge region EA of the active layer 21 can be individually adjusted through steps S10 to S11, so that the doping concentration of the channel portion 210 of the active layer 21 in the edge region EA is greater than that in the middle region CA. In this way, the threshold voltage difference between the edge region EA and the middle region CA of the thin film transistor can be reduced, thereby improving the hump effect.

[0091] In addition, in the embodiment of the present application, through a re-etch technology, two lightly doped portions with intermediate concentrations (i.e., the first lightly doped portion NM1 and the second lightly doped portion NM2) are provided between the heavily doped portion NP and the channel portion 210 to form a graded junction, thereby reducing the junction electric field strength and thus reducing the leakage current.

[0092] Combined with Figures 10k to 10p As shown, the method for manufacturing a display panel provided in the embodiment of the present application further includes:

[0093] Step S13: As Figure 10kAs shown, an interlayer dielectric layer 24 is formed on the gate insulating layer 22 and the first metal layer 23, and the interlayer dielectric layer 24 and the gate insulating layer 22 are etched to form a plurality of vias, and the vias expose the heavily doped portion NP;

[0094] Step S14: As Figure 10l shown, a second metal layer 25 is formed on the interlayer dielectric layer 24, and the second metal layer 25 is etched to form a source electrode 251 and a drain electrode 252;

[0095] Step S15: As Figure 10m shown, a planarization layer 26 is formed on the second metal layer 25 and the interlayer dielectric layer 24, and a plurality of vias are formed on the planarization layer 26, and the vias expose the drain electrode 252;

[0096] Step S16: As Figure 10n shown, a first electrode layer 27 is formed on the planarization layer 26;

[0097] Step S17: As Figure 10o shown, a passivation layer 28 is formed on the first electrode layer 27 and the planarization layer 26, and a plurality of vias are formed on the passivation layer 28, and the vias expose the drain electrode 252;

[0098] Step S18: As Figure 10p shown, a second electrode layer 29 is formed on the passivation layer 28, and the second electrode layer 29 is in contact with the drain electrode 252 through the vias on the passivation layer 28.

[0099] It should be noted that the method for manufacturing a display panel provided in the embodiments of the present application is only exemplified by the Figures 7 to 9 display panel shown, and only some steps of the method for manufacturing the display panel are schematically shown in the embodiments of the present application. For the structures of other display panels not shown and related manufacturing steps, reference can be made to the structures of existing display panels and related manufacturing steps. The method for manufacturing a display panel provided in the above embodiments is also applicable to the display panels provided in other embodiments, and will not be elaborated here.

[0100] Advantageous effects of the embodiments of the present application: The embodiments of the present application provide a display panel, which includes a substrate and an active layer. The active layer is disposed on the substrate. The active layer includes a channel portion and a doped portion. The doped portion is disposed on opposite sides of the channel portion along a first direction. The channel portion is divided into a middle region and edge regions located on opposite sides of the middle region along a second direction. By making the doping concentration in the edge regions of the channel portion greater than that in the middle region, the difference in threshold voltage between the edge regions and the middle region of the thin film transistor can be reduced, and the parasitic channel in the edge regions can be prevented from being turned on in advance, thereby improving the hump effect.

[0101] In summary, although the present application is disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is based on the scope defined by the claims.

Claims

1. A display panel, characterized in that, Comprising: A substrate; An active layer disposed on the substrate, the active layer including a channel portion and a doped portion, the doped portion being disposed on opposite sides of the channel portion along a first direction; Wherein, the channel portion is divided into an intermediate region and edge regions located on opposite sides of the intermediate region along a second direction, the doping concentration of the channel portion in the edge regions is greater than that in the intermediate region, and the first direction intersects the second direction; the doped portion is doped with a second ion, the doped portion includes a heavily doped portion and a lightly doped portion, the lightly doped portion is disposed between the heavily doped portion and the channel portion, the lightly doped portion includes a first lightly doped portion and a second lightly doped portion, the second lightly doped portion is disposed between the first lightly doped portion and the channel portion, the doping concentration of the second ion in the heavily doped portion is greater than that in the first lightly doped portion, and the doping concentration of the second ion in the first lightly doped portion is greater than that in the second lightly doped portion; The active layer includes a first surface, a second surface, and sidewalls that are respectively connected to the first surface and the second surface and are inclined. The second surface is disposed on a side of the first surface away from the substrate. The sidewalls are disposed in the edge region, and the included angle between the sidewalls and the second surface is between 50 degrees and 80 degrees; the total doping dose of the channel portion in the edge region is 4×10 12 / cm 2 , and the total doping dose of the channel portion in the middle region is 2×10 12 / cm 2 .

2. The display panel according to claim 1, wherein, The portion of the channel portion in the intermediate region is an extrinsic semiconductor.

3. The display panel according to claim 1, characterized in that, The channel portion is doped with a first ion, and the electrical property of the first ion is opposite to that of the second ion.

4. The display panel according to claim 3, wherein The doped portion is doped with the first ion, and the doping concentration of the first ion in the doped portion is less than that of the second ion.

5. The display panel according to claim 3, wherein The doping concentration of the first ion in the edge regions of the channel portion is less than that of the second ion in the second lightly doped portion.

6. The display panel according to claim 1, characterized in that, The thickness of the edge regions gradually decreases from one end close to the intermediate region to the end far from the intermediate region.

7. The display panel according to claim 1, characterized in that, The first surface is disposed on the intermediate region and the edge regions, and the second surface is disposed at least on the intermediate region.

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