Current mode circuit and calibration thereof

Abstract

A current mode circuit comprising at least one switching unit, each switching unit comprising a field effect transistor connected in series with an impedance at its source terminal and configured to carry a given current, wherein, for each switching unit or for at least one of the switching units, the impedance is a variable impedance; and an adjustment circuit configured to, for each switching unit or for at least one of the switching units, adjust the impedance of the variable impedance to calibrate a predetermined characteristic of the switching unit dependent on the field effect transistor.

Description

TECHNICAL FIELD

[0001] The present invention relates to current mode circuitry for use in, for example, a high speed digital-to-analog converter (DAC) or an analog-to-digital converter (ADC). Such current mode circuitry can be referred to as switching circuitry or circuitry. Such circuitry can be implemented as integrated circuitry on, for example, an IC chip. BACKGROUND

[0002] Figure 1 An overview of the previously considered DAC is shown by way of example. Figure 1 The DAC in Fig. 1 is part of a current steering type of DAC integrated circuit (IC) and is designed to convert an m-bit digital input word (D1 to Dm) into a corresponding analog output signal.

[0003] Reference is made to Figure 1 Fig. 1, which shows a schematic diagram of a DAC 1 according to an embodiment of the present invention. The DAC 1 comprises analog circuitry including a number n of identical current sources 21 to 2 n n = 2 m-1 Each current source 2 passes a substantially constant current I. The analog circuitry further comprises a number n of differential switching circuits 41 to 4 n corresponding to the respective current sources 21 to 2 n Each differential switching circuit 4 is connected to its respective current source 2 and switches the current I generated by the current source to either a first terminal connected to a first connection line A of the converter or to a second terminal connected to a second connection line B of the converter.

[0004] Each differential switching circuit 4 receives one of a plurality of digital control signals T1 to Tn (referred to as "thermometer encoded signals" for reasons explained below) and selects either its first terminal or its second terminal depending on the value of the signal in question. The first output current I A of the DAC 1 is the sum of the respective currents passed to the first terminals of the differential switching circuits, and the second output current I B of the DAC 1 is the sum of the respective currents passed to the second terminals of the differential switching circuits. The analog output signal is the voltage V A resulting from sinking the first output current I A of the DAC 1 into a resistance R, and the voltage V B resulting from sinking the second output current I B of the DAC 1 into another resistance R. The analog output signal is the voltage difference V A -V B .

[0005] The thermometer encoded signals T1 to Tn are obtained from the binary input words D1 to Dm by a digital circuit system including a binary thermometer decoder 6. The decoder 6 operates as follows: When the binary input words D1 to Dm have a minimum value, the thermometer encoded signals T1 to Tn cause the differential switching circuits 41 to 4... n Each of them selects its second terminal, thus all current sources 21 to 2 n Both are connected to the second connection line B. In this state, V A =0, V B =nIR. Analog output signal V A -V B =-nIR. As the values ​​of the binary input words D1 to Dm gradually increase, the thermometer-encoded signals T1 to Tn generated by the decoder 6 cause more differential switching circuits to select their respective first terminals (starting from differential switching circuit 41), while no differential switching circuit that has selected its first terminal switches back to its second terminal. When the binary input words D1 to Dm have a value i, the first i differential switching circuits 41 to 4... i Select their respective first terminals, while the remaining ni differential switching circuits 4 i+1 Up to 4 n Select their respective second terminals. Analog output signal V A -V B It equals (2i-n)IR.

[0006] Thermometer encoding is popular in current-directed DACs because as the binary input word increases, more current sources are switched to the first connection line A, while no current source already switched to line A is switched to another line B. Accordingly, the DAC's input / output characteristics are monotonic, and the glitches caused by changes in 1s in the input word are very small.

[0007] exist Figure 2 The text shows what is suitable and Figure 1 An exemplary differential switching circuit (or current-mode circuit) used in conjunction with a DAC. This differential switching circuit includes a first PMOS field-effect transistor (FET) S1 and a second PMOS field-effect transistor (FET) S2. The respective sources of transistors S1 and S2 are connected to a common node TAIL, and corresponding current sources ( Figure 1 21 to 2 n The drains of transistors S1 and S2 are connected to the common node TAIL. The drains of transistors S1 and S2 are connected to the circuit's respective first output node OUTA and second output node OUTB, which correspond to... Figure 1 The first and second terminals of each of the differential switching circuits shown.

[0008] Each transistor S1 and S2 has a corresponding drive circuit 81 or 82 connected to its gate. Complementary input signals IN and INB are applied to the inputs of drive circuits 81 and 82, respectively. Each driver circuit buffers and inverts its received input signal IN or INB to generate a switching signal SW1 or SW2 for its associated transistor S1 or S2, such that, under steady-state conditions, one of transistors S1 and S2 is turned on while the other is turned off. For example, as Figure 2 As shown, when the input signal IN is high (H) and the input signal INB is low (L), the switching signal SW1 (gate drive voltage) of transistor S1 is low (L), turning the transistor on, while the switching signal SW2 (gate drive voltage) of transistor S2 is high (H), turning the transistor off. Therefore, in this case, all input current flowing into the common node TAIL flows to the output node OUTA, and no current flows to the output node OUTB.

[0009] When expectations change Figure 2 When the circuit is in a state such that transistor S1 is turned off and transistor S2 is turned on, complementary changes occur simultaneously in the input signals IN and INB, causing input signal IN to change from H to L while input signal INB changes from L to H. As a result of these complementary changes, transistor S1 is turned off and transistor S2 is turned on, causing all input current flowing into the common node TAIL to flow to the output node OUTB and no current to flow to the output node OUTA.

[0010] In the differential switching circuitry of a high-speed DAC, transistors S1 and S2 need to switch from off to on very quickly, and vice versa. To achieve fast switching, the transistors must be made as small as possible. However, while minimizing the size of the transistors minimizes their switching delay, it is found that the mismatch in switching delay from one transistor to another increases. In other words, it is discovered that there may be a mismatch between the switching delay of a given transistor and a reference switching delay. Summary of the Invention

[0011] It is desirable to solve one or more of the above problems, and in particular, it is desirable to provide a current-mode circuit (sampling switching circuit) with improved performance, for example, at higher operating speeds.

[0012] According to an embodiment of the first aspect of the application, there is provided a current mode circuit comprising: at least one switching cell, each switching cell comprising a field effect transistor connected in series with an impedance at its source terminal and configured to carry a given current, wherein for each switching cell or for at least one of the switching cells the impedance is a variable impedance; and an adjustment circuit to adjust the impedance of the variable impedance for each switching cell or for said at least one of the switching cells to calibrate a predetermined characteristic of the switching cell dependent on the field effect transistor.

[0013] In this way, any mismatch of the field effect transistor S (relative to a reference field effect transistor - not shown) to the predetermined characteristic can be at least partially calibrated. Such calibration can for example be used at least partially as a switching delay calibration. Such calibration can also be particularly useful in case the field effect transistor S is a FinFET, i.e. a fin field effect transistor.

[0014] For each switching cell or for said at least one of the switching cells: the variable impedance can comprise a first resistor connected in parallel with a second resistor, the second resistor being a variable resistor; the adjustment circuit can be configured to adjust the resistance of the variable resistor to calibrate the predetermined characteristic.

[0015] For each switching cell or for said at least one of the switching cells: the first resistance can comprise a polysilicon resistor or a diffusion resistor, optionally a fixed resistance resistor; and / or the variable resistor can comprise a calibration transistor (e.g. a field effect transistor).

[0016] The first resistor can have a resistance of X Ohms, and the second resistor can be controllable to have a resistance in a defined resistance range. A mid-range resistance of the defined resistance range can be Y Ohms, with 5 < Y / X < 20, or 10 < Y / X < 14. The resistance range can be approximately from 5.X Ohms to 25.X Ohms (where 5.X means 5 times X, and similarly for other similar expressions), or approximately from 6.X Ohms to 20.X Ohms.

[0017] For each switching cell or for said at least one of the switching cells: the adjustment circuit can comprise a digital-to-analogue converter connected to control the variable resistor in dependence on a digital input signal; the adjustment circuit can be configured to control the digital input signal of the digital-to-analogue converter involved to adjust the resistance of the variable resistor.

[0018] The adjustment circuit can be configured to, for each switching unit, measure the predetermined property and to, for each switching unit or for said at least one of the switching units, adjust the impedance of the variable impedance to adjust the measured property to or towards a reference value. In this way, the predetermined property can be calibrated. Thereby, other properties such as switching delay can be controlled.

[0019] For each switching unit: the given current can have a defined value; and the predetermined property can be a potential difference comprising the sum of the gate-source voltage of the field effect transistor and the potential difference across the impedance connected in series with it, optionally when the field effect transistor is provided with a gate voltage having a defined on-voltage level to turn it on.

[0020] For each switching unit, the field effect transistor and the impedance can further be connected in series with a current source defining the given current, a node between the variable impedance and the current source being the measurement node, a voltage at the measurement node being the measurement voltage. The adjustment circuit can comprise a comparator configured to, for each switching unit or for said at least one of the switching units, compare the measurement voltage with a reference voltage and can be configured to, based on the comparison, adjust the impedance of the involved variable impedance to bring the measurement voltage and the reference voltage into or towards a target relationship.

[0021] For each switching unit or for said at least one of the switching units, the target relationship can be that the ratio between the measurement voltage and the reference voltage is substantially a predetermined ratio and / or that the measurement voltage and the reference voltage are substantially equal.

[0022] The current mode circuit can comprise a plurality of switching units. As one example, the reference voltage can be the same for all switching units and the adjustment circuit can be configured to, for each switching unit, based on the comparison, adjust the impedance of the involved variable impedance to bring the measurement voltage and the reference voltage into or towards a target relationship. As another example, the reference voltage of said at least one of the switching units can be the measurement voltage of another switching unit and the adjustment circuit can be configured to, for said at least one of the switching units, based on the comparison, adjust the impedance of its variable impedance to bring its measurement voltage and its reference voltage into or towards a target relationship.

[0023] The adjustment circuit can be configured to control the gate voltage of the field effect transistor to selectively have an on-voltage level to selectively turn the field effect transistor on to carry its given current. The given current and / or the on-voltage level can be the same for all switching units.

[0024] The various measurement nodes can be connected together to form a shared measurement node. A shared current source can be connected to the shared measurement node. The adjustment circuitry can be configured to: control the gate voltages of the field effect transistors to sequentially turn them on one by one, such that the shared current source defines a given current for the switch cell whose field effect transistor is turned on; and adjust the impedance of the variable impedance of each switch cell or of said at least one of the switch cells in case the field effect transistor of the switch cell or of said at least one of the switch cells is turned on.

[0025] According to embodiments of the second aspect of the application, there is provided a digital-to-analogue converter or an analogue-to-digital converter comprising a current mode circuit according to the above first aspect of the application.

[0026] According to embodiments of the third aspect of the application, there is provided an integrated circuit system, e.g. an IC chip, comprising a current mode circuit according to the above first aspect of the application, or a digital-to-analogue converter or an analogue-to-digital converter according to the above second aspect of the application.

[0027] The present disclosure corresponds to method aspects (e.g. methods of controlling a current mode circuit) respectively corresponding to the above described apparatus aspects. BRIEF DESCRIPTION OF DRAWINGS

[0028] Reference will now be made, by way of example, to the accompanying drawings, in which:

[0029] As mentioned above, Figure 1 is a schematic diagram of a DAC previously considered;

[0030] As mentioned above, Figure 2 is a schematic diagram of a differential switching circuit for use with Figure 1 the DAC of

[0031] Figure 3A is a schematic diagram of a current mode circuit embodying the present application;

[0032] Figure 3B is a schematic diagram of another current mode circuit embodying the present application;

[0033] Figure 4 is a schematic diagram indicating Figure 3A and Figure 3B how the impedances R, R1, R2 of

[0034] Figure 5 is a schematic diagram of another current mode circuit embodying the present application;

[0035] Figure 6 is a flow diagram representing a method which can be performed by Figure 5 circuitry;

[0036] Figure 7 is Figure 5 a schematic diagram of a part of a current-mode circuit, showing an example detailed implementation of its comparator circuitry;

[0037] Figure 8 to Figure 10 is a flowchart representing a method that can be performed by Figure 5 circuitry;

[0038] Figure 11 is a calibration current I Figure 5 calibration circuitry for calibrating CAL itself;

[0039] Figure 12 is a schematic circuit diagram of a current-mode (current-steering) sampler for understanding embodiments of the invention applied to ADC circuitry;

[0040] Figure 13 is a schematic diagram of a DAC embodying the invention;

[0041] Figure 14 is a schematic diagram of an ADC embodying the invention; and

[0042] Figure 15 is a schematic diagram of integrated circuitry embodying the invention. DETAILED DESCRIPTION

[0043] Embodiments of the invention seek to address the above problems.

[0044] Figure 3A is a schematic diagram of a current-mode circuit 100 embodying the invention. The current-mode circuit 100 comprises a switching cell 10, a trimming circuit 120, and a current source I REF .

[0045] As shown, the switching cell 10 comprises a field effect transistor S (which can be considered a switch) connected in series with an impedance R at its source terminal and configured to carry a given current (here labelled I REF ). The impedance R is a variable impedance.

[0046] The trimming circuit 120 is configured to adjust the impedance of the variable impedance R to “calibrate” any mismatch of the field effect transistor S (relative to a reference field effect transistor - not shown) for the influence on the switching cell 10 of a predetermined characteristic of the field effect transistor S. The predetermined characteristic is a characteristic of the switching cell 10 that depends on, for example, the physical configuration of the field effect transistor S as determined by its manufacture, including its size, its threshold voltage and / or its saturation current I SS . The trimming circuit 120 is configured to measure the predetermined characteristic and adjust the impedance of the variable impedance R to adjust the measured characteristic to or close to a reference value.

[0047] By 'calibrating' the effect of any such mismatch on the predetermined characteristic, the switching delay of the field effect transistor S can be calibrated at least in part.

[0048] In the case of the current mode circuit 100, the predetermined characteristic of the switching unit 10 is the potential difference comprising the sum of its gate-source voltage and the potential difference across the impedance R connected in series therewith, when the field effect transistor S is provided with a gate voltage having a defined on-voltage level to turn it on.

[0049] The field effect transistor S and the impedance R are further connected in series with a current source, as shown, the current source defining a given current I REF . For convenience, the current source defining the given current I REF is labelled I REF (i.e. in the same way as the current it provides), and current sources herein will be labelled in a similar way. In some arrangements, the given current I REF may be a calibration current or have been pre-calibrated for a calibration current I CAL .

[0050] The node M between the variable impedance R and the current source I REF is a measurement node, the voltage at the measurement node being a measurement voltage V M . The adjustment circuit 120 comprises a comparator (not shown) configured to compare the measurement voltage V M to a reference voltage V REF , and configured to adjust the impedance of the variable impedance R involved based on the comparison, to bring the measurement voltage V M into or towards a target relationship with the reference voltage V REF . The target relationship is that the measurement voltage V M and the reference voltage V REF are substantially equal, but can include a target ratio between those voltages (in addition to them being equal).

[0051] In this way, the predetermined characteristic of the switching unit 10 can be calibrated to a reference value (effectively defined by the reference voltage V REF ).

[0052] Although in the above description the predetermined characteristic of the switching unit 10 is the potential difference comprising the sum of its gate-source voltage and the potential difference across the impedance R connected in series therewith, the predetermined characteristic could be any other characteristic of the switching unit 10, such as the gate-source voltage itself, or the potential difference across the impedance R connected in series therewith. Figure 3AOnly one switching unit 10 is shown, but more than one switching unit 10 may be provided. The current-mode circuit 100 can be considered to include at least one switching unit 10, wherein for each switching unit 10 or for at least one switching unit among the switching units 10, the impedance R is a variable impedance. In this case, the adjustment circuit 120 can be configured to adjust the impedance of the variable impedance R for each switching unit 10 or at least one switching unit among the switching units 10 having a variable impedance R in a manner similar to that described above, to calibrate the predetermined characteristics of the switching unit 10 involved.

[0053] Figure 3B This is a schematic diagram of a current-mode circuit 200 implementing the present invention. The current-mode circuit 200 includes a first switching unit 10-1, a second switching unit 10-2, an adjustment circuit 220, and a current source I. REF1 and I REF2 Switching units 10-1 and 10-2 correspond to switching unit 10, while adjusting circuit 220 corresponds to adjusting circuit 120, and are therefore denoted by the same reference numerals.

[0054] As shown in the figure, the switching unit 10-1 includes a field-effect transistor S1 (which can be considered as a switch), which is connected in series with an impedance R1 at its source terminal and is configured to carry a given current (denoted as I here). REF1 Similarly, the switching unit 10-2 includes a field-effect transistor S2 (which can be considered as a switch), which is connected in series with an impedance R2 at its source terminal and is configured to carry a given current (denoted as I here). REF2 ).

[0055] For each switching unit, or for at least one switching unit among the switching units, the impedance is a variable impedance. For this purpose, impedance R1 is shown as a variable impedance, and impedance R2 is shown as an optional variable impedance (i.e., in some arrangements, impedance R2 may have a fixed impedance).

[0056] The adjustment circuit 220 is configured to adjust the impedance of the variable impedance for each switching unit or at least one of the switching units having a variable impedance, in order to calibrate a predetermined characteristic of the switching unit. For illustration, the adjustment circuit 220 is shown as controlling the impedance of impedance R1 and optionally controlling the impedance of impedance R2.

[0057] like Figure 3B As shown, the field-effect transistor S1 and the impedance R1 are connected to the current source I in this order. REF1 Series connection, current source I REF1 Define a given current I REF1 Variable impedance R1 and current source I REF1The node M1 between the variable impedance R1 and the current source I1 is a measurement node, and the voltage at the measurement node is a measurement voltage V M1 Similarly, the field effect transistor S2 and the impedance R2 are also connected in series with a current source I REF2 , in that order, the current source I REF2 defining a given current I REF2 . The variable impedance R2 is connected in series with the current source I REF2 between the variable impedance R2 and the current source I M2 .

[0058] The adjustment circuit 220 comprises a comparator (not shown) configured to, for each switching cell 10-1, 10-2, compare the measurement voltage V M1 , V M2 with a reference voltage, and configured to, based on the comparison, adjust the impedance of the involved variable impedance so that the measurement voltage and the reference voltage are or tend to be in a target relationship (defined similarly as before).

[0059] The reference voltage can be an externally provided reference voltage V REF (as shown), which is the same for both (or all) of the switching cells 10-1, 10-2. In such a case, the adjustment circuit 220 can be configured to, for each switching cell 10-1, 10-2, based on the comparison, adjust the impedance of the involved variable impedance R1, R2 so that the measurement voltage V M1 , V M2 and the reference voltage V REF are or tend to be in a target relationship.

[0060] However, as Figure 3B shown, it is not necessary to provide an external reference voltage V REF , and to illustrate this, the external reference voltage V REF is indicated as optional. For example, the reference voltage of one of the switching cells can be the measurement voltage of the other (or another) of the switching cells. For example, the reference voltage of the switching cell 10-1 can be the measurement voltage V M2 . In this case, the adjustment circuit 220 can be configured to, for the switching cell 10-1, based on the comparison, adjust the impedance of its variable impedance R1 so that its measurement voltage V M1 and its reference voltage V M2 are or tend to be in a target relationship. If the target relationship is that the voltages V M1 and V M2 are equal, and the currents I REF1 and I REF2The equalities, together with the gate voltages provided to the switches SI and S2, and the configuration (e.g. size) of the field effect transistors SI and S2, can be seen to enable the predetermined characteristics of the switch unit 10-1 to be calibrated to be substantially the same as the predetermined characteristics of the switch unit 10-2 in this way. That is, the effects of mismatch (threshold voltage mismatch) between the field effect transistors SI and S2, including switching delay mismatch, can be significantly reduced or compensated for.

[0061] Incidentally, although in Figure 3B each of the switch units 10-1, 10-2 is provided with its own current source I REF1 , I REF2 , the measurement nodes Ml and M2 can be connected together to form a common measurement node M (not shown), which can be considered to be a tail node and compared to the common node TAIL in Figure 2 . In such a case, a given current can be provided by a common current source I REF (not shown), and the field effect transistors SI, S2 are controlled (by their gate voltages) such that when one of them is on, the other is off, and vice versa.

[0062] Accordingly, the adjustment circuit 220 can be configured to control the gate voltages of the field effect transistors SI, S2 to sequentially turn them on one by one, such that the common current source I REF (not shown) defines a given current for the switch unit 10-1, 10-2 for which the field effect transistors SI, S2 are turned on. Furthermore, the adjustment circuit 220 can be configured to adjust the impedance of the variable impedance Rl, R2 of that switch unit 10-1, 10-2 while a given field effect transistor SI, S2 is turned on. The adjustment circuit 220 can be configured to control the gate voltages of the field effect transistors SI, S2 to have turn-on voltage levels to selectively turn them on to carry their given current, and the turn-on voltage levels can be the same for both switch units 10-1, 10-2.

[0063] Indeed, although not shown in Figure 3A , another switch unit 10 can be provided connected to the measurement nodes M, such that one of the field effect transistors SI can be turned on when the other of them is turned off, and vice versa. In this regard, both the current mode circuits 100 and 200 can be compared to the differential switching circuit (or current mode circuit) of Figure 2 , which is considered to be suitable for use with the DAC of Figure 1 in a similar manner. To assist in making this comparison, in Figure 3BThe drain terminals of field-effect transistors S1 and S2 indicate the first output node OUT1 and the second output node OUT2, and the first output node OUT1 and the second output node OUT2 can be connected to... Figure 2 Compare OUTA and OUTB in the table. For consistency, in Figure 3A The drain terminal of the field-effect transistor S indicates the output node OUT.

[0064] Figure 3A and Figure 3B The impedances R, R1, and R2 can be resistors (or resistors). Although Figure 3A and Figure 3B The impedances R, R1, R2 may additionally or alternatively include capacitors and / or inductors, but for simplicity they will be considered as forward resistors.

[0065] Figure 4 This is a schematic diagram illustrating how impedance R can be implemented as a variable impedance. Similar considerations certainly apply to impedances R1 and R2 (when they are variable impedances). As on the left-hand side, impedance R can be implemented as a variable resistor, and as in the center, as implemented with a first resistor R1 in parallel with a second resistor R2, where at least the second resistor R2 is a variable resistor. That is, the first resistor R1 can be a fixed resistor. In the context of an integrated circuit system, the first resistor R1 can include a polysilicon resistor or a diffused resistor. As on the right-hand side, the second resistor R2 can be implemented as a transistor, such as a field-effect transistor (FET). The gate voltage of the FET R2 can be controlled to control its on-resistance.

[0066] As an example only, the first resistor R1 could be a polysilicon resistor with a resistance of 50 ohms, and the second resistor R2 could be implemented as a field-effect transistor with a variable on-resistance ranging from 300 ohms to 1000 ohms. This would allow the resistance of the impedance R to vary between approximately 43 ohms and 48 ohms.

[0067] More generally, the first resistor R1 can have a resistance of X ohms and the second resistor R2 can be controllable to have a resistance within a defined resistance range. The resistance in the middle range of the defined resistance range can be Y ohms, where 5 ≤ Y / X ≤ 20, or 10 ≤ Y / X ≤ 14. The resistance range can be approximately from 5.X ohms to 25.X ohms, or approximately from 6.X ohms to 20.X ohms. Of course, increasing the resistance R increases the associated capacitance, which will adversely affect the switching speed of the associated field-effect transistor S. Furthermore, limiting the range of the resistance R will limit the calibration range.

[0068] Figure 3A and Figure 3BThe adjustment circuits 120 and 220 may include a digital unit or engine (not shown), and for each impedance R, R1, R2, which is a variable impedance, a digital-to-analog converter (not shown) is connected to control the impedance depending on the digital input signal. The adjustment circuits 120 and 220 can then be configured to control the digital input signal of the digital-to-analog converter involved to adjust the impedance. For example, in... Figure 4 In the right-hand implementation mode, the digital-to-analog converter can control the gate voltage of transistor R2.

[0069] review Figure 3A and Figure 3B It will be understood that using impedance R in switching unit 10 allows for the calibration of switching unit 10 (which has a field-effect transistor or switch S) without, for example, calibrating the gate or body voltage. This technique can have specific applications when the field-effect transistor S is a FinFET transistor, i.e., a fin field-effect transistor. In particular, voltage-controlled resistors (see...) Figure 4 The resistors R1 and R2 (where R2 is a FinFET) in the diagram enable the combination of a fixed "polysilicon" resistor R1 and an NMOS switch R2 in parallel to calibrate the switching unit 10 even in the case of a FinFET, in order to compensate for Vth (threshold voltage) mismatch. The on-resistance Ron of the NMOS switch R2 may be much higher than the resistance of the polysilicon resistor R1, which allows it to compensate for changes in Ron due to temperature variations within a sufficient calibration range.

[0070] Figure 5 This is a schematic diagram of a current-mode circuit 300 implementing the present invention, and is an extended implementation of current-mode circuits 100 and 200. The current-mode circuit 300 includes first to fourth switching units 10A, 10B, 10C, and 10D, an optional fifth switching unit 10E, an adjustment circuit 320, and a shared current source I. REF Back Figure 3A The switching units 10A to 10E corresponding to the switching unit 10, the adjustment circuit 320 corresponding to the adjustment circuit 120, and the current source I REF Shared current source I REF Therefore, it is indicated by similar reference numerals as those in the attached figures.

[0071] In order to Figure 3A The switching unit 10A is consistent with the switching unit 10A, which includes a field-effect transistor SA, and the field-effect transistor SA is connected to a variable impedance R1 at its source terminal. A R2 A Series connection. According to... Figure 4 The variable impedance is achieved by using the second resistor R2. A The first resistor R1 in parallel A The first resistor R1 Aimplemented as a poly-silicon resistor (with a fixed resistance), the second resistor R2 A implemented as a transistor. The field-effect transistors SA and the variable impedance R1 A , R2 A is also via the shared measurement node M with a shared current source I REF providing a defined current I REF in series connection.

[0072] The switching units 10B, 10C, 10D and 10E are each configured in the same way as the switching unit 10A, identical elements are denoted in the same way, but the suffix A is replaced by B, C, D or E, respectively, depending on the switching unit. Thus, a repeated description is omitted. All of the switching units 10A, 10B, 10C, 10D and 10E share the shared measurement node M and the shared current source I REF , thus the shared measurement node M can be considered as a tail node equivalent to a common node TAIL in Figure 2 .

[0073] The first and second output nodes OUTA and OUTB are provided for comparison with Figure 2 . The output node OUTA is connected to the drain terminals of the field-effect transistors SA and SB, the output node OUTB is connected to the drain terminals of the field-effect transistors SC and SD. The shared current source I REF is connected between the shared measurement node M and ground GND.

[0074] The adjustment circuit 320 comprises a comparator 322, a digital engine (digital circuit or digital unit) 324, a switch controller 326 and DACs A to E corresponding to the switching units 10A to 10E, respectively. The DACs A to E are configured to output voltage signals V A to V E , respectively, under control of the digital engine 324. The voltage signals V A to V E control the on-resistances of the second resistors R2 A to R2 E (implemented as field-effect transistors), respectively. The switch controller 326 is configured to output gate (voltage) signals GA to GE for controlling the gates of the field-effect transistors SA to SE, respectively, under control of the digital engine 324. It is recalled that the switching unit 10E is optional, thus the DAC E, the voltage signal V E and the gate signal GE can be considered as similarly optional.

[0075] The adjustment circuit 320 further comprises a DAC I and a DAC R corresponding to the shared current source I REF and the comparator 322, respectively.

[0076] DAC I is configured to output a voltage signal V I to control the shared current source I REF , thereby controlling the given current I REF . As will become apparent, in some arrangements the shared current source I REF may be configured to provide the given current I REF with a default (and non-variable) value, in which case there is no need to provide the DAC I.

[0077] DAC R is configured to output a reference voltage signal V REF to be provided to one of the inputs of the comparator 322, where the other input of the comparator 322 is connected to receive the measurement voltage V M provided at the shared measurement node M. As will become apparent, in some arrangements the comparator 322 can be provided with a reference voltage V REF with a default (and non-variable) value, in which case there is also no need to provide the DAC R.

[0078] Figure 5 The optional comparator circuitry 330 (labelled “compare”) and the optional calibration current source 340 are also indicated in FIG. 4. The calibration current source 340 provides a calibration current I CAL . The comparator can be considered separate from the adjustment circuit 320 or part of the adjustment circuit 320. As will become apparent, the comparator circuitry 330 can be used to compare the calibration current I CAL with the given current I REF , where the digital engine 324 uses the output comparison result signal COM to control the voltage signal V I , thereby adjusting (or tuning) the given current I REF to become the same (within a certain accuracy) as the calibration current I CAL . In the event that the given current I REF is tuned in this way, the switch unit 10E, the DAC E and their associated control signals V E and GE can be provided.

[0079] The operation of the current mode circuit 300 can be understood in conjunction with Figure 6 to Figure 10 .

[0080] Figure 6 is a schematic illustration of a method 400 for calibrating the given current I REF to be the same as the calibration current I CAL . Thus, the method 400 assumes that the switch unit 10E, the DAC E and their associated control signals V E and GE are provided. As mentioned above, in the event that the shared current source I REFconfigured to provide a given current I with a default (and non-variable) value REF In this case, there is no need to provide the switching unit 10E, the DAC E and its associated control signal V E and GE, and there is no need to perform the method 400.

[0081] The method 400 comprises steps S402, S403, S404, S405, S406 and S407 and can be performed by the adjustment circuit 320 (and the comparator circuitry 330).

[0082] At step S402, the digital engine 324 controls the switch controller 326 to set the gate signals GA to GE such that the field effect transistors SE are turned on and the field effect transistors SA to SD are turned off. Thus, the given current I REF is carried by the switching unit 10E.

[0083] At step S403, the digital engine 324 provides default (digital) values, e.g. mid values, for the DAC E and the DAC I such that the variable impedances R1 E , R2 E take the default resistance values and the given current I REF takes the default value.

[0084] At step S404, the comparator circuitry 330 is used to compare the calibration current I CAL with the given current I REF As mentioned above, the output comparison result signal COM is provided to the digital engine 324 such that it can be determined whether the calibration current I CAL is the same as the given current I REF If the calibration current I CAL is not the same as the given current I REF (S405, NO), the method 400 proceeds to step S406 at which the digital engine 324 adjusts the digital value provided to the DAC I based on the comparison result signal COM to make the given current I REF closer to the calibration current I CAL . Steps S404, S405, NO and S406 are then repeated until the calibration current I CAL is the same as the given current I REF (S405, YES), e.g. one 1 LSB change in the DAC I, in which case the method 400 continues to step S407.

[0085] At step S407, the existing digital value provided to the DAC I is set or recorded as the calibrated DAC I value, i.e. such that the given current I REF is the same as the calibration current I CAL .

[0086] Figure 7 is Figure 5 a schematic diagram of part 500 of the current-mode circuit 300. In particular, Figure 7 An example detailed implementation of the comparator circuitry 330 is presented to help understand the current-mode circuit 300 and the method of operation 400.

[0087] The comparator circuitry 330 includes nodes 331, 333, 335, 337, and 339, a capacitor 332, a switch 334, a comparator 336, and two inputs T1 and T2. The calibration current source 340 is shown implemented as a transistor connected to apply a calibration current I CAL at the input T1, and the shared current source I REF is shown implemented as a transistor and connected to apply a given current I REF at the input T2.

[0088] Figure 7 A digital engine 324 is also shown, connected to receive a signal COM from the output terminal T3 of the comparator circuitry 330 (and of the comparator 336) and to output a digital control signal to the DAC I, which in turn outputs a voltage signal V I to control the shared current source I REF in line with Figure 5 . It can be appreciated that the digital engine 324 is also capable of generating other control signals as in Figure 5 , but those other control signals are omitted here for simplicity.

[0089] The two inputs T1 and T2 are connected to a node 331, which can be considered a test node. The test node 331 is connected to one of the input terminals of the comparator 336 and to nodes 333 and 335, and the other input terminal of the comparator 336 is connected to nodes 337 and 339 and to a voltage source (not shown) to keep that node at a target voltage level (Vcm). The capacitor 332 and the switch 334 are connected in parallel to each other between the two input terminals of the comparator 336, with the capacitor 332 connected between nodes 333 and 337 and the switch 334 connected between nodes 335 and 339.

[0090] In the operation of comparator circuit system 330, switch 334 is turned on or off (e.g., via digital engine 324 or other control circuitry not shown), connecting node 335 and thus node 331 to node 339, which is maintained at the target voltage level (Vcm). Consequently, capacitor 332 discharges and test node 331 is biased to the target voltage level (Vcm). Switch 334 is then turned off or off (e.g., via digital engine 324 or other control circuitry not shown), and the difference between the current at T1 and the current at T2 (connected at node 331) begins to integrate across capacitor 332 (i.e., charging, positive or negative ground).

[0091] Depending on the difference between the currents at T1 and T2, the voltage at node 331 will fluctuate. After a given test period (selected to allow capacitor 332 to fully charge), the output of comparator 336 will be high or low (resulting in a voltage difference between its two inputs) depending on the difference between the currents at T1 and T2. Therefore, comparator 336 outputs a control signal COM (which is high or low depending on the difference between the currents at T1 and T2) to digital engine 324 at output T3.

[0092] Digital engine 324 is configured to receive control signal COM and output digital control signal to cause DAC I to adjust its voltage signal V. I According to Figure 6 Steps S404, S405, and S406 adjust the given current I REF For example, the process can be iterated in a successive approximation manner (e.g., binary search). This process can be iterated until the output of comparator 336 (control signal COM) changes state (i.e., from low to high or vice versa), for example, a 1LSB change in DAC I. At this point, the current at T1 and the current at T2 are considered to be calibrated to be in a defined relationship (e.g., equal) to be within the required accuracy. For example, the difference between the currents is then less than a threshold current difference.

[0093] The test period (the length of time the capacitor is allowed to charge) can be increased or decreased depending on the required accuracy / resolution and the operating speed of the comparator circuit system 330.

[0094] Figure 8 It is used to calibrate the reference voltage signal V REF A schematic diagram of method 600 for determining the value. Therefore, method 600 assumes that a DAC R is provided. As described above, in the reference voltage signal V REF When configured to have default (and invariable) values, DAC R is not required and method 600 does not need to be executed.

[0095] The method 600 comprises steps S602, S603, S604, S605, S606 and S607 and can be performed by the adjustment circuit 320.

[0096] At step S602, the digital engine 324 controls the switch controller 326 to set the gate signals GA to GE such that the field effect transistors SE are on and the field effect transistors SA to SD are off. Thus, the given current I REF is carried by the switch unit 10E.

[0097] At step S603, the digital engine 324 provides default (digital) values, e.g. middle values, to the DAC R and the DAC E such that the variable impedances R1 E , R2 E take on the default resistance values and the reference voltage signal V REF takes on the default value. Assuming that the method 400 has been performed, the digital engine 324 also provides its calibration value to the DAC I such that the given current I REF is the same as the calibration current I CAL .

[0098] At step S604, the comparator 322 is used to compare the reference voltage signal V REF to the measured voltage V M , the measured voltage V M being associated with the switch unit 10E as the other switch units are off. As shown, an output comparison result signal is provided from the comparator 322 to the digital engine 324 such that it can be determined whether the reference voltage signal V REF is the same as the measured voltage V M . If the reference voltage signal V REF is not the same as the measured voltage V M (S605, No), the method 600 proceeds to step S606 at which the digital engine 324 adjusts the digital value provided to the DAC R based on the comparison result signal from the comparator 322 to make the voltage signal V REF closer to the measured voltage V M . Steps S604, S605, No and S606 are then repeated until the reference voltage signal V REF is the same as the measured voltage V M (S605, Yes), e.g. one 1 LSB change in the DAC R, in which case the method 600 proceeds to step S607.

[0099] At step S607, the existing digital value provided to the DAC R is set or recorded as the calibrated DAC R value, i.e. such that the reference voltage signal V REF is the same as the measured voltage VM In this way, the reference voltage signal V REF may be taken to have a calibrated value.

[0100] Figure 9 is a schematic illustration of a method 700 for calibrating one or all of the switching units 10A to 10D. The method 700 comprises steps S701 to S708 and can be performed by the adjustment circuit 320.

[0101] At step S701, the digital engine 324 sets the value of the variable X to any one of A, B, C and D to enable the switching units 10A to 10D to be calibrated one by one. Of course, if only one of the switching units is to be calibrated, the variable X can be fixed accordingly. For ease of illustration, it is assumed that all of the switching units 10A to 10D are to be calibrated and, in the first instance of step S701, the digital engine 324 sets the value of the variable X to A (to calibrate the switching unit 10A first) and the first pass through steps S702 to S708 will be described accordingly.

[0102] At step S702, the digital engine 324 controls the switching controller 326 to set the gate signals GA to GE such that the field effect transistor SA is turned on and the field effect transistors SE and SB to SD are turned off. Thus, a given current I REF is carried by the switching unit 10A.

[0103] At step S703, the digital engine 324 provides the calibration values of the DAC R and the DAC I, assuming that the methods 400 and 600 have been performed, to the DAC R and the DAC I such that the reference voltage signal V REF has its calibrated value and the given current I REF is the same as the calibration current I CAL The digital engine 324 also provides a default (digital) value, for example a mid value, to the DAC A such that the variable impedance R1 A , R2 A takes on the default resistance value.

[0104] At step S704, the comparator 322 is used to compare the measured voltage V M (which is associated with the switching unit 10A as the other switching units are turned off) with the reference voltage signal V REF As shown, an output comparison result signal is provided from the comparator 322 to the digital engine 324 such that it can be determined whether the measured voltage V M is the same as the reference voltage signal V REF If the measured voltage V M is the same as the reference voltage signal V REFIf not (S705, No), the method 700 proceeds to step S706, at which the digital engine 324 adjusts the digital value provided to the DAC A based on the comparison result signal from the comparator 322 to cause the measured voltage V M to be closer to the voltage signal V REF . Steps S704, S705, No and S706 are then repeated until the measured voltage V M is the same as the reference voltage signal V REF (S705, Yes), e.g. one 1 LSB change in the DAC A, in which case the method 700 proceeds to step S707.

[0105] At step S707, the existing digital value provided to the DAC A is set or recorded as the calibrated DAC A value, i.e. such that the predetermined characteristic of the switching cell 10A has the calibration value and is the same as the value of the switching cell 10E.

[0106] The method then proceeds to step S708, at which it is checked whether the predetermined characteristic of all field effect transistors SA to SD (i.e. the field effect transistors of all switching cells 10A to 10D) that are intended to be calibrated have been calibrated. If not (S708, No), the method returns to step S701, at which the digital engine 324 sets the value of the variable X to a new one of A, B, C and D, and then goes through steps S702 to S708 again. For example, for a second pass through steps S702 to S708, the value of the variable can be set to B, while for a third pass and a fourth pass, the value of the variable is set to C and then D, respectively. Once all switching cells 10A to 10D that are intended to be calibrated have been calibrated (S708, Yes), the method ends.

[0107] In this way, the method 700 can obtain calibration values for the DAC B to DAC D (and the DAC A), which results in the predetermined characteristic of all field effect transistors SA to SD (i.e. the field effect transistors of all switching cells 10A to 10D) having the calibration values and being the same as each other (within 1 LSB DAC accuracy) and the same as the value of the calibrated field effect transistor SE (i.e. the switching cell 10E).

[0108] Figure 10 is a schematic illustration of a method 800 for configuring the current mode circuit 300 to perform a calibration operation. The method 800 comprises steps S801 and S802 and can be performed by the adjustment circuit 320.

[0109] At step S801, the digital engine 324 provides the DACs A to D with their calibration values, so that the predetermined characteristics of all the field effect transistors SA to SD (i.e. the field effect transistors of all the switching cells 10A to 10D) have their calibration values and are identical to each other (within 1 LSB DAC accuracy). It is assumed that the method 400 has been performed, and that the DAC I is also provided with its calibration value.

[0110] At step S802, which corresponds to a calibration operation, the digital engine 324 controls the switching controller 326 to control the gate signals GA to GD so that the current mode circuit 300 performs its intended function. For example, when the current mode circuit 300 is used in a DAC that is consistent with the differential switching circuit (or current mode circuit) of Figure 2 , the gate signals GA to GD can be controlled by thermometer encoded signals (depending on the data supplied to the DAC) so that when one of the field effect transistors SA to SD is on, the others are off, and so that from each clock cycle to the next (synchronized with the gate signals changing state), the on field effect transistor is off and one of the off field effect transistors is on, so that any distortion generated by the switching is independent of the data.

[0111] Recall Figure 5 that the calibration current source 340 provides the calibration current I CAL . With the technique disclosed in EP3618282A1, the calibration current source 340 itself can be calibrated to calibrate this calibration current I CAL , the entire contents of EP3618282A1 are incorporated herein by reference.

[0112] The technique disclosed in EP3618282A1 enables the calibration of multiple output current sources having different amplitudes (currents having different amplitudes), thereby also calibrating the relationship of the amplitudes between each of the output current sources (of the currents). The technique involves using a reference or “golden” current source to calibrate a plurality of candidate current sources, and then using the plurality of candidate current sources to further calibrate the output current sources for a particular application. For example, one of these output current sources (once calibrated) can be used as the calibration current source 340.

[0113] Figure 11 is a schematic diagram of the calibration circuitry 850, which is a simplified version of the calibration circuitry 300 of Figure 5 EP3618282A1. For simplicity of explanation, a single “golden” current source 820, four candidate current sources CCS1 to CCS4, and output current sources OCS 801 to 806 will be considered. As described in EP3618282A1, any number of candidate current sources or output current sources can be used.

[0114] In the following example, it is assumed that each output current source should output a current that is four times the current of the next output current source, i.e. the output current Im of the first output current source OCS 801 is four times the second output current I4 from the second output current source OCS 802, and so on. Such an application can be used for a segmented DAC. This can be summarized as follows:

[0115] Im = 4*I4 = 16*I3 = 64*I2 = 256*I1 = 1024*I0.

[0116] In the present example, the four candidate current sources CCS1 to CCS4 each outputting a candidate current CC1 to CC4 are first calibrated against the “golden” current source 820 outputting the golden current Ic. This is achieved by sequentially comparing each candidate current source with the “golden” current source using the comparator circuitry 830. The comparator circuit 830 can be configured the same as the comparator circuitry 330 and operate in a similar manner, so a repeated description can be omitted.

[0117] The control signal COM output by the comparator circuitry 330 can be used to adjust the candidate current output by each candidate current source. For example, the candidate current source CCS1 outputs a candidate current CC1 which can be compared to the “golden” current Ic. The candidate current source CCS1 can then be adjusted using the control signal COM by means of its control signal B1 (which can be a signal for controlling a variable impedance R, where the current source is implemented as a switching cell consistent with the switching cell 10 described earlier herein) so that the candidate current CC1 and the “golden” current Ic are substantially equal. This process can be repeated in turn for each candidate current source.

[0118] Next, the first output current source OCS 801 is calibrated. The four calibrated candidate current sources CCS1 to CCS4 are added by connecting their outputs together and compared collectively to the first output current Im of the first output current source OCS 801 (i.e. CC1 + CC2 + CC3 + CC4 is compared to Im). In this example, the first output current source OCS 801 is configured to have an output current Im of 4*Ic, i.e. four times the “golden” current. The first output current source OCS 801 is adjusted using the control signal COM output by the comparator circuitry 330 by means of its control signal B-MSB until the first output current Im and the combined candidate current (CC1 + CC2 + CC3 + CC4) are substantially equal. Again, the control signal B-MSB can be a signal for controlling a variable impedance R, where the current source OCS 801 is implemented as a switching cell consistent with the switching cell 10 described earlier herein.

[0119] Next, to calibrate the remaining output current sources, the second output current I4 from the second output current source OCS 802 is compared to a single candidate current (e.g., CC1) and adjusted until the current I4 is equal to that current CC1. This results in the amplitude of the second output current I4 being ¼ the amplitude of the first output current Im, since only one of the four candidate currents is used for comparison. The output COM of the comparator circuitry 330 is used as a control signal based on which the control signal B-LSB4 of the second output current source OCS 802 is adjusted until the second output current I4 is substantially equal to the candidate current CC1.

[0120] Next, the calibrated second output current I4 is compared to the sum of all four candidate currents (i.e., CC1+CC2+CC3+CC4 is compared to I4). However, this time, the output COM of the comparator circuitry 330 is used as the basis for collectively adjusting the candidate current sources via the common control signal input GV (which can be a gate voltage signal) so that their combination is substantially equal to the calibrated second output current I4. This step effectively reduces the amplitude of the candidate currents to a quarter, since the calibrated second output current I4 was previously substantially equal to only one candidate current.

[0121] A similar step is then performed for the remaining output current sources.

[0122] For example, the third output current I3 from the third output current source OCS 803 is compared to a single candidate current (i.e., CC1) and the control signal B-LSB3 is adjusted until I3 = CC1. Once substantially equal, the calibrated third output current I3 is compared to the sum of all four candidate currents (i.e., CC1+CC2+CC3+CC4 is compared to I3) and the candidate current sources are collectively adjusted using the common control input GV so that their sum is substantially equal to the calibrated third output current I3. This again effectively reduces the amplitude of the candidate currents to a quarter, since the calibrated third output current I3 was previously substantially equal to only one candidate current.

[0123] In a similar manner, I2, II, and IO can be calibrated. The result is that the calibrated output currents have a defined relationship to one another (1:4). As noted above, any one of the calibrated output current sources can be used as the calibration current source 340.

[0124] As previously mentioned, the use of impedance R in switching unit 10 allows for the calibration of the switch (field-effect transistor) S without, for example, controlling the gate or body voltage. This technique has specific applications when the field-effect transistor S is a FinFET transistor, i.e., a FinFET field-effect transistor. Instead of controlling the Vth of the switching transistor S through its bulk, the clock switch S is achieved by adjusting the tail voltage Vm of the switch S using voltage-controlled resistors R1 and R2 (see [link to technical documentation]). Figure 5 Calibration of mismatch between DAC chips. In a DAC with multiple DAC chips (each corresponding to...) Figure 5 , and corresponding to Figure 1 In the case of current source 2 and differential switching circuit 4 (pairs), the clock switch S of each DAC chip can be switched by using a dedicated calibration DAC (e.g., Figure 5 The DAC A) used for switching SA compares the chip's tail voltage Vm with the chip's adjusted reference tail voltage V. REF Calibration is performed by comparison. This can be done until the tail voltage Vm used for the involved switch S (e.g., SA) becomes equal to the adjusted tail reference voltage V within 1 LSB accuracy in the calibrated DAC (e.g., DAC A). REF The total resistances R1 and R2 (for each switch S) are effectively adjusted to compensate for the mismatch of switch S. The digital calibration engine 324 can determine whether to increment or decrement the calibration DAC (e.g., DAC A for switch SA) using a binary search method to find the correct calibration code until the tail voltage Vm of switch S becomes equal to the adjusted tail reference voltage V within 1 LSB accuracy. REF This cross-switch SA to SD calibration reduces switching delay mismatch, thereby improving the linearity of the entire DAC.

[0125] Incidentally, although current-mode circuits have been described in this article regarding DAC functionality, it should be understood that they can also be used in ADCs. Figure 12 This is a schematic circuit diagram of a four-phase (i.e., multi-phase) current-mode (current-guided) sampler 900, corresponding to EP-A1-2211468. Figure 10 The entire contents of sampler 42, EP-A1-2211468, are incorporated herein by reference. The sampler forms the front end of the ADC.

[0126] Sampler 900 is configured to receive a differential input current signal, which is modeled as a current source I whose amplitude varies with the input signal. IN For differential signaling, sampler 900 effectively has two matched (or corresponding or complementary) sections 954 and 956 for the two differential inputs. Therefore, a first set of output streams IOUT exists in section 954. A To IOUT Dand a second set of matching output currents IOUTB is present in section 954 A to IOUTB D where IOUTB represents and where IOUT A is paired with IOUTB A , IOUT B is paired with IOUTB B and so on.

[0127] Focusing on the first section 954 by way of example (as the second section 956 operates similarly to the first section 954), there are provided four n-channel FETs 958 A to 958 D (i.e. one per stream or per path) with their source terminals connected together at a common tail node 960.

[0128] The aforementioned current source I IN is connected between the common tail node 960 and an equivalent common tail node 966 of section 956. Another current source I DC 962 is connected between the common tail node 960 and a ground supply and carries a constant DC current I DC . The gate terminals of the four transistors 958 A to 958 D are driven by four clock signals θ0 to θ3 respectively provided from a VCO (not shown). As mentioned above, section 956 is structurally similar to section 954 and thus includes transistors 964 A to 964 D , a common tail node 966 and a current source I DC 968.

[0129] It is assumed that the clock signals θ0 to θ3 are time-interleaved raised cosine waveforms provided as four voltage waveforms from the VCO. The use of four clock signals in the present case is due to the four-way interleaved design of the ADC circuitry described in more detail in EP-A1-2211468, but it will be appreciated that this is not essential.

[0130] The clock signals θ0 to θ3 are 90° out of phase with each other, such that θ0 is at 0° phase, θ1 is at 90° phase, θ2 is at 180° phase and θ3 is at 270° phase. The effect of the sampling circuitry 900 under the control of the clock signals θ0 to θ3 is to output currents IOUT A to IOUT Dis a four-string (or four-stream) current pulse, the pulse sequence in each string has the same period as one of the clock signals θ0to θ3, and the pulses of all four strings are time-interleaved with each other as an effective total pulse string at a quarter of the period of one of the clock signals (or at four times the sampling frequency of one of the clock signals).

[0131] By comparing the current-mode circuit 300 with, for example, the first part 954, it can be appreciated that the field-effect transistor 958 A to 958 D Each of these can be replaced by a switch cell corresponding to the switch cell 10A, and the tail node 960 can be used as the measurement node M for use with the adjustment circuit 320. Thus, such a switch cell can be calibrated using the techniques described earlier herein. The second part 956 can be configured and calibrated in a similar manner. Such an arrangement implements the present application.

[0132] Figure 13 is a schematic diagram of a DAC 1000 implementing the present application. The DAC 1000 comprises any of the current-mode circuits 100, 200, 300 disclosed herein (including modified versions of the sampler 900 as described above). As shown, the DAC 1000 can output an analog signal based on an input digital signal.

[0133] Figure 14 is a schematic diagram of an ADC 2000 implementing the present application. The ADC 2000 comprises any of the current-mode circuits 100, 200, 300 disclosed herein (including modified versions of the sampler 900 as described above). As shown, the ADC 2000 can output a digital signal based on an input analog signal.

[0134] Any of the circuitry disclosed herein can be implemented as integrated circuitry or as an integrated circuit, for example, as an IC chip such as a flip-chip (or as part of it). Figure 15 is a schematic diagram of an integrated circuit system 3000 implementing the present application. The integrated circuit system 3000 can comprise the DAC 1000 and / or the ADC 2000 and / or any of the current-mode circuits 100, 200, 300 disclosed herein (including modified versions of the sampler 900 as described above).

[0135] The integrated circuit system 3000 can represent some or all of an IC chip. The present application extends to the above-mentioned integrated circuit systems and IC chips, circuit boards comprising such IC chips, and communication networks (for example, the Internet fibre-optic network and wireless networks) and network equipment of such networks comprising such circuit boards.

[0136] In any of the above aspects, various features can be implemented in hardware, or as software modules running on one or more processors / computers.

[0137] The present application also provides a computer program or computer program product comprising instructions which, when executed by a computer, cause the computer to carry out any of the methods / method steps described herein; and a non-transitory computer readable medium comprising instructions which, when executed by a computer, cause the computer to carry out any of the methods / method steps described herein. The computer program implementing the present application can be stored on a non-transitory computer readable medium, or it can be in the form of, for example, a signal such as a downloadable data signal provided from an Internet website, or it can be in any other form.

[0138] The application can be implemented in many different ways depending upon the application at hand in accordance with the teachings of the foregoing disclosure.

Claims

1. A current-mode circuit, comprising: A plurality of switching units, each of which includes a field-effect transistor connected in series with an impedance and configured to carry a given current, wherein the impedance is a variable impedance for each switching unit or for at least one of the plurality of switching units; An adjustment circuit is configured to adjust the impedance of the variable impedance for each switching unit or for at least one of the plurality of switching units to calibrate a predetermined characteristic of the switching unit that depends on the field-effect transistor. Shared current source; and Shared measurement nodes in: For each switching unit, the series connection of the field-effect transistor and the impedance is also connected in series with the shared current source, which defines the given current. The node between the series connection and the shared current source is the shared measurement node, and the voltage at the shared measurement node is the measurement voltage. The adjustment circuit includes a comparator configured to compare the measured voltage with a reference voltage for each switching unit or for at least one of the plurality of switching units, and the comparator is configured to adjust the impedance of the variable impedance involved based on the comparison so that the measured voltage and the reference voltage are or tend toward a target relationship.

2. The current-mode circuit according to claim 1, wherein, For each switching unit or for at least one of the plurality of switching units: The variable impedance includes a first resistor, which is connected in parallel with a second resistor, and the second resistor is a variable resistor; and The adjustment circuit is configured to adjust the resistance of the variable resistor to calibrate the predetermined characteristics.

3. The current-mode circuit according to claim 2, wherein, For each switching unit or for at least one of the plurality of switching units: The first resistor includes a polysilicon resistor or a diffused resistor; And / or The variable resistor includes a transistor.

4. The current-mode circuit according to claim 3, wherein, The first resistor has a resistance of X ohms, and the second resistor can be controlled to have a resistance within a defined range, wherein: The mid-range resistance of the defined resistance range is Y ohms, where 5 ≤ Y / X ≤ 20, or where 10 ≤ Y / X ≤ 14; or The resistance range is from 5X ohms to 25X ohms, or from 6X ohms to 20X ohms.

5. The current-mode circuit according to any one of claims 2 to 4, wherein, For each switching unit or for at least one of the plurality of switching units: The adjustment circuit includes a digital-to-analog converter connected to control the variable resistor according to a digital input signal. and The adjustment circuit is configured to control the digital input signal of the digital-to-analog converter involved to adjust the resistance of the variable resistor.

6. The current-mode circuit according to any one of claims 1 to 4, wherein, The adjustment circuit is configured to: For each switching unit, the predetermined characteristic is measured; and For each switching unit or for at least one of the plurality of switching units, the impedance of the variable impedance is adjusted to bring the measured characteristic to or toward a reference value.

7. The current-mode circuit according to claim 6, wherein, For each switching unit: The given current has a defined value; and The predetermined characteristic is a potential difference, which includes the sum of the gate-source voltage of the field-effect transistor and the potential difference across the series connection impedance of the field-effect transistor.

8. The current-mode circuit according to any one of claims 1 to 4, wherein, For each switching unit or for at least one of the plurality of switching units, the target relationship is that the ratio between the measured voltage and the reference voltage is substantially a predetermined ratio and / or the measured voltage is substantially equal to the reference voltage.

9. The current-mode circuit according to any one of claims 1 to 4, wherein: The reference voltage is the same for all of the plurality of switching units, and the adjustment circuit is configured to, for each switching unit, adjust the impedance of the variable impedance involved based on the comparison, so that the measured voltage and the reference voltage are or tend toward the target relationship; or The reference voltage of at least one of the plurality of switching units is the measured voltage of another switching unit, and the adjustment circuit is configured to adjust the impedance of the variable impedance of at least one of the plurality of switching units based on the comparison, so that its measured voltage and its reference voltage are in or tend toward the target relationship.

10. The current-mode circuit according to claim 9, wherein: The adjustment circuit is configured to control the gate voltage of the field-effect transistor to selectively have a turn-on voltage level to selectively turn on the field-effect transistor to carry its given current. as well as The given current and / or the on-voltage level are the same for all of the plurality of switching units.

11. The current-mode circuit according to claim 9, wherein: The adjustment circuit is configured to: Controlling the gate voltage of the field-effect transistors to sequentially turn them on, such that the shared current source defines the given current for the switching units where its field-effect transistors are turned on; and When the field-effect transistor of each switching unit or at least one of the plurality of switching units is turned on, the impedance of the variable impedance of the switching unit is adjusted.

12. The current-mode circuit according to claim 3, wherein, The first resistor is a constant resistance resistor.

13. The current-mode circuit according to claim 7, wherein, The potential difference includes the sum of the gate-source voltage of the field-effect transistor and the potential difference across the series connection impedance of the field-effect transistor when the field-effect transistor is turned on by providing a gate voltage with a defined on-state voltage level.

14. A digital-to-analog converter or analog-to-digital converter, comprising the current-mode circuit of any one of claims 1 to 13.

15. An integrated circuit system comprising a current-mode circuit according to any one of claims 1 to 13, or a digital-to-analog converter or analog-to-digital converter according to claim 14.

16. The integrated circuit system according to claim 15, wherein, The integrated circuit system is an IC chip.

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