Device channel profile structure

Abstract

The transistor channel profile structure can be improved to provide better transistor circuit performance. In one example, the transistor circuit can include different fin profiles for NMOS transistors and PMOS transistors, such as NMOS fins (150) are thicker than PMOS fins (120), or NMOS fins have straight vertical surfaces and PMOS fins have notches at the bottom area of ​​the fins. In another example, the transistor circuit can include different nanosheet profiles for NMOS GAA devices and PMOS GAA devices, where the NMOS nanosheets are thicker than the PMOS nanosheets. This configuration optimizes NMOS transistors and PMOS transistors, where NMOS has low channel resistance and PMOS has lower short channel effects.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of U.S. Non-Provisional Application No. 16 / 917,451, filed on June 30, 2020, entitled “DEVICE CHANNEL PROFILESTRUCTURE,” which is assigned to the assignee of the present application and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to transistors and, more particularly, but not exclusively, to transistor channel profiles. Background Art

[0004] Devices based on transistors such as complementary metal oxide semiconductor (CMOS) transistors, fin field effect transistors (finfets), and non-sheet all-around gate (GAA) transistors are becoming more and more common, driving the demand for better and smaller transistors. CMOS transistors are scaling from planar transistors to finfets and are migrating to nanosheet all-around gate (GAA) devices. As manufacturing technology scales to the 5nm node, the manufacturing process becomes more complex and device performance becomes difficult to improve further. Finfet and GAA device scaling is limited by short channel effects and high channel resistance. For example, the fin profile (top thickness and bottom thickness) and GAA nanosheet thickness are critical to the short channel effect (leakage) and drive current performance of finfet and GAA devices. In addition, since NMOS finfet and PMOS finfet have different responses to different channel profiles, the complexity of the problem increases. For example, n-channel metal oxide semiconductor (NMOS) transistors require lower channel resistance to obtain high performance, while P-channel metal oxide semiconductor (PMOS) transistors require thinner channels to control short channel effects.

[0005] Therefore, there is a need for systems, devices, and methods that overcome the deficiencies of conventional approaches, including the methods, systems, and devices provided herein. Summary of the invention

[0006] The following presents a simplified overview of one or more aspects and / or examples associated with the apparatus and method disclosed herein. Thus, the following overview should not be considered an exhaustive overview of all expected aspects and / or examples, nor should it be considered to identify key or important elements associated with all expected aspects and / or examples, or to describe the scope associated with any particular aspect and / or example. Accordingly, the following overview has the following sole purpose: prior to the detailed description presented below, certain concepts related to one or more aspects and / or examples of the apparatus and method disclosed herein are presented in a simplified form.

[0007] In one aspect, a transistor circuit includes a first fin field effect transistor including a first fin having a first width; and a second fin field effect transistor including a second fin having a second width, wherein the first width is less than the second width.

[0008] In another aspect, a transistor circuit includes: a first component for amplification and switching including a first fin having a first width; and a second component for amplification and switching including a second fin having a second width, wherein the first width is smaller than the second width.

[0009] In yet another aspect, a transistor circuit includes a first gate all around (GAA) transistor including a first channel having a first thickness; and a second GAA transistor including a second channel having a second thickness, wherein the first thickness is greater than the second thickness.

[0010] In another aspect, a method for manufacturing a transistor circuit includes: providing a silicon substrate; forming a first fin of a first fin field effect transistor on the silicon substrate; forming a second fin of a second fin field effect transistor on the silicon substrate near the first fin; trimming a first width of the first fin, the trimmed first width being smaller than a second width of the second fin; and forming gates on the first fin and the second fin.

[0011] Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A more complete understanding of the aspects of the present disclosure and its many attendant advantages will be readily obtained as the same becomes better understood with reference to the following detailed description when considered in conjunction with the accompanying drawings, which are presented for purposes of illustration only and are not limiting of the present disclosure, wherein:

[0013] Figure 1A-1B illustrates exemplary transistor circuits having different fin widths according to some examples of the present disclosure;

[0014] Figure 2A-2Billustrates an exemplary transistor circuit with a fin notch according to some examples of the present disclosure;

[0015] Figure 3A-3B illustrates exemplary transistor circuits with different nanosheet thicknesses according to some examples of the present disclosure;

[0016] Figure 4A-Figure 4I illustrates an exemplary partial method for fabricating transistor circuits having different fin widths according to some examples of the present disclosure;

[0017] Figure 5A-5C illustrates an exemplary partial method for fabricating a transistor circuit with a fin recess according to some examples of the present disclosure;

[0018] Figure 6A-6C illustrates an exemplary partial method for fabricating transistor circuits having different nanosheet thicknesses according to some examples of the present disclosure;

[0019] Figure 7 illustrates an exemplary partial method for manufacturing a transistor circuit according to some examples of the present disclosure;

[0020] Figure 8 illustrates an exemplary mobile device according to some examples of the present disclosure; and

[0021] Fig. 9 Various electronic devices that may be integrated with any of the above-described methods, devices, semiconductor devices, integrated circuits, dies, interposers, packages, or packages-on-packages (PoPs) according to some examples of the present disclosure are illustrated.

[0022] As is customary, features depicted in the drawings may not be drawn to scale. Therefore, the dimensions of the depicted features may be arbitrarily enlarged or reduced for clarity. As is customary, some of the drawings in the drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. In addition, throughout the specification and drawings, the same reference numerals represent the same features. DETAILED DESCRIPTION

[0023] The exemplary methods, devices and systems disclosed herein alleviate the shortcomings of conventional methods, devices and systems, as well as other previously unidentified needs. The examples herein include profile structures for improving the channel performance of transistor circuits. In one example, the transistor circuit is composed of different fin profiles for NMOS transistors and PMOS transistors, wherein the NMOS fin is thicker than the PMOS fin (at both the top and bottom of the fin). In another example, the transistor circuit is composed of different fin profiles for NMOS transistors and PMOS transistors, respectively, wherein the NMOS fin has a straight vertical surface, and the PMOS fin has a notch at the bottom area of ​​the fin. In another example, the transistor circuit is composed of different nanosheet profiles for NMOS GAA devices and PMOS GAA devices, wherein the NMOS nanosheet is thicker than the PMOS nanosheet. In this example, both NMOS transistors and PMOS transistors are optimized, wherein NMOS has a low channel resistance (therefore having a higher drive current), and PMOS has a lower short channel effect (therefore having a lower leakage).

[0024] Figure 1A-1B illustratively shows exemplary transistor circuits with different fin widths according to some examples of the present disclosure. Figure 1A As shown in , transistor circuit 100 may include a first transistor 110 (e.g., a P-type finfet) having a first fin 120 and a first substrate 130 (e.g., silicon, silicon germanium, or similar material), a second transistor 140 (e.g., an N-type finfet) having a second fin 150 and a second substrate 160, and a shared gate 170. Although the first transistor 110 and the second transistor 140 are shown as having two fins, separate substrates, and a shared gate, it should be understood that each transistor may have more or fewer fins, the number of fins may differ between the first transistor 110 and the second transistor 140, a common substrate may be used instead of separate substrates, and separate gates may be used instead of a common or shared gate.

[0025] Figure 1B Shown along Figure 1A Side view of the cutting line in . Figure 1A As shown in the top view of FIG. 1 , each first fin 120 has a first length 122 and a first width 124, and each second fin 150 has a second length 152 and a second width 154. Figure 1B As shown in , the first width 124 includes a first top width 126 and a first bottom width 128, and the first top width 126 is smaller than the first bottom width 128. The first bottom width 128 is closer to the first substrate 130 than the first top width 126. Figure 1BAs shown in , the second width 154 includes a second top width 156 and a second bottom width 158, and the second top width 156 is smaller than the second bottom width 158. The second bottom width 158 is closer to the second substrate 160 than the second top width 156. In addition, the first top width 126 is smaller than or less than the second top width 156, and the first bottom width 128 is smaller than or less than the second bottom width 158. A longer or larger width in the fin profile reduces resistance and makes the fin less susceptible to short channel effects (good for n-type finfets). In contrast, a shorter or smaller width in the fin profile can increase resistance, but makes the fin more susceptible to short channel effects, which in turn makes short channel effects (high leakage current) more controllable (good for p-type finfets).

[0026] Figure 2A-2B FIG. 4 illustrates an exemplary transistor circuit with a fin notch according to some examples of the present disclosure. Figure 2A As shown in , transistor circuit 200 (e.g., transistor circuit 100) may include a first transistor 210 (e.g., a P-type finfet) having a first fin 220 and a first substrate 230 (e.g., silicon, silicon germanium, or a similar material), a second transistor 240 (e.g., an N-type finfet) having a second fin 250 and a second substrate 260, and a shared gate 270. Although the first transistor 210 and the second transistor 240 are shown as having two fins, separate substrates, and a shared gate, it should be understood that each transistor may have more or fewer fins, the number of fins may differ between the first transistor 210 and the second transistor 240, a common substrate may be used instead of separate substrates, and separate gates may be used instead of a common or shared gate.

[0027] Figure 2B Shown along Figure 2A Side view of the cutting line in . Figure 2A As shown in the top view of FIG. 2 , each first fin 220 has a first length 222 and a first width 224, and each second fin 250 has a second length 252 and a second width 254. Figure 2B As shown in FIG. 1 , the first width 224 includes a first top width 226, a first notch width 229, and a first bottom width 228. The first top width 226 is smaller than the first bottom width 228, and the first notch width 229 is smaller than the first bottom width 228. The first notch width 229 can be the same as, larger than, or smaller than the first top width 226. The shorter or smaller width at the notch position near the bottom can increase resistance, but can make the fin more susceptible to short channel effects, which in turn makes the short channel effects (high leakage current) more controllable (good for p-type finFETs).

[0028] Figure 3A-3B FIG. 4 illustrates exemplary transistor circuits with different nanosheet thicknesses according to some examples of the present disclosure. Figure 3A As shown in , transistor circuit 300 may include a first transistor 310 (e.g., a P-type GAA device) having a first substrate 330 (e.g., silicon, silicon germanium, or similar material), a second transistor 340 (e.g., an N-type GAA device) having a second substrate 360, and a shared gate 370. Although first transistor 310 and second transistor 340 are shown as having separate substrates and a shared gate, it should be understood that a common substrate may be used in place of separate substrates, and separate gates may be used in place of a common or shared gate.

[0029] Figure 3B Shown along Figure 3A Side view of the cutting line in . Figure 3B As shown in FIG, the first transistor 310 includes a first channel 320 having a first thickness 324, the second transistor 340 includes a second channel 350 having a second thickness 354, and the first thickness 324 is less than or smaller than the second thickness 354. Smaller thicknesses in the channel profile can increase resistance but make the fin more susceptible to short channel effects, which in turn makes short channel effects (high leakage current) more controllable (good for p-type GAA devices).

[0030] Figure 4A-Figure 4I An exemplary partial method for manufacturing transistor circuits with different fin widths according to some examples of the present disclosure is illustrated. Figure 4A As shown in , a partial method 400 for manufacturing a transistor circuit (e.g., transistor circuit 100) may begin by providing a common substrate 430, forming a plurality of first fins 420 for a first transistor 410, forming a plurality of second fins 450 for a second transistor 440, and applying a mask 480 (e.g., a hard mask such as SiN) to the top of each of the first fins 420 and the second fins 450. In addition, a dummy gate may be formed at this stage. The partial method 400 may be performed at Figure 4B The method 400 continues in which the shallow trench isolation oxide 482 is filled and planarized to level the top portion. Figure 4C The process continues in which a portion of the oxide 482 is removed to expose the first fin 420 .

[0031] Part of method 400 may be found at Figure 4D Continuing in, where the first fin 420 is trimmed to reduce the fin width or profile. As shown, the trimming can include oxidation and removing oxide from the fin surface. Portions of the method 400 can be Figure 4E4. The method 400 may be continued in which the first fin 420 is masked (eg, a photoresist film or mask) and the oxide is removed to expose the second fin 450. Figure 4F The process continues in which the various masks are removed and a common gate 470 is formed around the first fin 420 and the second fin 450 .

[0032] Alternatively, part of the method 400 may include forming the first fin 420 separately from the second fin 450, such as Figure 4G-Figure 4I As shown in Figure 4G As shown in , part of the method 400 may include providing a substrate 430, applying a mask 480 to locations that will become the first fin 420 and the second fin 450. Figure 4H As shown in , part of the method 400 may include applying a mask 484 to the second fin 450 location and trimming the mask 480 at the first fin 420 location so that the first width of the first fin 420 will be less than or smaller than the second width of the second fin 450. Fig. 4I As shown in , part of the method 400 may include exposing a first fin 420 and subsequently exposing a second fin 450 (not shown).

[0033] Figure 5A-5C An exemplary partial method for manufacturing a transistor circuit with a fin recess according to some examples of the present disclosure is illustrated. Figure 5A As shown in FIG. 5 , a portion of a method 500 for manufacturing a transistor circuit (eg, transistor circuit 200 ) may be as follows: Figure 4A-4D or Figure 4G-Figure 4I , and includes providing a common substrate 530, forming a plurality of first fins 520 for a first transistor 510, forming a plurality of second fins 550 for a second transistor 540, and forming a first fin spacer 586 near a top portion on each of the first fins 520 after partially recessing the oxide to expose the first fins 520. The first fin spacer 586 may be formed by depositing a SiN layer and etching to form the first fin spacer 586. Portions of the method 500 may be in Figure 5B 4. The method 500 may be continued in which the oxide under the first fin spacer 586 and the oxide 482 are removed to expose a portion of the first fin 420. Figure 5C Continuing in, the first fin 420 under the first fin spacer 586 is trimmed to reduce the fin width or profile to a first notch width 529. As shown, trimming may include oxidation and removal of oxide from the fin surface.

[0034] Figure 6A-6C An exemplary partial method for fabricating transistor circuits with different nanosheet thicknesses according to some examples of the present disclosure is illustrated. Fig. 6AAs shown in , a portion of a method 500 for manufacturing a transistor circuit (e.g., transistor circuit 300) may include providing a common substrate 630, forming a plurality of first channels 620 for a first transistor 610, and forming a plurality of second channels 650 for a second transistor 640. The channel formation may include forming multiple layers of Si and SiGe to form a pseudo-polysilicon gate, and recessing the pseudo-polysilicon in the region of the first transistor 610. The portion of the method 600 may be performed at Figure 6B 6. The method 600 may be continued in the step of selectively removing SiGe from the first transistor 610 region. Figure 6C Continuing in, the first channel 620 nanosheet is trimmed to reduce the channel width (ie, thickness in the vertical direction and width in the horizontal direction) or profile to be less than the width (thickness) of the second channel 650.

[0035] Figure 7 An exemplary partial method for manufacturing a transistor circuit according to some examples of the present disclosure is illustrated. Figure 7 As shown in , part of the method 700 may begin in box 702 with providing a silicon substrate. Part of the method 700 may continue in box 704, where a first fin of a first finfet transistor is formed on the silicon substrate. Part of the method 700 may continue in box 706, where a second fin of a second finfet transistor is formed on the silicon substrate near the first fin. Part of the method 700 may continue in box 708, where a first width of the first fin is trimmed, and the trimmed first width is less than a second width of the second fin. Part of the method 700 may end in box 710, where a gate is formed on the first fin and the second fin. Alternatively, part of the method 700 may include incorporating the transistor circuit into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a motor vehicle.

[0036] Figure 8 An exemplary mobile device according to some examples of the present disclosure is illustrated. Figure 8, depicts a block diagram of a mobile device configured according to exemplary aspects and generally designated as 800. In some aspects, the mobile device 800 can be configured as a wireless communication device. As shown, the mobile device 800 includes a processor 801, which can be configured to implement the methods described in some aspects herein. The processor 801 is shown to include an instruction pipeline 812, a buffer processing unit (BPU) 808, a branch instruction queue (BIQ) 811, and a throttle 810 as is known in the art. For clarity, other well-known details of these blocks (e.g., counters, entries, confidence fields, weighted sums, comparators, etc.) are omitted from this view of the processor 801.

[0037] The processor 801 may be communicatively coupled to the memory 832 via a link, which may be a die-to-die or chip-to-chip link. The mobile device 800 also includes a display 828 and a display controller 826 , wherein the display controller 826 is coupled to the processor 801 and the display 828 .

[0038] In some aspects, Figure 8 May include a coder / decoder (CODEC) 834 (e.g., an audio and / or voice CODEC) coupled to the processor 801; a speaker 836 and a microphone 838 coupled to the CODEC 834; and a wireless controller 840 (which may include a modem) coupled to a wireless antenna 842 and the processor 801.

[0039] In certain aspects, where one or more of the above blocks are present, the processor 801, display controller 826, memory 832, CODEC 834, and wireless controller 840 may be included in a system-in-package or system-on-chip device 822. The input device 830 (e.g., a physical or virtual keyboard), power supply 844 (e.g., a battery), display 828, input device 830, speaker 836, microphone 838, wireless antenna 842, and power supply 844 may be external to the system-on-chip device 822 and may be coupled to a component of the system-on-chip device 822, such as an interface or controller.

[0040] It should be noted that although Figure 8 A mobile device is depicted, but the processor 801 and memory 832 may also be integrated into a set-top box, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit, computer, laptop computer, tablet computer, communication device, mobile phone, or other similar device.

[0041] Fig. 9Various electronic devices that can be integrated with any of the aforementioned integrated devices, semiconductor devices, integrated circuits, dies, interposers, packages, or packages-on-package (PoP) according to some examples of the present disclosure are illustrated. For example, a mobile phone device 902, a laptop device 904, and a fixed location terminal device 906 may include an integrated device 900 as described herein. The integrated device 900 may be, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, and package-on-package devices described herein. Fig. 9 The devices 902, 904, 906 illustrated in the figure are exemplary only. Other electronic devices may also feature the integrated device 900, including but not limited to a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smart phones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0042] It should be understood that the various aspects disclosed herein may be described as functional equivalents of structures, materials, and / or devices described and / or recognized by those skilled in the art. It should also be noted that the methods, systems, and apparatus disclosed in the description or claims may be implemented by devices including components for performing the corresponding actions of the method. For example, in one aspect, a transistor circuit may include: a first component for amplification and switching (e.g., a CMOS transistor, a finfet transistor, a GAA transistor, etc.), including a first fin having a first width; and a second component for amplification and switching, including a second fin having a second width, wherein the first width is less than the second width. It should be understood that the foregoing aspects are provided only as examples, and the various aspects claimed are not limited to the specific references and / or descriptions cited as examples.

[0043] Figure 1- Fig. 9 One or more of the components, processes, features, and / or functions illustrated in the drawings may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that FIG. 1- Fig. 9 and the corresponding description thereof are not limited to bare chips and / or ICs. In some embodiments, FIG. 1- Fig. 9and corresponding descriptions thereof can be used to manufacture, create, provide, and / or produce an integrated device. In some embodiments, a device may include a bare die, an integrated device, a bare die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, and / or an interposer. The active side of a device (such as a bare die) is the portion of the device that contains the active components of the device (e.g., transistors, resistors, capacitors, inductors, etc.), which perform the operation or function of the device. The back side of a device is the side of the device opposite the active side.

[0044] As used herein, the terms "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal" and variations thereof may interchangeably refer to any suitable mobile or fixed device that can receive wireless communications and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smart phones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, mobile devices in motor vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short range radio, etc.). These terms are also intended to include a device that communicates with another device that can receive wireless communications and / or navigation signals, such as through a short-range wireless, infrared, wired connection, or other connection, whether satellite signal reception, assistance data reception, and / or location-related processing occurs at the device or at other devices. In addition, these terms are intended to include all devices, including wireless and wired communication devices, that are capable of communicating with a core network via a radio access network (RAN), and through the core network, the UE can connect to external networks such as the Internet, as well as to other UEs. Of course, other mechanisms for the UE to connect to the core network and / or the Internet are also possible, such as through a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11, etc.), and the like. The UE can be implemented by any of a variety of types of devices, including but not limited to a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wired phone, a smartphone, a tablet, a tracking device, an asset tag, and the like. The communication link through which the UE sends signals to the RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). The communication link through which the RAN can send signals to the UE is called a downlink or forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein, the term traffic channel (TCH) may refer to an uplink / reverse or a downlink / forward traffic channel.

[0045] Wireless communication between electronic devices can be based on different technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi) and IEEE 802.15.4 (Zigbee / Thread) or other protocols that can be used for wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group, which aims to significantly reduce power consumption and cost while maintaining similar communication range. In 2010, with the adoption of Bluetooth Core Specification Version 4.0 and the update of Bluetooth 5, BLE was merged into the main Bluetooth standard (both of which are expressly incorporated herein in their entirety).

[0046] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as preferred over other examples. Likewise, the term "example" does not mean that all examples include the discussed features, advantages, or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Furthermore, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0047] The terms used herein are for the purpose of describing specific examples and are not intended to limit the examples of the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to also include plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "include", "have", "contain", and / or "comprise" when used herein specify the presence of the features, integers, actions, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, actions, operations, elements, components, and / or groups thereof.

[0048] It should be noted that the terms “connected”, “coupled” or any variations thereof mean any direct or indirect connection or coupling between elements, and may include the presence of intermediate elements between two elements (the two elements are “connected” or “coupled” together via the intermediate elements).

[0049] Any reference to elements using names such as "first", "second", etc. herein does not limit the quantity and / or order of these elements. Instead, these names are used as a convenient method to distinguish two or more elements and / or element instances. In addition, unless otherwise specified, a set of elements may include one or more elements.

[0050] No statement or illustration in this application is intended to confer any component, act, feature, benefit, advantage, or equivalent to the public regardless of whether the component, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0051] In addition, it will be appreciated by those skilled in the art that the various illustrative logic blocks, modules, circuits and algorithmic actions described in conjunction with the examples disclosed herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits and actions are generally described above according to their functions. Whether this functionality is implemented as hardware or software depends on specific applications and the design constraints imposed on the overall system. The technician can implement the described functions in different ways for each specific application, but this implementation decision should not be interpreted as causing deviations from the scope of the present disclosure.

[0052] The methods, sequences and / or algorithms described in conjunction with the examples disclosed herein may be directly included in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art, including a non-transient type of memory or storage medium. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and can write information to the storage medium. In an alternative, the storage medium may be integral to the processor.

[0053] Although some aspects have been described in conjunction with the device, it goes without saying that these aspects also constitute a description of the corresponding method, so the block or component of the device should also be understood as the corresponding method action, or be understood as the feature of the method action. Similarly, the aspects described in conjunction with the method action or as the method action also constitute a description of the corresponding block or details or features of the corresponding device. Some or all of the method actions in the method action can be performed by a hardware device (or using a hardware device), for example, such as a microprocessor, a programmable computer or an electronic circuit. In some examples, some or more of the most important method actions in the most important method actions can be performed by such a device.

[0054] As can be seen in the above detailed description, different features are combined together in the examples. This disclosure should not be understood as an intention that the examples claimed have more features than those explicitly mentioned in the corresponding claims. On the contrary, the present disclosure may include less than all the features of the disclosed individual examples. Therefore, the attached claims should be considered to be included in the description, where each claim itself can be used as a separate example. Although each claim itself can be used as a separate example, it should be noted that although the dependent claims in the claims may refer to a specific combination of one or more claims, other examples may also cover or include a combination of the subject matter of the dependent claims with any other dependent claims, or any feature with other dependent and independent claims. Such combinations are proposed herein unless it is explicitly expressed that a specific combination is not desired. In addition, it is also intended that the features of a claim can be included in any other independent claim, even if the claim is not directly subordinate to the independent claim.

[0055] In addition, in some examples, a single action can be subdivided into multiple sub-actions or include multiple sub-actions. Such sub-actions can be included in the disclosure of a single action and are part of the disclosure of a single action.

[0056] Although the foregoing disclosure shows illustrative examples of the present disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and / or actions of the method claims according to the disclosed examples described herein do not need to be performed in any particular order. In addition, well-known elements will not be described in detail or may be omitted to avoid confusing the relevant details of the aspects and examples disclosed herein. In addition, although the elements of the present disclosure may be described or claimed in the singular, unless explicitly stated to be limited to the singular, the plural form is contemplated.

Claims

1. A transistor circuit comprising: A first fin field effect transistor comprising a first fin having a first width, wherein the first fin field effect transistor is configured as a p-type fin field effect transistor; as well as a second fin field effect transistor including a second fin having a second width, the second fin field effect transistor being configured as an n-type fin field effect transistor, wherein the first width includes a first top width and a first bottom width, and the first top width is less than the first bottom width, and wherein the first width also includes a first notch width between the first top width and the first bottom width, and the first notch width is less than the first bottom width, wherein the second width includes a second top width and a second bottom width, wherein the first bottom width is less than the second bottom width, and wherein the second fin has a straight vertical surface without a notch; as well as A gate is on the first fin and the second fin. 2 . The transistor circuit of claim 1 , wherein the second top width is smaller than the second bottom width. 3 . The transistor circuit of claim 2 , wherein the first top width is smaller than the second top width, and the first bottom width is smaller than the second bottom width. 4 . The transistor circuit of claim 1 , wherein the first FinFET comprises a plurality of fins, the second FinFET comprises a plurality of fins, and each of the plurality of fins of the first FinFET has a smaller width than each of the plurality of fins of the second FinFET.

5. The transistor circuit of claim 1 , wherein the transistor circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a motor vehicle.

6. A transistor circuit comprising: A first component for amplification and switching, comprising a first fin having a first width, wherein the first component for amplification and switching is configured as a p-type fin field effect transistor; a second component for amplification and switching, comprising a second fin having a second width, the second component for amplification and switching being configured as an n-type fin field effect transistor, wherein the first width comprises a first top width and a first bottom width, and the first top width is smaller than the first bottom width, and wherein the first width also comprises a first notch width between the first top width and the first bottom width, and the first notch width is smaller than the first bottom width, wherein the second width comprises a second top width and a second bottom width, wherein the first bottom width is smaller than the second bottom width, and wherein the second fin has a straight vertical surface without a notch; as well as A gate is on the first fin and the second fin. The transistor circuit of claim 6 , wherein the second top width is smaller than the second bottom width. 8 . The transistor circuit of claim 7 , wherein the first top width is smaller than the second top width, and the first bottom width is smaller than the second bottom width.

9. The transistor circuit according to claim 6, wherein the first component for amplifying and switching includes a plurality of fins, the second component for amplifying and switching includes a plurality of fins, and each of the plurality of fins of the first component for amplifying and switching has a smaller width than each of the plurality of fins of the second component for amplifying and switching.

10. The transistor circuit of claim 6, wherein the transistor circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a motor vehicle.

11. A transistor circuit comprising: a first gate-all-around GAA transistor comprising a first channel having a first thickness in a first direction, wherein the first gate-all-around GAA transistor is configured as a p-type GAA device; and a second all-around gate GAA transistor comprising a second channel having a second thickness in the first direction, wherein the second all-around gate GAA transistor is configured as an n-type GAA device, wherein the first thickness in the first direction is less than the second thickness in the first direction, and A shared gate is provided on the first channel and the second channel, the first channel and the second channel are spaced apart from each other in a second direction different from the first direction, so that the first channel and the second channel do not overlap each other in the shared gate in the first direction.

12. The transistor circuit of claim 11 , wherein the first all-around-gate GAA transistor comprises a plurality of channels, the second all-around-gate GAA transistor comprises a plurality of channels, and each of the plurality of channels of the first all-around-gate GAA transistor has a smaller thickness than each of the plurality of channels of the second all-around-gate GAA transistor.

13. The transistor circuit of claim 11, wherein the transistor circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a motor vehicle.

14. A method for manufacturing a transistor circuit, the method comprising: providing a silicon substrate; forming a first fin of a first fin field effect transistor on the silicon substrate, wherein the first fin field effect transistor is configured as a p-type fin field effect transistor; forming a second fin of a second fin field effect transistor on the silicon substrate near the first fin, wherein the second fin field effect transistor is configured as an n-type fin field effect transistor; trimming a first width of the first fin without trimming a second width of the second fin, wherein the first width includes a first top width and a first bottom width, and the first top width is smaller than the first bottom width, and wherein the first width also includes a first notch width between the first top width and the first bottom width, and the first notch width is smaller than the first bottom width, wherein the second width includes a second top width and a second bottom width, wherein the first bottom width is smaller than the second bottom width, and wherein the second fin has a straight vertical surface without a notch; as well as forming a gate on the first fin and the second fin, The forming of the first fin, the forming of the second fin, and trimming of the first fin without trimming of the second fin include: applying a mask to a first fin location and a second fin location, the first fin location and the second fin location being locations on the silicon substrate that will become the first fin and the second fin; trimming the mask at the first fin location without trimming the mask at the second fin location; and The first fin is exposed, and then the second fin is exposed. 15 . The method of claim 14 , further comprising forming a plurality of first fins and forming a plurality of second fins, wherein each of the plurality of first fins of the first fin field effect transistor has a smaller width than each of the plurality of second fins of the second fin field effect transistor.

16. The method of claim 14, further comprising incorporating the transistor circuit into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a motor vehicle.

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