Multilayer wiring board and method for manufacturing the same

Abstract

A multilayer circuit board and a manufacturing method thereof. The manufacturing method comprises: providing a first circuit substrate comprising a first circuit layer, the first circuit layer comprising a connection pad, the first circuit substrate being provided with a first blind hole on a side of the first circuit layer, the blind hole being provided with a first conductive part formed by curing of conductive paste, the first conductive part comprising oppositely arranged first and second end parts, the first end part being used for electrically connecting the connection pad; providing a second circuit substrate comprising a second circuit layer and a third circuit layer, the second circuit layer comprising a signal line; and laminating and pressing the first and second circuit substrates, so that the second circuit layer is located between the first and third circuit layers, in a length direction of the first circuit substrate, the signal line is connected with part of the second end part, and in a thickness direction of the first circuit substrate, an orthogonal projection of a connection area of the second end part and the signal line on the connection pad is located in the connection pad.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit board, and in particular to a multilayer circuit board and a preparation method thereof. BACKGROUND

[0002] With the development of 5G technology, the application frequency of electronic devices is gradually developing towards the millimeter wave frequency band. Accordingly, the design of the circuit board used for transmission lines or antennas also needs to meet the demand of high frequency.

[0003] The circuit board includes signal lines located in the inner layer and pads located in the outer layer. In order to lead out the signal lines and electrically connect with external components (such as mainboards), a via hole needs to be arranged between the pads located in the same layer as the signal lines and the pads in the outer layer, and the signal lines are electrically connected to the pads in the outer layer through the via hole. However, a large parasitic capacitance will be generated between the two pads, causing signal integrity problems. SUMMARY

[0004] In order to solve at least one of the above problems in the prior art, it is necessary to provide a multilayer circuit board and a preparation method thereof.

[0005] The present application provides a preparation method of a multilayer circuit board, comprising the following steps: providing a first circuit substrate comprising a first circuit layer, the first circuit layer comprising a connection pad, the first circuit substrate being provided with a first blind hole on one side of the first circuit layer, the blind hole being provided with a first conductive part formed by curing conductive paste, the first conductive part comprising oppositely arranged first and second end parts, the first end part being used for electrically connecting the connection pad; providing a second circuit substrate comprising a second circuit layer and a third circuit layer, the second circuit layer comprising a signal line; stacking and pressing the first circuit substrate and the second circuit substrate, so that the second circuit layer is located between the first circuit layer and the third circuit layer, in the length direction of the first circuit substrate, the signal line is connected to part of the second end part, and in the thickness direction of the first circuit substrate, the orthogonal projection of the connection area of the second end part and the signal line on the connection pad is located in the connection pad, thereby obtaining the multilayer circuit board.

[0006] In some possible implementation manners, in the length direction of the first circuit substrate, the length L of the connection area and the diameter D of the second end part satisfy: D / 3 < L < D.

[0007] In some possible implementation manners, the second circuit layer further comprises a hole ring, the hole ring is arranged around the connection area, the hole ring is provided with a first gap, and the signal line passes through the first gap.

[0008] In some possible implementation manners, the hole ring is further provided with a plurality of second gaps in the circumferential direction of the hole ring.

[0009] In some possible implementation manners, the first circuit substrate further includes a base layer, a fourth circuit layer and a dielectric layer, the first circuit layer, the dielectric layer, the fourth circuit layer and the base layer are sequentially stacked, the dielectric layer is provided with a second blind hole, the second blind hole is provided with a second conductive part formed by curing conductive paste, the second conductive part is electrically connected to the connection pad, the base layer is provided with the first conductive part, and the first conductive part is further electrically connected to the second conductive part.

[0010] The application further provides a multilayer circuit board including a first circuit substrate and a second circuit substrate which are stacked. The first circuit substrate includes a first circuit layer including a connection pad, and is provided with a first blind hole on a side of the first circuit layer, and the first blind hole is provided with a first conductive part, the first conductive part is made of conductive paste, and the first conductive part includes oppositely arranged first and second end parts, and the first end part is used for electrically connecting the connection pad. The second circuit substrate includes a second circuit layer and a third circuit layer, and the second circuit layer includes a signal line. The second circuit layer is located between the first circuit layer and the third circuit layer, in a length direction of the multilayer circuit board, the signal line is connected to part of the second end part, and in a thickness direction of the multilayer circuit board, an orthogonal projection of a connection region of the second end part and the signal line on the connection pad is located in the connection pad.

[0011] In some possible implementation manners, in the length direction of the multilayer circuit board, a length L of the connection region and a diameter D of the second end part satisfy D / 3 < L < D.

[0012] In some possible implementation manners, the second circuit layer further includes a hole ring, the hole ring is arranged around the connection region, the hole ring is provided with a first notch, and the signal line passes through the first notch.

[0013] In some possible implementation manners, the hole ring is further provided with a plurality of second notches in a circumferential direction of the hole ring.

[0014] In some possible implementation manners, the first circuit substrate further includes a base layer, a fourth circuit layer and a dielectric layer, the first circuit layer, the dielectric layer, the fourth circuit layer and the base layer are sequentially stacked, the dielectric layer is provided with a second blind hole, the second blind hole is provided with a second conductive part, the second conductive part is made of conductive paste, the second conductive part is electrically connected to the connection pad, the base layer is provided with the first conductive part, and the first conductive part is further electrically connected to the second conductive part.

[0015] In this application, since the orthogonal projection of the connection area between the second end and the signal line on the connection pad is located within the connection pad, the overlapping area between the connection pad and the connection area in the thickness direction is reduced, which is beneficial to reduce parasitic capacitance during high-frequency transmission and improve signal integrity. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view of a single-sided copper-clad substrate provided in one embodiment of this application.

[0017] Figure 2 To be Figure 1 The cross-sectional view shown is of the copper foil layer of the single-sided copper-clad substrate after it has been etched into the circuit layer.

[0018] Figure 3 In order to be in Figure 2 A cross-sectional view of the first blind via and the first opening in the first base layer of the single-sided copper-clad substrate shown.

[0019] Figure 4 In order to be in Figure 3 The cross-sectional view of the first circuit board obtained after filling the first blind hole and the first opening with conductive paste is shown.

[0020] Figure 5 This is a cross-sectional view of a double-sided copper-clad substrate provided in one embodiment of this application.

[0021] Figure 6 In order to be in Figure 5 The cross-sectional view shown is of a double-sided copper-clad substrate after a second opening has been made.

[0022] Figure 7 In order to be in Figure 6 The cross-sectional view of the second opening after electroplating is shown.

[0023] Figure 8 To be Figure 7 The cross-sectional view of the second circuit substrate obtained after etching the copper foil layer of the double-sided copper-clad substrate into a circuit layer is shown.

[0024] Figure 9 To be Figure 4 The first circuit board shown and Figure 8 The cross-sectional view shown is of the second circuit board after it has been stacked and laminated.

[0025] Figure 10 for Figure 9 The hole ring on one side of the signal line is shown in a top view in some embodiments.

[0026] Figure 11 for Figure 9 The hole ring on one side of the signal line shown is a top view in some other embodiments.

[0027] Figure 12 FIG. 1 is a cross-sectional view of a multilayer circuit board according to an embodiment of the present application. Figure 9 FIG. 2 is a cross-sectional view of a multilayer circuit board obtained after a protective layer is provided on the circuit layer shown in FIG. 1.

[0028] Figure 13 FIG. 3 is a cross-sectional view of a multilayer circuit board prepared for another embodiment of the present application.

[0029] Explanation of Main Element Symbols

[0030] Multilayer circuit board 1, 2

[0031] Single-sided copper-clad substrate 10

[0032] First base layer 11

[0033] First copper foil layer 12

[0034] First circuit layer 13

[0035] First via 14

[0036] First conductive pillar 15

[0037] Fourth circuit layer 16

[0038] Dielectric layer 17

[0039] Second via 18

[0040] Double-sided copper-clad substrate 20

[0041] Second base layer 21

[0042] Second copper foil layer 22

[0043] Third copper foil layer 23

[0044] Second conductive pillar 24

[0045] Second circuit layer 25

[0046] Third circuit layer 26

[0047] First protective layer 30

[0048] Second protective layer 40

[0049] First circuit substrate 100

[0050] First blind hole 110

[0051] First open hole 111

[0052] Connection pad 130

[0053] First ground line 131

[0054] First end portion 141

[0055] second end portion 142

[0056] second hole ring 160

[0057] second blind hole 170

[0058] second circuit substrate 200

[0059] second opening 201

[0060] signal line 250

[0061] first hole ring 251

[0062] second ground line 260

[0063] first notch 2511

[0064] second notch 2512

[0065] connection area A

[0066] length L

[0067] diameter D

[0068] length direction T1

[0069] thickness direction T2

[0070] The following detailed description will further describe the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0071] The following description will refer to the accompanying drawings to more fully describe the present application. Shown in the drawings are exemplary embodiments of the present application. However, the present application can be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. These exemplary embodiments are provided so that the present application will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art. Like reference numerals refer to like or similar components throughout.

[0072] The terms used herein are only for the purpose of describing particular exemplary embodiments and are not intended to limit the present application. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. Furthermore, when used herein, "include" and / or "comprise" or "including" and / or "comprising" or "have" and / or "has" and / or "having" and the integers, steps, operations, components and / or components thereof, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, components, components and / or groups thereof.

[0073] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0074] The following description of example embodiments will be made with reference to the accompanying drawings. Note that the components depicted in the drawings are not necessarily to scale; rather, the same or similar components will be designated by the same or similar reference numerals, or similar technical terms.

[0075] The specific embodiments of the present application will be further described with reference to the drawings.

[0076] An embodiment of the present application provides a method for manufacturing a multilayer circuit board 1, which can be used to manufacture a transmission line or an antenna. The manufacturing method comprises the following steps:

[0077] S1, please refer to Figure 1 , a single-sided copper-clad substrate 10 is provided, which comprises a first base layer 11 and a first copper foil layer 12 arranged on the surface of the first base layer 11.

[0078] In some embodiments, the material of the first base layer 11 is a thermoplastic resin with a low dielectric constant. Specifically, the material of the first base layer 11 can be selected from one of polypropylene (PP), polyethylene (PE), polycarbonate (PC), polyvinyl chloride (PVC), etc.

[0079] S2, please refer to Figure 2 , the first copper foil layer 12 is etched to form a first circuit layer 13. The first circuit layer 13 comprises a connection pad 130 and a first ground line 131.

[0080] In some embodiments, the first circuit layer 13 can be manufactured through processes such as film pressing, exposure, development, etching, film removal, etc.

[0081] S3, please refer to Figure 3 , a first blind hole 110 and a first opening hole 111 are formed in the single-sided copper-clad substrate 10, both of which penetrate through the first base layer 11, and the bottom of the first blind hole 110 corresponds to the connection pad 130.

[0082] In some embodiments, the first blind hole 110 and the first opening hole 111 can be formed by laser drilling or mechanical drilling.

[0083] S4, please refer to Figure 4The conductive paste is filled in the first blind hole 110 and the first opening 111 to obtain the first conducting part 14 and the first conductive column 15. At this time, the first circuit substrate 100 is obtained.

[0084] In some embodiments, the conductive paste comprises resin and metal particles dispersed in the resin. The metal particles can be made of copper, silver, tin, bismuth, or the like.

[0085] The first conducting part 14 comprises a first end part 141 and a second end part 142. The first end part 141 is connected with the connection pad 130, and the second end part 142 is arranged opposite to the first end part 141. In some embodiments, the end part (i.e. the second end part 142) of the first conducting part 14 and the first conductive column 15 away from the first circuit layer 13 can be flush with the surface of the first base layer 11 away from the first circuit layer 13.

[0086] S5, please refer to Figure 5 , a double-sided copper clad substrate 20 is provided, comprising a second base layer 21 and a second copper foil layer 22 and a third copper foil layer 23 arranged on opposite surfaces of the second base layer 21 respectively.

[0087] In some embodiments, the second base layer 21 is made of thermoplastic resin with a lower dielectric constant. Specifically, the second base layer 21 can be made of one of polypropylene (PP), polyethylene (PE), polycarbonate (PC), polyvinyl chloride (PVC), or the like.

[0088] S6, please refer to Figure 6 A second opening 201 is formed in the double-sided copper clad substrate 20, the second opening 201 penetrates the second copper foil layer 22 and the second base layer 21, and the bottom of the second opening 201 corresponds to the third copper foil layer 23.

[0089] In some embodiments, the second opening 201 can be formed by laser drilling or mechanical drilling.

[0090] S7, please refer to Figure 7 The second conductive column 24 is obtained by electroplating conductive material in the second opening 201.

[0091] In some embodiments, the second conductive column 24 can be formed by electroplating copper in the second opening 201. The end of the second conductive column 24 away from the third copper foil layer 23 protrudes out of the surface of the second copper foil layer 22 away from the third copper foil layer 23.

[0092] S8, please refer to Figure 8 The second copper foil layer 22 and the third copper foil layer 23 are etched to obtain a second circuit layer 25 and a third circuit layer 26 respectively. At this time, the second circuit substrate 200 is obtained.

[0093] The second circuit layer 25 includes a signal line 250. The third circuit layer 26 includes a second ground line 260.

[0094] In some embodiments, the second circuit layer 25 and the third circuit layer 26 can be manufactured by processes such as film pressing, exposure, development, etching, film removing, etc.

[0095] S9, please refer to Figure 9 The first circuit substrate 100 and the second circuit substrate 200 are laminated and pressed to make the second circuit layer 25 between the first circuit layer 13 and the third circuit layer 26. The first ground line 131 and the second ground line 260 are respectively on both sides of the signal line 250, thereby achieving the effects of backflow and grounding.

[0096] The first conductive part 14 is in a semi-cured state, and after pressing, the conductive paste of the first conductive part 14 can flow and connect the signal line 250. In the length direction T1 of the first circuit substrate 100 or the second circuit substrate 200, the signal line 250 is only connected with part of the second end part 142 of the first conductive part 14, and there is a connection area A between them. In the thickness direction T2 of the first circuit substrate 100 or the second circuit substrate 200, the orthogonal projection of the connection area A of the second end part 142 and the signal line 250 on the connection pad 130 is located in the connection pad 130. In this way, the signal line 250 can be electrically connected to the connection pad 130 through the first conductive part 14. Subsequently, electronic components (such as chips) or mainboards can be further connected on the connection pad 130, so that the electrical property of the signal line 250 is led out. Moreover, since the orthogonal projection of the connection area A of the second end part 142 and the signal line 250 on the connection pad 130 is located in the connection pad 130, the overlapping area between the connection pad 130 and the connection area A in the thickness direction T2 is reduced, which is beneficial to reduce the parasitic capacitance during high-frequency transmission and improve signal integrity.

[0097] Please refer to Figure 10 In some embodiments, in the length direction T1 of the first circuit substrate 100 or the second circuit substrate 200, the length L of the connection area A of the second end part 142 and the signal line 250 satisfies: D / 3 < L < D, where D is the diameter of the second end part 142. In this way, the parasitic capacitance can be reduced while ensuring the reliability of the electrical connection between the signal line 250 and the connection pad 130.

[0098] As shown in Figure 10 In some embodiments, the second circuit layer 25 further includes a first hole ring 251. The first hole ring 251 is arranged around the connection area A of the second end part 142 and the signal line 250, and the first hole ring 251 is in a non-closed shape. Since the first hole ring 251 is not closed, the overflow problem of the first conductive part 14 can be inhibited during pressing.

[0099] As shown in FIG. 1, the first via hole 15 is formed in the first base layer 11. The first via hole 15 is filled with the conductive paste to form the first conductive pillar 15. The first conductive pillar 15 is electrically connected to the first connection pad 130. The first connection pad 130 is exposed on the first circuit layer 13. Figure 10 As shown in FIG. 1, in some embodiments, the first hole ring 251 is provided with a first gap 2511, and the signal line 250 passes through the first gap 2511. The first gap 2511 can accommodate the overflow of the conductive paste, thereby avoiding the overflow of the first conductive pillar 14 to other areas after the pressing. Figure 11 In other embodiments, the first hole ring 251 can be further provided with a plurality of second gaps 2512 along the circumferential direction of the first hole ring 251, so that the first hole ring 251 forms a plurality of intermittently distributed areas. The second gap 2512 can also be used to accommodate the overflow of the conductive paste, thereby further avoiding the overflow of the first conductive pillar 14 to other areas after the pressing.

[0100] Further, as shown in FIG. 1, after the pressing, the second conductive pillar 24 is electrically connected to the first conductive pillar 15, thereby electrically connecting the first circuit layer 13, the second circuit layer 25 and the third circuit layer 26. In some embodiments, the second conductive pillar 24 is directly connected to the first conductive pillar 15. In other embodiments, the second conductive pillar 24 can also be connected to the second circuit layer 25, and the interlayer conduction can also be achieved. Figure 9 In some embodiments, the first base layer 11 and the second base layer 21 are both in a semi-cured state, which can flow and fill the circuit gap of the second circuit layer 25 during the pressing.

[0101] S10, as shown in FIG. 1, the first protection layer 30 and the second protection layer 40 are respectively arranged on the first circuit layer 13 and the third circuit layer 26, and the connection pad 130 is exposed on the first protection layer 30. At this time, the multilayer circuit board 1 is obtained.

[0102] Figure 12 In some embodiments, the first protection layer 30 and the second protection layer 40 can both be anti-solder layers. The material of the anti-solder layer can be anti-solder ink.

[0103] As shown in FIG. 1, in some embodiments, the first hole ring 251 is provided with a first gap 2511, and the signal line 250 passes through the first gap 2511. The first gap 2511 can accommodate the overflow of the conductive paste, thereby avoiding the overflow of the first conductive pillar 14 to other areas after the pressing.

[0104] As shown in FIG. 1, in some embodiments, the first hole ring 251 is provided with a first gap 2511, and the signal line 250 passes through the first gap 2511. The first gap 2511 can accommodate the overflow of the conductive paste, thereby avoiding the overflow of the first conductive pillar 14 to other areas after the pressing. Figure 13 The application further provides a preparation method of the multilayer circuit board 2. Different from the above-mentioned embodiments, the first circuit substrate 100 further comprises a fourth circuit layer 16 and a dielectric layer 17, and the first circuit layer 13, the dielectric layer 17, the fourth circuit layer 16 and the first base layer 11 are sequentially stacked. The dielectric layer 17 is provided with a second blind hole 170, and the second blind hole 170 is provided with a second conductive pillar 18 formed by the solidification of the conductive paste. At this time, the first conductive pillar 14 is electrically connected to the connection pad 130 through the second conductive pillar 18. Specifically, the second conductive pillar 18 is electrically connected to the connection pad 130. The first end portion 141 of the first conductive pillar 14 is electrically connected to the second conductive pillar 18.

[0105] ​In some embodiments, the material of the dielectric layer 17 is a thermoplastic resin with a low dielectric constant. Specifically, the material of the second base layer 21 can be selected from one of polypropylene (PP), polyethylene (PE), polycarbonate (PC), polyvinyl chloride (PVC), and the like.

[0106] In some embodiments, as shown in FIG. 1, the first conductive part 14 and the second conductive part 18 are positionally corresponding along the thickness direction T2 of the first circuit substrate 100 or the second circuit substrate 200. Figure 13

[0107] In other embodiments, the first conductive part 14 and the second conductive part 18 can also have a positional deviation along the thickness direction T2. In this case, the fourth circuit layer 16 can also be provided with a second hole ring 160. The second conductive part 18 is connected between the connection pad 130 and the second hole ring 160, and the second conductive part 18 is connected between the second hole ring 160 and the signal line 250. In this way, even if the first conductive part 14 and the second conductive part 18 have a positional deviation along the thickness direction T2, since the first conductive part 14 and the second conductive part 18 are both connected to the second hole ring 160, the reliability of the electrical connection between the first conductive part 14 and the second conductive part 18 can be ensured. Moreover, the second hole ring 160 is in a non-closed shape, so that the overflow problem of the first conductive part 14 and the second conductive part 18 can be inhibited during the pressing process.

[0108] Referring to FIG. 1, an embodiment of the present application provides a multilayer circuit board 1 comprising a first circuit substrate 100 and a second circuit substrate 200 stacked together. Figure 12

[0109] The first circuit substrate 100 comprises a first base layer 11 and a first circuit layer 13 arranged on the surface of the first base layer 11, and the first circuit layer 13 comprises a connection pad 130. The first base layer 11 is provided with a first blind hole 110, and the first blind hole 110 is provided with a first conductive part 14. The material of the first conductive part 14 is conductive paste. The first conductive part 14 comprises a first end part 141 and a second end part 142 arranged oppositely, and the first end part 141 is used for electrically connecting the connection pad 130. The second circuit substrate 200 comprises a second base layer 21 and a second circuit layer 25 and a third circuit layer 26 arranged on the opposite surfaces of the second base layer 21 respectively, and the second circuit layer 25 comprises a signal line 250.

[0110] The second circuit layer 25 is located between the first circuit layer 13 and the third circuit layer 26. In the length direction T1 of the multilayer circuit board 1, the signal line 250 is connected with part of the second end part 142. In the thickness direction T2 of the multilayer circuit board 1, the orthogonal projection of the connection region A between the second end part 142 and the signal line 250 on the connection pad 130 is located within the connection pad 130.

[0111] Referring to FIG. 1, an embodiment of the present application provides a multilayer circuit board 1 comprising a first circuit substrate 100 and a second circuit substrate 200 stacked together. Figure 13 ​​Another embodiment of the present application also provides a multilayer circuit board 2. The difference from the above-mentioned multilayer circuit board 1 is that the first circuit substrate 100 further comprises a fourth circuit layer 16 and a dielectric layer 17, and the first circuit layer 13, the dielectric layer 17, the fourth circuit layer 16 and the first base layer 11 are sequentially stacked. The second blind hole 170 is provided in the dielectric layer 17, and the second blind hole 170 is provided with the second conductive part 18 formed by curing the conductive paste. At this time, the first conductive part 14 is electrically connected to the connecting pad 130 through the second conductive part 18. Specifically, the second conductive part 18 is electrically connected to the connecting pad 130. The first end portion 141 of the first conductive part 14 is electrically connected to the second conductive part 18.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not limited. Although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A method for producing a multilayer wiring board, characterized by, The method comprises the following steps: providing a first circuit substrate comprising a first circuit layer, the first circuit layer comprising a connection pad, the first circuit substrate being provided with a first blind hole on one side of the first circuit layer, the blind hole being provided with a first conductive part formed by curing conductive paste, the first conductive part comprising oppositely arranged first and second end parts, the first end part being used for electrically connecting the connection pad; providing a second circuit substrate comprising a second circuit layer and a third circuit layer, the second circuit layer comprising a signal line; stacking and pressing the first and second circuit substrates, so that the second circuit layer is located between the first and third circuit layers, in the length direction of the first circuit substrate, the signal line is connected to part of the second end part, and in the thickness direction of the first circuit substrate, the orthogonal projection of the connection area of the second end part and the signal line on the connection pad is located within the connection pad, thereby obtaining the multilayer circuit board, and in the length direction of the first circuit substrate, the length L of the connection area and the diameter D of the second end part satisfy D / 3 < L < D.

2. The multilayer wiring board manufacturing method according to claim 1, wherein The second circuit layer further comprises a hole ring, the hole ring is arranged around the connection area, and the hole ring is provided with a first notch, and the signal line passes through the first notch.

3. The multilayer wiring board manufacturing method according to claim 2, wherein The hole ring is further provided with a plurality of second notches along the outer peripheral direction of the hole ring.

4. The multilayer wiring board manufacturing method according to claim 1, wherein The first circuit substrate further comprises a base layer, a fourth circuit layer and a dielectric layer, the first circuit layer, the dielectric layer, the fourth circuit layer and the base layer are sequentially stacked, the dielectric layer is provided with a second blind hole, the second blind hole is provided with a second conductive part formed by curing conductive paste, the second conductive part is electrically connected to the connection pad, the base layer is provided with the first conductive part, and the first conductive part is further electrically connected to the second conductive part.

5. A multilayer wiring board, characterized by, The method comprises the following steps: providing a first circuit substrate comprising a first circuit layer, the first circuit layer comprising a connection pad, the first circuit substrate being provided with a first blind hole on one side of the first circuit layer, the blind hole being provided with a first conductive part formed by curing conductive paste, the first conductive part comprising oppositely arranged first and second end parts, the first end part being used for electrically connecting the connection pad; providing a second circuit substrate comprising a second circuit layer and a third circuit layer, the second circuit layer comprising a signal line; stacking and pressing the first and second circuit substrates, so that the second circuit layer is located between the first and third circuit layers, in the length direction of the first circuit substrate, the signal line is connected to part of the second end part, and in the thickness direction of the first circuit substrate, the orthogonal projection of the connection area of the second end part and the signal line on the connection pad is located within the connection pad, thereby obtaining the multilayer circuit board, and in the length direction of the first circuit substrate, the length L of the connection area and the diameter D of the second end part satisfy D / 3 < L < D.

6. The multilayer wiring board according to claim 5, wherein The second circuit layer further comprises a hole ring, the hole ring is arranged around the connection area, and the hole ring is provided with a first notch, and the signal line passes through the first notch.

7. The multilayer wiring board according to claim 6, wherein The hole ring is further provided with a plurality of second notches along the outer peripheral direction of the hole ring.

8. The multilayer wiring board according to claim 5, wherein The first circuit substrate further comprises a base layer, a fourth circuit layer and a dielectric layer, the first circuit layer, the dielectric layer, the fourth circuit layer and the base layer are sequentially stacked, the dielectric layer is provided with a second blind hole, the second blind hole is provided with a second conducting part, the material of the second conducting part is conductive paste, the second conducting part is electrically connected with the connecting pad, the base layer is provided with the first conducting part, and the first conducting part is further electrically connected with the second conducting part.

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