Vertical transistor fuse latch

Abstract

This application relates to vertical transistor fuse latches. An apparatus can include a substrate and a memory array coupled with the substrate. The apparatus can also include a latch configured to store information from fuses for the memory array. The latch can be at least partially within an additional substrate that is separate from and above the substrate. The latch can include a quantity of p-type vertical transistors and a quantity of n-type vertical transistors each disposed at least partially within the additional substrate above the substrate.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 396,341, entitled “Vertical Transistor Fuse Latches,” filed August 6, 2021, by Simsek-Ege et al., the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to vertical transistor fuse latches. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program states into the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for a long time, even without external power. Volatile memory devices (e.g., DRAM) lose their stored state when disconnected from external power. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a substrate; a memory array coupled to the substrate; and a latch configured to store information from a fuse for the memory array, the latch including a plurality of p-type vertical transistors and a plurality of n-type vertical transistors, each at least partially disposed within an additional substrate above the substrate.

[0007] Describe an apparatus. The apparatus may include: a memory array coupled to a substrate; a fuse for the memory array; and a latch at least partially located within an additional substrate above the substrate and configured to store information from the fuse. The latch may include: a first p-type vertical transistor including a gate terminal and a drain terminal; a first n-type vertical transistor including a gate terminal coupled to the gate terminal of the first p-type vertical transistor and a source terminal coupled to the drain terminal of the first p-type vertical transistor; a second p-type vertical transistor including a gate terminal and a drain terminal; and a second n-type vertical transistor including a gate terminal coupled to the gate terminal of the second p-type vertical transistor and a source terminal coupled to the drain terminal of the second p-type vertical transistor.

[0008] Describe an apparatus. The apparatus may include: a first substrate; a memory array coupled to and at least partially disposed on the first substrate; a first p-type vertical transistor of a latch configured to store information from a fuse for the memory array, the first p-type vertical transistor being at least partially located in a second substrate on the first substrate; and a first n-type vertical transistor of the latch, the first n-type vertical transistor being at least partially located in the second substrate on the first substrate. Attached Figure Description

[0009] Figure 1 This document describes examples of memory devices that support vertical transistor fuse latches, based on the examples disclosed herein.

[0010] Figure 2 This document describes examples of memory devices that support vertical transistor fuse latches, based on the examples disclosed herein.

[0011] Figure 3 This describes an instance of a latch based on the examples disclosed in this document.

[0012] Figure 4 This describes an instance of a latch based on the examples disclosed in this document.

[0013] Figure 5 This document describes examples of devices that support vertical transistor fuse latches, based on the examples disclosed herein. Detailed Implementation

[0014] In some memory devices, the memory array and supporting circuitry for operating the memory array may be disposed on a first substrate (which may be referred to as a base substrate), at least partially formed within the base substrate, or both. For example, latches storing fuse information for the memory array may be disposed on the base substrate, which may limit the size of the base substrate, reduce the area of ​​the base substrate available for other components, or both, and other advantages. According to the techniques described herein, latches storing fuse information for the memory array may comprise vertical transistors (e.g., pillar transistors, thin-film transistors) above the base substrate (e.g., composed of said vertical transistors). For example, one or more of the vertical transistors may be at least partially disposed within an additional substrate (or other material) separate from and above the base substrate. Arranging latches above the base substrate (e.g., at least partially within the additional substrate) frees up space on the base substrate for other components, allows for a smaller base substrate, or both, and other advantages.

[0015] The features of this disclosure are firstly in reference to Figure 1 and 2 The background of the described memory device is described. Features of this disclosure are described in the reference _________. Figures 3 to 4 The background latch is described in the description. These and other features of this disclosure are further referenced. Figure 5 The device description supporting the vertical transistor fuse latch is illustrated and referenced in the device description.

[0016] Figure 1 This document describes an example of a memory device 100 supporting a vertical transistor fuse latch, based on the examples disclosed herein. In some examples, the memory device 100 may be referred to as a memory chip, memory device, or electronic memory device. The memory device 100 may include one or more memory cells 105, each programmable to store different logic states (e.g., programmed to be one of a set of two or more possible states). For example, memory cell 105 may be operable to store one information bit at a time (e.g., logic 0 or logic 1). In some examples, memory cell 105 (e.g., a multi-level memory cell) may be operable to store more than one information bit at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some examples, memory cells 105 may be arranged in an array, which may be referred to as a memory array.

[0017] Memory cell 105 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material for storing charge representing a programmable state. In other memory architectures, other memory devices and components are possible. For example, a nonlinear dielectric material may be used. Memory cell 105 may include logic storage components, such as capacitor 130 and switching components 135. Capacitor 130 may be an example of a dielectric capacitor or a ferroelectric capacitor. Nodes of capacitor 130 may be coupled to a voltage source 140, which may be a plate reference voltage (e.g., Vpl) or ground (e.g., Vss).

[0018] Memory device 100 may include one or more access lines (e.g., one or more word lines 110 and one or more digital lines 115) arranged in a pattern such as a grid pattern. Access lines may be conductive lines coupled to memory cells 105 and used to perform access operations on memory cells 105. In some instances, word lines 110 may be referred to as row lines. In some instances, digital lines 115 may be referred to as column lines or bit lines. The terms access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, are interchangeable without loss of understanding or operability. Memory cells 105 may be located at the intersection of word lines 110 and digital lines 115.

[0019] For example, read and write operations can be performed on memory cell 105 by activating or selecting one or more access lines, such as word line 110 or digital line 115. A single memory cell 105 can be accessed at its intersection point by applying a bias voltage to word line 110 and digital line 115 (e.g., applying a voltage to word line 110 or digital line 115). The intersection point of word line 110 and digital line 115 in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 105.

[0020] The memory access unit 105 can be controlled by either row decoder 120 or column decoder 125. For example, row decoder 120 can receive a row address from local memory controller 160 and activate word line 110 based on the received row address. Column decoder 125 can receive a column address from local memory controller 160 and activate digital line 115 based on the received column address.

[0021] Selecting or deselecting memory cell 105 can be achieved by activating or deactivating switching component 135 using word line 110. Capacitor 130 can be coupled to digital line 115 using switching component 135. For example, when switching component 135 is deactivated, capacitor 130 can be isolated from digital line 115, and when switching component 135 is activated, capacitor 130 can be coupled to digital line 115.

[0022] Word line 110 may be a conductive line for electronic communication with memory cell 105, and may be used to perform access operations on memory cell 105. In some architectures, word line 110 may be coupled to the gate of switching component 135 of memory cell 105 and operable to control switching component 135 of memory cell 105. In some architectures, word line 110 may be coupled to a node of capacitor in memory cell 105 and memory cell 105 may not include a switching component.

[0023] Digital line 115 may be a conductive line connecting memory cell 105 and sensing component 145. In some architectures, memory cell 105 may be selectively coupled to digital line 115 during a portion of an access operation. For example, word line 110 of memory cell 105 and switching component 135 may be operable to couple and / or isolate capacitor 130 of memory cell 105 from digital line 115. In some architectures, memory cell 105 may be coupled to digital line 115.

[0024] Sensing component 145 is operable to detect a state (e.g., charge) stored on capacitor 130 of memory cell 105 and determine a logic state of memory cell 105 based on the stored state. Sensing component 145 may include one or more sensing amplifiers to amplify or otherwise convert signals originating from accessing memory cell 105. Sensing component 145 may compare the signal detected from memory cell 105 with a reference 150 (e.g., a reference voltage). The detected logic state of memory cell 105 may be provided as an output of sensing component 145 (e.g., to input / output 155) and may indicate the detected logic state to another component of the memory device including memory device 100.

[0025] The local memory controller 160 can control access to memory cells 105 via various components, such as row decoder 120, column decoder 125, and sensing component 145. In some instances, one or more of the row decoder 120, column decoder 125, and sensing component 145 may co-locate with the local memory controller 160. The local memory controller 160 is operable to: receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller associated with a host device, or another controller associated with memory device 100); translate the commands or data (or both) into information usable by memory device 100; perform one or more operations on memory device 100; and transfer data from memory device 100 to host device based on the performance of one or more operations. The local memory controller 160 can generate row signals and column address signals to activate target word line 110 and target digital line 115. The local memory controller 160 can also generate and control various voltages or currents used during operation of memory device 100. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ depending on the various operations discussed in the operating memory device 100.

[0026] The local memory controller 160 is operable to perform one or more access operations on one or more memory cells 105 of the memory device 100. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 160 in response to various access commands (e.g., from a host device). The local memory controller 160 is operable to perform other access operations not listed herein or other operations related to the operation of the memory device 100 that are not directly related to accessing memory cells 105.

[0027] Local memory controller 160 is operable to perform write operations (e.g., programming operations) on one or more memory cells 105 of memory device 100. During a write operation, the memory cells 105 of memory device 100 can be programmed to store a desired logical state. Local memory controller 160 can identify the target memory cell 105 to which a write operation is performed. Local memory controller 160 can identify a target word line 110 and a target digital line 115 coupled to the target memory cell 105 (e.g., the address of the target memory cell 105). Local memory controller 160 can activate the target word line 110 and the target digital line 115 (e.g., apply a voltage to the word line 110 or the digital line 115) to access the target memory cell 105. Local memory controller 160 can apply a specific signal (e.g., a write pulse) to the digital line 115 during a write operation to store a specific state (e.g., charge) in a capacitor 130 of memory cell 105. The pulse used as part of the write operation may include one or more voltage levels over a duration.

[0028] Local memory controller 160 is operable to perform read operations (e.g., sensing operations) on one or more memory cells 105 of memory device 100. During a read operation, a logical state stored in the memory cells 105 of memory device 100 can be determined. Local memory controller 160 can identify a target memory cell 105 on which the read operation is performed. Local memory controller 160 can identify a target word line 110 and a target digital line 115 coupled to the target memory cell 105 (e.g., the address of the target memory cell 105). Local memory controller 160 can activate the target word line 110 and the target digital line 115 (e.g., apply a voltage to the word line 110 or the digital line 115) to access the target memory cell 105. The target memory cell 105 can transfer a signal to a sensing component 145 in response to a bias applied to the access line. Sensing component 145 can amplify the signal. Local memory controller 160 can activate sensing component 145 (e.g., latch sensing component) and thereby compare the signal received from memory cell 105 with a reference 150. Based on the comparison, the sensing component 145 can determine the logic state stored in the storage unit 105.

[0029] In some instances, memory device 100 may include one or more fuses that store information (e.g., trimming information, system information, repair information) for operating a memory array containing memory cells 105. After memory device 100 is powered on, the information stored by the fuses may be transmitted (e.g., broadcast) to latches for storage and retrieval (e.g., via memory device 100). A latch may also be referred to as a latching circuit, latching assembly, or other suitable terms, and a latch configured to store information from a fuse may also be referred to as a fuse latch, fuse latching circuit, fuse latching assembly, or other suitable terms. Information stored by or transmitted from a fuse may be referred to as fuse information.

[0030] In some other technologies and devices, latches may be disposed on the same substrate (e.g., a base substrate) that includes other components of the memory array and memory device 100, which may be an inefficient use of the base substrate. According to the techniques described herein, latches containing vertical transistors may be disposed on the base substrate. For example, latches may be at least partially disposed within an additional substrate (or other material) above the base substrate, which may allow for the placement of other components on the base substrate, allow for a reduction in the size of the base substrate, or both, and other advantages.

[0031] Figure 2 This document describes an example of a memory device 200 supporting a vertical transistor fuse latch, based on the examples disclosed herein. The memory device 200 may include a base substrate 205 (e.g., a silicon substrate) and an upper substrate 210 (e.g., a polycrystalline silicon substrate, a silicon-germanium (SiGe) substrate, or an indium gallium zinc oxide (IGZO) substrate). In some examples, the upper substrate 210 may be separated from the base substrate 205 by one or more materials. In such examples, the upper substrate 210 may not directly contact the base substrate 205, while in other examples, the upper substrate 210 may directly contact the base substrate 205. For illustration, aspects of the memory device 200 may be described with reference to the x, y, and z directions of coordinate system 201. In some examples, the z direction may describe a direction perpendicular to the surface of the base substrate 205 (e.g., a surface in the xy plane, a surface on which other materials may be deposited or above). As illustrated by their corresponding cross-sections in the xz plane, the base substrate 205 and the upper substrate 210 may extend a certain distance in the y and x directions.

[0032] Although described in relation to a substrate and an upper substrate, the techniques described herein can be implemented using various other layers of other materials.

[0033] The substrate 205 may include regions 215 and 225, each extending in the y-direction. Region 215, also referred to as a peripheral site, may include or be coupled to logic and circuitry for operating the memory array 230. For example, region 215 may be coupled (e.g., contact) to memory bank logic, pitch cells, sense amplifiers, sub-word line drivers (SWDs), or combinations thereof, and other components. Region 225 may include or be coupled to the memory array 230, which may be disposed on or at least partially within the substrate of region 225. For example, capacitor components (e.g., capacitors) for memory cells of the memory array 230 may be on region 225, and various access lines (e.g., word lines, digital lines) for the memory cells may be at least partially disposed on or within the substrate of region 225. However, other configurations of the memory device 200 are contemplated and are within the scope of this disclosure. In some instances, input-output (I / O) circuitry for communicating with another device (e.g., a host device) may be located on the upper substrate 210 (e.g., within or coupled to the back-end process (BEOL) portion 250). The BEOL portion 250 may comprise various materials (e.g., metallic materials, dielectric materials) and may provide interconnections (e.g., contacts, insulating layers, metal layers, bonding sites) for individual components of the memory device 200 (e.g., chip-to-package connections).

[0034] The memory device 200 may also include a set of latches 235, which may be latches containing at least one vertical transistor. Latches 235 may also be referred to as vertical transistor latches or thin-film transistor (TFT) latches, and other suitable terms. Latches 235 may be configured to store information from a fuse coupled to the latches 235 (or information that may already be stored in the fuse). For various reasons (e.g., due to process variations), using vertical transistors for latches 235, in contrast to non-vertical transistors, allows latches 235 to be at least partially disposed on or within the upper substrate 210, freeing up space on the base substrate 205 that would otherwise be available for latches 235 in other different embodiments.

[0035] Reference is now made to latch 235-a, which may be an example of latch 235. Latch 235-a may be configured to store (e.g., retain, save) information from the fuse (e.g., output status).

[0036] Latch 235-a may contain a number of vertical transistor groups, as shown in the extended diagram. For example, latch 235-a may contain vertical transistor groups TG1 to TG6. Each transistor group may contain one or more vertical transistors, which in some instances may be connected in parallel and operate in a collective (e.g., unified) manner (e.g., essentially as a single vertical transistor). For example, such as Figure 2 As shown, each transistor group may contain four vertical transistors connected in parallel. However, other numbers of vertical transistors per transistor group are contemplated and within the scope of this disclosure. Using multiple vertical transistors in parallel allows for the use of thinner channels (without reducing current capacity), which in turn improves the current properties of the materials used to form the vertical transistors (compared to thicker channels). The use of multiple vertical transistors per transistor group increases the reliability of latch 235-a (e.g., by reducing the incidence of soft errors) and other advantages.

[0037] A vertical transistor may include a channel portion (e.g., at least partially formed of a polycrystalline semiconductor such as polysilicon, SiGe, or IGZO) and a gate portion (e.g., a conductor such as titanium (Ti), titanium nitride (TiN), ruthenium (Ru), tungsten (W), or molybdenum (Mo), formed adjacent to, along, or at least partially surrounding the channel portion) formed by one or more pillars or other structures. The gate portion may be configured to activate the channel portion based on a voltage applied to the gate portion (e.g., to open or close a conductive path in the channel portion). For example, the gate portion (denoted as G) may be configured to activate the channel between the drain portion (denoted as D) and the source portion (denoted as S) of the vertical transistor, allowing current to flow through the channel. The gate, drain, and source portions of the vertical transistor may also be referred to as a gate terminal, a drain terminal, and a source terminal, respectively. A vertical transistor may also be referred to as a pillar transistor, a TFT, or other suitable terminology. Although shown as a source portion on top and a drain portion on the bottom, portions of a vertical transistor may be based on wiring and voltage reversal applied to the vertical transistor.

[0038] In some instances, latch 235-a may include an n-type vertical transistor and a p-type vertical transistor. The n-type vertical transistor may be a transistor comprising an n-doped material, a p-doped material, and a stack of n-doped materials (e.g., an n-doped drain portion, a p-doped gate portion, and an n-doped source portion). Alternatively (e.g., in the case of a polysilicon channel), the source and drain portions may be n-doped portions of polysilicon, and the gate portion (e.g., a metal sidewall region) may be undoped. Therefore, the n-type vertical transistor can use an electron flow to carry charge and thus can exhibit characteristics (and operate similarly) to other (e.g., non-vertical) instances of n-type transistors. The p-type vertical transistor may be a transistor comprising a p-doped material, an n-doped material, and a stack of p-doped materials (e.g., a p-doped drain portion, an n-doped gate portion, and a p-doped source portion). Alternatively (e.g., in the case of a polysilicon channel), the source and drain portions may be p-doped portions of polysilicon, and the gate portion (e.g., a metal sidewall region) may be undoped. Therefore, a p-type vertical transistor can use a hole flow to carry charge and thus exhibit characteristics (and operate similarly) to other (e.g., non-vertical) instances of a p-type transistor. Using a p-type vertical transistor in latch 235 reduces the power consumption of latch 235 (e.g., because the gate voltage required to activate a p-type vertical transistor is lower than that of an n-type vertical transistor).

[0039] Latch 235-a may be coupled to control circuitry 240, which may include a set of switching components, such as vertical transistors (e.g., within upper substrate 210) or non-vertical transistors (e.g., disposed on and / or at least partially disposed within substrate 205). Control circuitry 240 may be controlled by a select (SEL) signal (e.g., which may be associated with or from a controller, such as local memory controller 160) and may be configured to selectively couple latch 235-a to corresponding fuses (e.g., from a fuse array for memory array 230) based on the select signal. For example, the select signal may be applied to the gate terminals of transistor groups TG1 and TG2, which may conduct current based on applied signals Fuse_T and Fuse_B, which may be output from one or more fuses or control circuitry. In some instances, the input lines of Fuse_T and Fuse_B may be shared by multiple latches 235. In some instances, the fuse array may be on region 215 of substrate 205.

[0040] Latch 235-a can be configured to store the state of input signals (e.g., Fuse_T and Fuse_B) at output node 245. Specifically, latch 235-a may include transistor groups TG3 and TG4, which may include corresponding gate terminals coupled together (e.g., via conductive lines) and configured to receive input signals (e.g., Fuse_B) from control circuitry 240. The gate terminals of transistor groups TG3 and TG4 may also be coupled to terminals (e.g., drain terminals) of transistor group TG5 and to terminals (e.g., source terminals) of transistor group TG6. Transistor group TG3 may include a first set of terminals (e.g., source terminals) coupled to a voltage source Vdd and a second set of terminals (e.g., drain terminals) coupled to transistor group TG4. Transistor group TG4 may include a first set of terminals (e.g., drain terminals) coupled to a voltage source Vss and a second set of terminals (e.g., source terminals) coupled to transistor group TG3. Voltage source Vdd may have a voltage higher than voltage source Vss. In some instances, voltage source Vdd has a positive voltage and voltage source Vss has a negative voltage.

[0041] Latch 235-a may also include transistor groups TG5 and TG6, which may include respective gate terminals coupled together (e.g., via conductive lines) and configured to receive input signals (e.g., Fuse_T) from control circuitry 240. The gate terminals of transistor groups TG5 and TG6 may also be coupled to terminals (e.g., drain terminals) of transistor group TG3 and to terminals (e.g., source terminals) of transistor group TG4. Transistor group TG5 may include a first set of terminals (e.g., source terminals) coupled to a voltage source Vdd and a second set of terminals (e.g., drain terminals) coupled to transistor group TG6. Transistor group TG6 may include a first set of terminals (e.g., drain terminals) coupled to a voltage source Vss and a second set of terminals (e.g., source terminals) coupled to transistor group TG5.

[0042] Therefore, the gate terminals of transistor groups TG3 and TG4 can be coupled together, the drain terminals of transistor groups TG3 and TG5 can be coupled to the corresponding source terminals of transistor groups TG4 and TG6, and the gate terminals of transistor groups TG5 and TG6 can be coupled together. Figure 2 Other links described in the document.

[0043] By using a vertical transistor for latch 235, latch 235 can be at least partially housed within upper substrate 210. Therefore, space on base substrate 205 originally intended for latch 235 can be reserved for other components, the size of the base substrate can be reduced, or both, and other advantages can be achieved.

[0044] Figure 3This document describes an example of a latch 300 supporting a vertical transistor fuse latch, based on the examples disclosed herein. Latch 300 may be used as a reference. Figure 2 The latch 235 described herein may therefore include vertical transistors positioned within an upper substrate (or other material) above a base substrate. For illustration, aspects of the latch 300 may be described with reference to the x, y, and z directions of coordinate system 301. In some instances, the z direction may refer to a direction perpendicular to a surface of the base substrate (e.g., a surface in the xy plane, a surface on or above which other material may be deposited). Conductive lines (illustrated by various shading patterns) connecting the transistor group of the latch 300 may extend through the upper substrate in a three-dimensional (3D) manner. For example, Figure 3 This demonstrates the first option of routing conductive lines behind or in front of each other in the y-direction. Figure 3 In this context, a conductive line that follows another conductive line in the y-direction is shown as disappearing below that conductive line. Conductive lines can also be called connections, conductive traces, electrical traces, or other suitable terms.

[0045] Latch 300 can be used as a reference. Figure 2 The described latch 235-a is an example, and therefore may include transistor groups TG3 to TG6. Transistor groups TG3 to TG6 may be as follows: Figure 2 The logical connection is shown and described as described. However, conductive lines that could originally cross a single plane can be positioned in different planes. For example, at least a first portion (e.g., portion P0) of conductive line L1, which couples the drain terminal of transistor group TG3 to the source terminal of transistor group TG4 (and the gate terminals of transistor groups TG5 and TG6), can be positioned in front of at least a first portion (about the y-direction) of conductive line L2, which couples the gate terminals of transistor groups TG3 and TG4 to the drain terminal of transistor group TG5 and the source terminal of transistor group TG6. In some instances, conductive line L1 can be coupled to a first switching component of the control circuit (e.g., transistor group TG1) and conductive line L2 can be coupled to a second switching component of the control circuit (e.g., transistor group TG2).

[0046] Alternatively or alternatively, at least one second portion (e.g., portion P1) of conductive line L1 may be positioned in front of at least one second portion of conductive line L2 (about the y-direction). Alternatively or alternatively, at least one third portion (e.g., portion P2) of conductive line L1 may be positioned behind at least one third portion of conductive line L2 (about the y-direction). Portion P0 may be positioned in the x-direction between transistor groups TG3 and TG4; portion P1 may be positioned in the x-direction between transistor groups TG4 and TG5; and portion P2 may be positioned in the x-direction between transistor groups TG5 and TG6.

[0047] In some instances, one or more conductive lines can be used to couple the terminals of vertical transistors in a transistor group. For example, conductive line M1 can couple the drain terminal of a vertical transistor in transistor group TG3, and K0 can couple the source terminal of a vertical transistor in transistor group TG3. Similar terminal connection conductive lines within transistor groups can be used for other transistor groups TG4 to TG6. Using conductive lines M1 and K0 allows the vertical transistor in the transistor group to be used as or operate as a single vertical transistor. For example, conductive line M1 can couple the drain terminal of a vertical transistor in transistor group TG3 such that the drain terminals collectively form the drain terminal of transistor group TG3. Similarly, conductive line K0 can couple the source terminal of a vertical transistor in transistor group TG3 such that the source terminals collectively form the source terminal of transistor group TG3.

[0048] Therefore, the conductive lines can be extended in a 3D manner (e.g., within an upper substrate or other material) to connect to the vertical transistors in latch 300. However, other configurations and orientations of the conductive lines are contemplated and are within the scope of this disclosure.

[0049] Figure 4 This document describes an example of a latch 400 supporting a vertical transistor fuse latch, based on the examples disclosed herein. Latch 400 may be used as a reference. Figure 2 The latch 235 described herein may therefore include a vertical transistor positioned within an upper substrate (or other material) above a base substrate. For illustration, aspects of the latch 400 may be described with reference to the x, y, and z directions of coordinate system 401. In some instances, the z direction may refer to a direction perpendicular to a surface of the base substrate (e.g., a surface in the xy plane, a surface on or above which other material may be deposited). Conductive lines (illustrated by various shading patterns) connecting the vertical transistors of the latch 400 may extend through the upper substrate in a 3D manner. For example, Figure 4 This demonstrates a second option: routing the conductive lines behind or in front of each other in the y-direction. Figure 4 In the diagram, conductive lines following other conductive lines in the y-direction are shown as disappearing below other conductive lines.

[0050] Latch 400 can be used as a reference. Figure 2 The described latch 235-a is an example, and therefore may include transistor groups TG3 to TG6. Transistor groups TG3 to TG6 may be as follows: Figure 2The logical connection is shown and described as described. However, conductive lines that could originally cross a single plane can be positioned in different planes. For example, at least a first portion (e.g., portion P0) of conductive line L1, which couples the drain terminal of transistor group TG3 to the source terminal of transistor group TG4 (and the gate terminals of transistor groups TG5 and TG6), can be positioned in front of at least a first portion (about the y-direction) of conductive line L2, which couples the gate terminals of transistor groups TG3 and TG4 to the drain terminal of transistor group TG5 and the source terminal of transistor group TG6. In some instances, conductive line L1 can be coupled to a first switching component of the control circuit (e.g., transistor group TG1) and conductive line L2 can be coupled to a second switching component of the control circuit (e.g., transistor group TG2).

[0051] Alternatively, at least one second portion (e.g., portion P1) of conductive line L1 may be positioned in front of at least one second portion of conductive line L2 (about the y-direction). Alternatively, at least one third portion (e.g., portion P2) of conductive line L1 may be positioned behind at least one third portion of conductive line L2 (about the y-direction). Portion P0 may be positioned in the x-direction between transistor groups TG3 and TG4; portion P1 may be positioned in the x-direction between transistor groups TG4 and TG5; and portion P2 may be positioned in the x-direction between transistor groups TG5 and TG6.

[0052] In some instances, one or more conductive lines may be used to couple the terminals of vertical transistors within a transistor group. For example, conductive line M1 may couple the drain terminal of a vertical transistor in transistor group TG3, and K0 may couple the source terminal of a vertical transistor in transistor group TG3. Similar terminal connection conductive lines within transistor groups may be used for other transistor groups TG4 through TG6.

[0053] Therefore, the conductive lines can be extended in a 3D manner (e.g., within an upper substrate or other material) to connect the vertical transistors in the latch 400. However, other configurations and orientations of the conductive lines are contemplated and are within the scope of this disclosure.

[0054] Figure 5 This document describes an example of a device 500 supporting a vertical transistor fuse latch, based on the examples disclosed herein. Device 500 may be used as a reference. Figure 2An example of a portion of the described memory device 200. Device 500 may include a substrate 505 and a latch 510 at least partially disposed within an upper substrate (or other material). For illustration, aspects of the latch 510 may be described with reference to the x, y, and z directions of coordinate system 501. In some instances, the z direction may describe a direction perpendicular to a surface of the substrate 505 (e.g., a surface in the xy plane, a surface on or above which other material may be deposited). Conductive lines (illustrated by various shading patterns) connecting vertical transistors of the latch 510 may extend through the upper substrate in a 3D manner. For example, Figure 5 This demonstrates a third option: routing the conductive lines behind or in front of each other in the y-direction. Figure 5 In the diagram, conductive lines following other conductive lines in the y-direction are shown as disappearing below other conductive lines.

[0055] Figure 5 The connection between latch 510 and control circuit 515 can also be described, with control circuit 515 coupled to substrate 505 (e.g., at least partially disposed within substrate 505).

[0056] The latch 510 can be used as a reference. Figure 2 The described latch 235-a is an example and therefore may include transistor groups TG3 to TG6. Transistor groups TG3 to TG6 may be as follows: Figure 2 The logical connection is shown and described as described. However, conductive lines that could originally cross a single plane can be positioned in different planes. For example, at least a first portion (e.g., portion P0) of conductive line L1, which couples the drain terminal of transistor group TG3 to the source terminal of transistor group TG4 (and the gate terminals of transistor groups TG5 and TG6), can be positioned behind at least a first portion (about the y-direction) of conductive line L2, which couples the gate terminals of transistor groups TG3 and TG4 to the drain terminal of transistor group TG5 and the source terminal of transistor group TG6. Conductive line L1 can be coupled to transistor group TG1, and conductive line L2 can be coupled to transistor group TG2.

[0057] Alternatively or alternatively, at least one second portion (e.g., portion P1) of conductive line L1 may be positioned in front of at least one second portion of conductive line L2 (about the y-direction). Alternatively or alternatively, at least one third portion (e.g., portion P2) of conductive line L1 may be positioned in front of at least one third portion of conductive line L2 (about the y-direction). Portion P0 may be positioned in the x-direction between transistor groups TG3 and TG4; portion P1 may be positioned in the x-direction between transistor groups TG4 and TG5; and portion P2 may be positioned in the x-direction between transistor groups TG5 and TG6.

[0058] Conductive lines L1 and L2 can also couple latch 510 to control circuit 515, which is a reference. Figure 2 The described control circuit 240 may function in an example or similar manner. For instance, conductive line L1 may couple the gate terminals of transistor groups TG5 and TG6 to switching component 520-a, which may be a non-vertical transistor (e.g., at least partially disposed on substrate 505) or a vertical transistor (e.g., disposed on substrate 505, possibly at least partially within the same upper substrate as latch 510). Conductive line L2 may couple the gate terminals of transistor groups TG3 and TG4 to switching component 520-b, which may be a non-vertical transistor (e.g., at least partially disposed on substrate 505) or a vertical transistor (e.g., disposed on a substrate, possibly at least partially within the same upper substrate as latch 510). Therefore, switching component 520 may be 1) a non-vertical transistor at least partially disposed within substrate 505 as shown, or 2) a vertical transistor disposed on substrate 505 (e.g., non-vertical transistor at least partially disposed within substrate 505 as shown). Figure 2 (As shown in the diagram). As described, the switching component 520 can be controlled (e.g., via a selection signal) to selectively apply signals Fuse_T and Fuse_B (which may come from the fuse corresponding to latch 510) to latch 510.

[0059] In some instances, one or more conductive lines may be used to couple the terminals of vertical transistors within a transistor group. For example, conductive line M1 may couple the drain terminal of a vertical transistor in transistor group TG3, and K0 may couple the source terminal of a vertical transistor in transistor group TG3. Similar terminal connection conductive lines within transistor groups may be used for other transistor groups TG4 through TG6.

[0060] Therefore, the conductive lines can extend in a 3D manner (e.g., within an upper substrate or other material) to connect the vertical transistor in latch 510 to the control circuitry 515. However, other configurations and orientations of the conductive lines are contemplated and are within the scope of this disclosure.

[0061] Describe an apparatus. The apparatus may include: a substrate; a memory array coupled to the substrate; and a latch configured to store information from a fuse for the memory array, the latch including a plurality of p-type vertical transistors and a plurality of n-type vertical transistors, each at least partially disposed within an additional substrate above the substrate.

[0062] In some instances of the device, the plurality of p-type vertical transistors includes a first p-type vertical transistor coupled to a second p-type vertical transistor. In some instances of the device, the plurality of n-type vertical transistors includes a first n-type vertical transistor coupled to a second n-type vertical transistor.

[0063] In some instances, the device may include a first conductive line coupling the gate terminal of the first p-type vertical transistor to the gate terminal of the first n-type vertical transistor. In some instances, the device may include a second conductive line coupling the gate terminal of the second p-type vertical transistor to the gate terminal of the second n-type vertical transistor.

[0064] In some instances, the device may include a first conductive line coupling the source terminal of the first n-type vertical transistor to the drain terminal of the first p-type vertical transistor. In some instances, the device may include a second conductive line coupling the source terminal of the second n-type vertical transistor to the drain terminal of the second p-type vertical transistor.

[0065] In some instances, the device may include: a first conductive line coupled to the source terminal of the first n-type vertical transistor and the drain terminal of the first p-type vertical transistor and the gate terminal of the second n-type vertical transistor and the gate terminal of the second p-type vertical transistor; and a second conductive line coupled to the source terminal of the second n-type vertical transistor and the drain terminal of the second p-type vertical transistor and the gate terminal of the first n-type vertical transistor and the gate terminal of the first p-type vertical transistor.

[0066] In some instances, the device may include a first plurality of conductive lines, wherein each of the first plurality of conductive lines is coupled to the source terminals of a corresponding group of a plurality of p-type vertical transistors that can be connected in parallel. In some instances, the device may include a second plurality of conductive lines, wherein each of the second plurality of conductive lines is coupled to the drain terminals of a corresponding group of a plurality of n-type vertical transistors that can be connected in parallel.

[0067] In some instances, the device may include a set of transistors disposed on the substrate and configured to selectively couple the latch to the fuse. In some instances of the device, the memory array includes memory cells positioned on a first region of the substrate. In some instances of the device, the latch may be positioned on a second region of the substrate.

[0068] In some instances, the device may include logic disposed on the second region of the substrate and configured to operate the memory array. In some instances of the device, the memory array comprises a DRAM array.

[0069] Describe another device. The device may include: a memory array coupled to a substrate; a fuse for the memory array; and a latch, at least partially located in an additional substrate above the substrate and configured to store information from the fuse, the latch including: a first p-type vertical transistor including a gate terminal and a drain terminal; a first n-type vertical transistor including a gate terminal coupled to the gate terminal of the first p-type vertical transistor and a source terminal coupled to the drain terminal of the first p-type vertical transistor; a second p-type vertical transistor including a gate terminal and a drain terminal; and a second n-type vertical transistor including a gate terminal coupled to the gate terminal of the second p-type vertical transistor and a source terminal coupled to the drain terminal of the second p-type vertical transistor.

[0070] In some instances, the device may include a conductive wire network coupling the first p-type vertical transistor, the first n-type vertical transistor, the second p-type vertical transistor, and the second n-type vertical transistor, wherein the conductive wire network extends three-dimensionally through the additional substrate.

[0071] In some instances, the device may include a set of transistors coupled to the substrate and configured to selectively couple the fuse to the respective gate terminals of the first p-type vertical transistor and the first n-type vertical transistor.

[0072] In some embodiments, the device may include a first conductive line coupling the source terminal of the first n-type vertical transistor and the drain terminal of the first p-type vertical transistor to the gate terminal of the second n-type vertical transistor and the gate terminal of the second p-type vertical transistor. In some embodiments, the device may include a second conductive line coupling the source terminal of the second n-type vertical transistor and the drain terminal of the second p-type vertical transistor to the gate terminal of the first n-type vertical transistor and the gate terminal of the first p-type vertical transistor.

[0073] In some instances, the device may include a first negative voltage supply coupled to the drain terminal of the first n-type vertical transistor and a second negative voltage supply coupled to the drain terminal of the second n-type vertical transistor. In some instances, the device may include a first positive voltage supply coupled to the source terminal of the first p-type vertical transistor and a second positive voltage supply coupled to the source terminal of the second p-type vertical transistor.

[0074] In some instances of the device, the memory array may be at least partially disposed within a first region of the substrate. In some instances, the latch may be located on a second region of the substrate.

[0075] Another device is described. The device may include: a first substrate; a memory array coupled to and at least partially disposed on the first substrate; a first p-type vertical transistor of a latch configured to store information from a fuse for the memory array, the first p-type vertical transistor being at least partially located in a second substrate on the first substrate; and a first n-type vertical transistor of the latch, the first n-type vertical transistor being at least partially located in the second substrate on the first substrate.

[0076] In some instances, the device may include a first conductive line coupling the gate terminal of the first p-type vertical transistor to the gate terminal of the first n-type vertical transistor. In some instances, the device may include a second conductive line coupling the drain terminal of the first p-type vertical transistor to the source terminal of the first n-type vertical transistor.

[0077] In some instances, the device may include a second p-type vertical transistor of the latch, the second p-type vertical transistor being at least partially located within a second substrate that may be situated above the first substrate. In some instances, the device may include a second n-type vertical transistor of the latch, the second n-type vertical transistor being at least partially located within a second substrate that may be situated above the first substrate.

[0078] In some instances, the device may include a third conductive line coupling the gate terminal of the second p-type vertical transistor to the gate terminal of the second n-type vertical transistor. In some instances, the device may include a fourth conductive line coupling the drain terminal of the second p-type vertical transistor to the source terminal of the second n-type vertical transistor.

[0079] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal can represent a bus of signals, where the bus can have various bit widths.

[0080] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) with each other if there exists any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0081] The term "coupling" refers to the condition that changes from an open-circuit relationship between components (where signals cannot currently be transmitted between components via a conductive path) to a closed-circuit relationship between components (where signals can be transmitted between components via a conductive path). When a component, such as a controller, couples other components together, the component triggers a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0082] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, when a switch positioned between two components is turned on, the components separated by the switch are isolated from each other. When a controller isolates two components, the controller causes a change that prevents signals from flowing between the components using the conductive paths previously allowed for signal flow.

[0083] As used herein, the terms "layer" or "level" refer to a hierarchical or sheet-like geometric structure. Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0084] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0085] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0086] The descriptions herein, illustrated in conjunction with the accompanying drawings, depict exemplary configurations and do not represent all implementable or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" rather than "preferred" or "superior to other examples." Detailed descriptions include specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concept of the described examples.

[0087] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by having the reference numeral followed by a dash and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, without regard to the second reference numeral.

[0088] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located in various locations, including portions distributed such that the functions are implemented in different physical locations.

[0089] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in alternative examples, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0090] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be interpreted as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be understood in the same way as the phrase "at least partially based on".

[0091] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, optical fiber, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, optical fiber, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. The combination above is also included within the scope of computer-readable media.

[0092] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure will be made, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Substrate, A memory array coupled to the substrate; and A latch configured to store information from a fuse for the memory array, the latch being disposed within an additional substrate above the substrate and comprising: A plurality of p-type vertical transistors, each of the plurality of p-type vertical transistors comprising: a corresponding gate terminal of a plurality of first gate terminals coupled together, a corresponding drain terminal of a plurality of first drain terminals coupled together, and a corresponding source terminal of a plurality of first source terminals coupled together; and A plurality of n-type vertical transistors, each of the plurality of n-type vertical transistors including a corresponding gate terminal of a second plurality of gate terminals coupled together.

2. The device of claim 1, wherein the plurality of p-type vertical transistors comprises: A first p-type vertical transistor and a second p-type vertical transistor, each of the first p-type vertical transistor and the second p-type vertical transistor being coupled to a positive voltage supply, and wherein the plurality of n-type vertical transistors include: A first n-type vertical transistor and a second n-type vertical transistor, each of which is coupled to a negative voltage supply.

3. The device according to claim 2, further comprising: A first conductive line is coupled to the gate terminal of the first p-type vertical transistor and the gate terminal of the first n-type vertical transistor. and The second conductive line couples the gate terminal of the second p-type vertical transistor to the gate terminal of the second n-type vertical transistor.

4. The device of claim 1, wherein the plurality of p-type vertical transistors includes a first p-type vertical transistor, and wherein the plurality of n-type vertical transistors includes a first n-type vertical transistor, the device further comprising: A first conductive line is coupled to the source terminal of the first n-type vertical transistor and the drain terminal of the first p-type vertical transistor; and The second conductive line couples the source terminal of the second n-type vertical transistor to the drain terminal of the second p-type vertical transistor.

5. The device of claim 1, wherein the plurality of p-type vertical transistors includes a first p-type vertical transistor, and wherein the plurality of n-type vertical transistors includes a first n-type vertical transistor, the device further comprising: A first conductive line couples the source terminal of the first n-type vertical transistor and the drain terminal of the first p-type vertical transistor to the gate terminal of the second n-type vertical transistor and the gate terminal of the second p-type vertical transistor; and The second conductive line couples the source terminal of the second n-type vertical transistor and the drain terminal of the second p-type vertical transistor to the gate terminal of the first n-type vertical transistor and the gate terminal of the first p-type vertical transistor.

6. The device according to claim 1, further comprising: A set of transistors disposed on the substrate and configured to selectively couple the latch to the fuse.

7. The device of claim 1, wherein the memory array includes memory cells positioned on a first region of the substrate, and wherein the latch is positioned on a second region of the substrate.

8. The device according to claim 7, further comprising: The logic is disposed on the second region of the substrate and configured to operate the memory array.

9. The device of claim 1, wherein the memory array comprises a dynamic random access memory (DRAM) array.

10. An apparatus comprising: A memory array coupled to a substrate; A fuse, which is used in the memory array; and A latch, at least partially located within an additional substrate above the said substrate and configured to store information from the fuse, the latch comprising: The first p-type vertical transistor includes a gate terminal and a drain terminal; A first n-type vertical transistor includes a gate terminal coupled to the gate terminal of the first p-type vertical transistor and a source terminal coupled to the drain terminal of the first p-type vertical transistor. The second p-type vertical transistor includes a gate terminal and a drain terminal; and The second n-type vertical transistor includes: A gate terminal coupled to the gate terminal of the second p-type vertical transistor, coupled to the drain terminal of the first p-type vertical transistor, and coupled to the source terminal of the first n-type vertical transistor; and A source terminal coupled to the drain terminal of the second p-type vertical transistor, coupled to the gate terminal of the first p-type vertical transistor, and coupled to the gate terminal of the first n-type vertical transistor.

11. The device according to claim 10, further comprising: A conductive network coupling the first p-type vertical transistor, the first n-type vertical transistor, the second p-type vertical transistor, and the second n-type vertical transistor, wherein the conductive network extends three-dimensionally through the additional substrate.

12. The device according to claim 11, further comprising: A set of transistors coupled to the substrate and configured to selectively couple the fuse to the respective gate terminals of the first p-type vertical transistor and the first n-type vertical transistor.

13. The device according to claim 10, further comprising: A first conductive line is coupled to the source terminal of the first n-type vertical transistor and the drain terminal of the first p-type vertical transistor and the gate terminal of the second n-type vertical transistor and the gate terminal of the second p-type vertical transistor. and A second conductive line is coupled to the source terminal of the second n-type vertical transistor and the drain terminal of the second p-type vertical transistor, and to the gate terminal of the first n-type vertical transistor and the gate terminal of the first p-type vertical transistor.

14. The device according to claim 10, further comprising: A first negative voltage supply coupled to the drain terminal of the first n-type vertical transistor and a second negative voltage supply coupled to the drain terminal of the second n-type vertical transistor; and A first positive voltage supply coupled to the source terminal of the first p-type vertical transistor and a second positive voltage supply coupled to the source terminal of the second p-type vertical transistor.

15. The device of claim 10, wherein the memory array is at least partially disposed within a first region of the substrate, and wherein the latch is disposed over a second region of the substrate.

16. An apparatus comprising: First substrate; A memory array coupled to the first substrate and at least partially disposed on the first substrate; A first p-type vertical transistor of a latch, the latch being configured to store information from a fuse for the memory array, the first p-type vertical transistor being at least partially located within a second substrate above the first substrate; The latch has a first n-type vertical transistor, which is at least partially located within the second substrate above the first substrate; and The second n-type vertical transistor includes: A gate terminal coupled to the drain terminal of the first p-type vertical transistor and coupled to the source terminal of the first n-type vertical transistor; and The source terminal coupled to the gate terminal of the first p-type vertical transistor.

17. The device according to claim 16, further comprising: A first conductive line is coupled to the gate terminal of the first p-type vertical transistor and the gate terminal of the first n-type vertical transistor. and A second conductive line couples the drain terminal of the first p-type vertical transistor to the source terminal of the first n-type vertical transistor.

18. The device according to claim 17, further comprising: The latch has a second p-type vertical transistor, which is at least partially located within the second substrate above the first substrate; and The second n-type vertical transistor is at least partially located within the second substrate above the first substrate.

19. The apparatus of claim 18, further comprising: A third conductive line is coupled to the gate terminal of the second p-type vertical transistor and the gate terminal of the second n-type vertical transistor; and A fourth conductive line, which couples the drain terminal of the second p-type vertical transistor to the source terminal of the second n-type vertical transistor.

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