Laterally diffused metal oxide semiconductor device with multi-thickness buffer dielectric layer

Abstract

The present invention relates to a laterally diffused metal oxide semiconductor device having a multi-thickness buffer dielectric layer. A structure for a laterally diffused metal oxide semiconductor device and a method for forming the structure for the laterally diffused metal oxide semiconductor device are provided. The structure includes: a drift well located in a semiconductor substrate; a source region and a drain region located in the semiconductor substrate; a gate dielectric layer located on the semiconductor substrate; and a buffer dielectric layer located on the semiconductor substrate above the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first segment extending from the second side edge to the first side edge, and a plurality of second segments extending from the second side edge toward the first side edge. The first segment has a first thickness, and the second segment has a second thickness less than the first thickness. The gate electrode includes respective portions overlapping the buffer dielectric layer and overlapping the gate dielectric layer.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices and integrated circuit fabrication, and more particularly to structures for laterally diffused metal oxide semiconductor devices and methods of forming structures for laterally diffused metal oxide semiconductor devices. Background Art

[0002] For example, high-voltage integrated circuits used in microwave / RF power amplifiers often require specialized circuit technology capable of withstanding higher voltages. Laterally diffused metal oxide semiconductor (LDMOS) devices, also known as extended drain metal oxide semiconductor (EDMOS) devices, are designed to handle these higher voltages by incorporating additional transistor features that facilitate higher voltage handling capabilities, such as a drift well that provides an extended drain. LDMOS devices can be used, for example, in high-voltage power switches.

[0003] Reduced surface field (RESURF) technology can be used to provide a laterally diffused metal oxide semiconductor device with low characteristic on-resistance and high breakdown voltage. Laterally diffused metal oxide semiconductor devices can include a thick field oxide layer embedded in a drift well between the source and the drain. The field oxide layer must be formed to have a thickness that reflects the expected operating voltage. The thickness of the field oxide layer increases commensurately with the expected operating voltage. The top layer can be formed as an oppositely doped region in the drift well below the field oxide layer to reduce the characteristic on-resistance while maintaining a high breakdown voltage. The current flowing between the source and the drain must pass through the field oxide layer and the drift well around the top layer, which may cause current congestion near the corner of the field oxide layer and the top layer.

[0004] There is a need for improved structures for laterally diffused metal oxide semiconductor devices and methods of forming structures for laterally diffused metal oxide semiconductor devices. Summary of the Invention

[0005] In one embodiment, a structure for a laterally diffused metal oxide semiconductor device is provided. The structure includes: a semiconductor substrate; a drift well located in the semiconductor substrate; a source region and a drain region located in the semiconductor substrate; a gate dielectric layer located on the semiconductor substrate; and a buffer dielectric layer located on the semiconductor substrate above the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first segment extending from the second side edge to the first side edge, and a plurality of second segments extending from the second side edge toward the first side edge. The first segment has a first thickness, and each of the second segments has a second thickness less than the first thickness. The structure also includes a gate electrode located laterally between the source region and the drain region. The gate electrode includes a first portion overlapping the buffer dielectric layer and a second portion overlapping the gate dielectric layer.

[0006] In one embodiment, a method for forming a structure for a laterally diffused metal oxide semiconductor device is provided, the method comprising: forming a drift well in a semiconductor substrate; forming a source region and a drain region in the semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; and forming a buffer dielectric layer on the semiconductor substrate above the drift well. The buffer dielectric layer comprises a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first segment extending from the second side edge to the first side edge, and a plurality of second segments extending from the second side edge toward the first side edge. The first segment has a first thickness, and each of the second segments has a second thickness less than the first thickness. The method further comprises forming a gate electrode laterally located between the source region and the drain region. The gate electrode comprises a first portion overlapping the buffer dielectric layer and a second portion overlapping the gate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain embodiments of the present invention. In the accompanying drawings, like reference numerals are used to indicate like features throughout the various views.

[0008] Figure 1 is a cross-sectional view of a structure at an initial manufacturing stage of a processing method according to an embodiment of the present invention.

[0009] Figure 2 is Figure 1 Top view of the structure at a later stage of fabrication.

[0010] Figure 3 It is roughly along Figure 2 A cross-sectional view taken along line 3-3 in FIG.

[0011] Figure 3A It is roughly along Figure 2 A cross-sectional view taken along line 3A-3A in FIG.

[0012] Figure 3B It is roughly along Figure 2 A cross-sectional view taken along line 3B-3B in FIG.

[0013] Figure 4 is Figure 2 Top view of the structure at a later stage of fabrication.

[0014] Figure 5 It is roughly along Figure 4 A cross-sectional view taken along line 5-5 in FIG.

[0015] Figure 5A It is roughly along Figure 4 A cross-sectional view taken along line 5A-5A in FIG.

[0016] Figure 5B It is roughly along Figure 4 A cross-sectional view taken along line 5B-5B in FIG.

[0017] Figure 6 、 6A 6B is in Figure 5 、 5A , a cross-sectional view of the structure at the manufacturing stage after 5B.

[0018] Figure 7 、 7A 7B is in Figure 6 、 6A , a cross-sectional view of the structure at the manufacturing stage after 6B.

[0019] Figure 8 is a top view of a structure according to an alternative embodiment of the present invention.

[0020] Figure 9 is Figure 8 Top view of the structure at a later stage of fabrication.

[0021] Figure 10 It is roughly along Figure 9 A cross-sectional view taken along line 10-10 in FIG.

[0022] Figure 10A It is roughly along Figure 9 A cross-sectional view taken along line 10A-10A in FIG.

[0023] Figure 10B It is roughly along Figure 9A cross-sectional view taken along line 10B-10B in FIG. DETAILED DESCRIPTION

[0024] refer to Figure 1 And according to an embodiment of the present invention, a structure 10 for a laterally diffused metal oxide semiconductor device includes a substrate 12 and a shallow trench isolation region 14 arranged in the substrate 12 to surround the active device area. The substrate 12 can be composed of a semiconductor material, such as single crystal silicon. In one embodiment, the substrate 12 can be lightly doped to have p-type conductivity. The substrate 12 may include an epitaxial layer of semiconductor material epitaxially grown with a given thickness close to the top surface. The shallow trench isolation region 14 can be formed by patterning shallow trenches in the substrate 12 using photolithography and etching processes, depositing a dielectric material to fill the shallow trenches, and planarizing the deposited dielectric material and / or recessing the deposited dielectric material. The dielectric material of the shallow trench isolation region 14 may include silicon dioxide deposited by chemical vapor deposition.

[0025] The buried isolation layer 16 is formed within a given depth range below the top surface of the substrate 12. The buried isolation layer 16 may be formed in the substrate 12 by blanket ion implantation, or, alternatively, may be formed by in-situ doping during epitaxial growth of a semiconductor material of an epitaxial layer included in the substrate 12. The buried isolation layer 16 is doped to have a conductivity type opposite to that of the substrate 12. In an embodiment where the substrate 12 is p-doped, the buried isolation layer 16 may include an n-type dopant, such as arsenic or phosphorus, and may be heavily doped with the n-type dopant.

[0026] Deep trench isolation regions 18 are formed in deep trenches that penetrate shallow trench isolation regions 14 and substrate 12 between shallow trench isolation regions 14 and buried isolation layer 16 to a shallower depth within substrate 12 below buried isolation layer 16. Similar to shallow trench isolation regions 14, deep trench isolation regions 18 may surround active device regions. Deep trench isolation regions 18 may cooperate with buried isolation layer 16 to electrically isolate the active device regions from the rest of substrate 12. Deep trench isolation regions 18 may include a dielectric ring (e.g., silicon dioxide) lining the sidewalls of the deep trench and a conductive core (e.g., doped polysilicon or metal). The conductive core is coupled to substrate 12 below buried isolation layer 16 and isolated from substrate 12 above buried isolation layer 16 by the dielectric ring.

[0027] The well 20 is formed within a given depth range above the buried isolation layer 16. The well 20 can be formed, for example, by introducing dopants into the substrate 12 using blanket ion implantation at given implantation conditions. The implantation conditions (e.g., ion species, dose, kinetic energy) can be selected to adjust the electrical and physical properties of the well 20. The well 20 can be composed of the semiconductor material of the substrate 12, which is doped to have a conductivity type opposite to that of the substrate 12 and the same conductivity type as the buried isolation layer 16, but with a lower dopant concentration. In an embodiment where the substrate 12 is p-type doped, the well 20 can include a semiconductor material doped with an n-type dopant (e.g., phosphorus and / or arsenic) to provide n-type conductivity. The well 20 can provide a high-voltage well in the completed device structure 10.

[0028] Drift well 21 is formed in a portion of the active device region above buried isolation layer 16 and well 20. Drift well 21 can be formed, for example, by introducing dopants into substrate 12 using ion implantation under given implantation conditions. A patterned implantation mask can be formed to define selected areas (e.g., location and horizontal dimensions) on the top surface of substrate 12, which are exposed for implantation to form drift well 21. The implantation mask can include a layer of material, such as an organic photoresist, having a thickness and stopping power sufficient to block implantation in the masked areas. Implantation conditions (e.g., ion species, dose, kinetic energy) can be selected to adjust the electrical and physical properties of drift well 21. Drift well 21 can be composed of the semiconductor material of substrate 12, doped to have a conductivity type opposite to that of well 20. In embodiments where well 20 has n-type conductivity, drift well 21 can include semiconductor material lightly doped with a p-type dopant (e.g., boron) to provide p-type conductivity. Drift well 21 provides a drift region for an extended drain in the completed structure 10.

[0029] refer to Figure 2 、 3 , 3A, 3B, wherein the same reference numerals refer to Figure 1 The same features in the substrate 12 are formed and in a subsequent manufacturing stage, a hard mask 22 is formed over the substrate 12. The hard mask 22 may include a liner layer composed of a dielectric material such as silicon nitride and may be patterned by photolithography and etching processes to provide a patterned shape. In this regard, an etch mask formed by photolithography may be used to pattern the hard mask 22. The etch mask may include a layer of photosensitive material, such as a photoresist, which is applied by a spin coating process and then pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define an opening area having the shape to be formed in the hard mask 22. An etching process, such as a reactive ion etching process, may then be used to remove the portion of the liner layer exposed by the opening in the etch mask, followed by stripping the etch mask to define an opening 28 in the hard mask 22.

[0030] Each opening 28 in the hard mask 22 has a series of notches 24 arranged along a side edge. The notches 24 alternate with portions of the hard mask 22 that define protrusions 26 along the side edge of each opening 28. Each protrusion 26 is positioned between an adjacent pair of notches 24 in the form of a finger, thereby defining a comb shape. The other side edges of each opening 28 in the hard mask 22 are not notched and are therefore smooth. The notches 24 and protrusions 26 have dimensions selected by design rules used as input to the photolithography process. Specifically, the notches 24 have a width W1, the protrusions 26 have a width W2 that establishes a spacing between adjacent notches 24, and the notches 24 have a depth or length L1. The values ​​of width W1, width W2, and length L1 can be used to determine the thickness variation of the subsequently formed oxide layer.

[0031] In one embodiment, the distribution of the recesses 24 and protrusions 26 can be uniform along the side edges of each opening 28. In a representative embodiment, the recesses 24 and protrusions 26 can be rectangular. In an alternative embodiment, the recesses 24 and protrusions 26 can be trapezoidal. In an alternative embodiment, the recesses 24 can have a pointed shape and the protrusions 26 can be trapezoidal.

[0032] The doped region 34 can be formed as a top layer in the drift well 21, for example, by ion implantation, wherein the hard mask 22 serves as an implantation mask. As a result, the doped region 34 is formed within the openings 28 in the hard mask 22, which define the implanted regions of the substrate 12. The hard mask 22 blocks implantation of regions of the substrate 12 surrounding the openings 28. The implantation conditions (e.g., ion species, dose, kinetic energy) can be selected to adjust the electrical and physical properties of the doped region 34. The doped region 34 is doped to have a conductivity type opposite to that of the drift well 21. In embodiments where the drift well 21 includes a p-type dopant, the semiconductor material of the doped region 34 can include an n-type dopant (e.g., arsenic and / or phosphorus) that provides n-type conductivity.

[0033] The implanted area of ​​each doped region 34 matches the opening area of ​​the corresponding opening 28 and exhibits the same shape variation as that imparted by recess 24 and protrusion 26. In this regard, doped region 34 extending in substrate 12 below recess 24 of opening 28 has a length L2, and doped region 34 at the location of protrusion 26 has a length L3 that is less than length L2.

[0034] refer to Figure 4 、 5 , 5A, 5B, wherein the same reference numerals refer to Figure 2 、 3, 3A, 3B and in a subsequent manufacturing stage, a buffer dielectric layer 30 is formed using the openings 28 in the hard mask 22, and the hard mask 22 is removed after the buffer dielectric layer 30 is formed. In one embodiment, the buffer dielectric layer 30 can be composed of silicon dioxide. In one embodiment, the buffer dielectric layer 30 can be formed as a field oxide by performing thermal oxidation on the substrate 12 in an oxidizing atmosphere (e.g., an atmosphere with an oxygen content) using a local oxidation of silicon (LOCOS) process. Oxidizing species (e.g., oxygen) are prevented from diffusing through the thickness of the hard mask 22 during thermal oxidation, and the openings 28 in the hard mask 22 define exposed or unprotected areas that are thermally oxidized to grow the buffer dielectric layer 30. Each buffer dielectric layer 30 can grow under the protrusion 26 in the hard mask 22 and adjacent to the other edge of the corresponding opening 28 because the oxidizing species diffuse laterally in the substrate 12 under the hard mask 22. Specifically, the oxidizing species diffuses laterally from recess 24 below each protrusion 26 (starting from each side edge thereof) in substrate 12. The oxidizing species reacts with the semiconductor material of substrate 12 below protrusion 26.

[0035] Each buffer dielectric layer 30 includes a side edge 32, a side edge 33 opposite the side edge 32, a segment 60 having a thickness T1, a segment 62 having a thickness T2, and a segment 64 providing a thickness transition between the segments 60 and 62. The segments 60 of the buffer dielectric layer 30 can be formed within the openings 28 in the hard mask 22, including within the space defined by the recesses 24. The segments 62 of the buffer dielectric layer 30 can be formed under the protrusions 26 of the hard mask 22. The shape and size of each segment 60, 62 of the buffer dielectric layer 30 are at least partially determined by the shape and size of the recesses 24 and the protrusions 26.

[0036] The thickness T2 of the segment 62 is less than the thickness T1 of the segment 60. In one embodiment, the thickness T1 of each segment 60 of the buffer dielectric layer 30 can be uniform. In one embodiment, the thickness T2 of each segment 62 of the buffer dielectric layer 30 can be uniform. In one embodiment, the thickness T1 of each segment 60 of the buffer dielectric layer 30 can be substantially uniform. In one embodiment, the thickness T2 of each segment 62 of the buffer dielectric layer 30 can be substantially uniform.

[0037] Each segment 64 of the buffer dielectric layer 30 tapers in a range of thicknesses from a thickness T1 at the intersection with the segment 60 to a thickness T2 at the intersection with each segment 62. The segments 64 are formed adjacent to side edges of the protrusions 26 of the hard mask 22. Each segment 64 extends around multiple sides of each segment 62.

[0038] Each buffer dielectric layer 30 segment 60 , 62 also includes a peripheral segment 66 , represented as a bird's beak, where the dielectric material tapers to zero thickness. The side edges 32 , 33 of each buffer dielectric layer 30 are defined at the corners between the segment 60 and the peripheral segment 66 .

[0039] The doped regions 34 are self-aligned with each segment 60 of the buffer dielectric layer 30 because they are formed using the same patterned hard mask 22. That is, the doped regions 34 are located only below the segments 60 of the buffer dielectric layer 30, thereby defining the comb shape. In one embodiment, the doped regions 34 can be coextensive with (i.e., share a boundary with) the segments 60 of the buffer dielectric layer 30. The doped regions 34 are not located below the segments 62 of the buffer dielectric layer 30. Instead, some portions of the drift well 21 are located below the segments 62 of the buffer dielectric layer 30. In one embodiment, these portions of the drift well 21 can be coextensive with the segments 62 of the buffer dielectric layer 30.

[0040] refer to Figure 6 、 6A , 6B, wherein the same reference numerals refer to Figure 5 、 5A 5B and, in a subsequent manufacturing stage, wells 36, 38, and 40 are formed in the active region of substrate 12. Wells 38 and 40 are formed from the semiconductor material of substrate 12, which is doped to have a given conductivity type. Well 36 is formed from the semiconductor material of substrate 12, which is doped to have a conductivity type opposite to that of wells 38 and 40. Well 36 can be formed, for example, by introducing dopants into substrate 12 using ion implantation under given implantation conditions. Wells 38 and 40 can be formed, for example, by introducing different dopants of opposite conductivity types into substrate 12 using ion implantation. A patterned implantation mask can be formed to define one or more selected areas on the top surface of substrate 12 that are exposed for individual implantations. The implantation mask covers different areas on the top surface of substrate 12 to at least partially determine the position and horizontal dimensions of wells 36, 38, and 40. Each implantation mask can include a layer of material, such as an organic photoresist, applied and patterned so that different areas on the top surface of substrate 12 are covered and masked. Each implantation mask has a thickness and stopping power sufficient to stop implantation in the masked areas.

[0041] Implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to adjust the electrical and physical properties of well 36. A separate set of implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to adjust the electrical and physical properties of well 38. A separate set of implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to adjust the electrical and physical properties of well 40. Well 40 may include well 38 and may have a lower dopant concentration than well 38. In embodiments where well 20 has n-type conductivity and drift well 21 has p-type conductivity, well 36 may include a semiconductor material doped with a p-type dopant (e.g., boron) to provide p-type conductivity, and wells 38, 40 may include semiconductor materials doped with n-type dopants (e.g., phosphorus and / or arsenic) at different dopant concentrations to provide n-type conductivity.

[0042] refer to Figure 7 、 7A , 7B, wherein the same reference numerals refer to Figure 6 、 6A 6B and, in a subsequent manufacturing stage, gate electrodes 42 and gate dielectric layers 44 defining a pair of gates are formed to have a split-gate arrangement. Each gate dielectric layer 44 is composed of a dielectric material, such as silicon dioxide formed by thermal oxidation of the semiconductor material of substrate 12. Gate dielectric layers 44 have a thickness T3 that is less than the thickness of segments 60 of buffer dielectric layer 30 and less than the thickness of segments 62 of buffer dielectric layer 30. Each gate electrode 42 is composed of a conductor, such as doped polysilicon. Gate electrodes 42 and gate dielectric layers 44 can be formed by patterning their respective material layers using photolithography and etching processes.

[0043] Source regions 50, drain regions 52, and body contact regions 54 for the LDMOS device are formed in wells 36 and 38. Source and drain regions 50, 52 may be doped to have a conductivity type opposite to that of body contact region 54. Source region 50 disposed in well 38 may be doped to have a conductivity type opposite to that of well 38 and may be heavily doped. Drain region 52 disposed in well 36 may be doped to have the same conductivity type as well 36 but with a higher dopant concentration (e.g., heavily doped). Body contact region 54 disposed in well 38 and which may be in abutting relationship with source region 50 may be doped to have the same conductivity type as well 38. In embodiments where well 36 has p-type conductivity and well 38 has n-type conductivity, source region 50 and drain region 52 may be doped (e.g., heavily doped) with a p-type dopant (e.g., boron) to provide p-type conductivity, and body contact region 54 may be doped (e.g., heavily doped) with an n-type dopant (e.g., phosphorus and / or arsenic) to provide n-type conductivity.

[0044] Source and drain regions 50, 52 may be formed by selectively implanting ions (e.g., ions including a p-type dopant), wherein an implantation mask defines the desired locations for source and drain regions 50, 52 in substrate 12. Body contact region 54 may be formed by selectively implanting ions (e.g., ions including an n-type dopant), wherein a different implantation mask defines the desired locations for body contact region 54 in substrate 12.

[0045] Each gate dielectric layer 44 is positioned adjacent to a side edge 32 of one of the buffer dielectric layers 30 and, in one embodiment, abuts the side edge 32 of an adjacent buffer dielectric layer 30. Each gate electrode 42 includes a portion overlapping the gate dielectric layer 44 and another portion overlapping the buffer dielectric layer 30. The portion of each gate electrode 42 overlapping the buffer dielectric layer 30 defines a field plate. In one embodiment, each gate electrode 42 completely overlaps a segment 62 of the buffer dielectric layer 30. Each segment 60 of the buffer dielectric layer 30 extends from a side edge 32 adjacent to the gate dielectric layer 44 to a side edge 33. Each segment 62 of the buffer dielectric layer 30 extends from the side edge 32 toward the side edge 33 and, therefore, only partially extends across the buffer dielectric layer 30. The side edge 33 of each buffer dielectric layer 30 is adjacent to the drain region 52.

[0046] Each set of buffer dielectric layer 30, gate electrode 42, and gate dielectric layer 44 is laterally positioned on substrate 12 between drain region 52 and one of source regions 50. Segments 62 of each buffer dielectric layer 30 (which have a reduced thickness relative to segments 60) are positioned adjacent to one of source regions 50 and distal from drain region 52. Segments 62 of each buffer dielectric layer 30 are separated from drain region 52 by segments 60.

[0047] Middle of the line (MOL) processing and back of the line (BEOL) processing are then performed, which includes forming interconnect structures coupled to structure 10. Specifically, one or more contacts are formed to couple to each gate electrode 42, one or more contacts are formed to couple to each source region 50, one or more contacts are formed to couple to drain region 52, and one or more contacts are formed to couple to each body contact region 54.

[0048] Structure 10 can exhibit improved performance and versatility. Doped regions 34 that are not present beneath segments 62 of buffer dielectric layer 30 are slightly offset away from the corners of segments 62 of buffer dielectric layer 30 toward drain region 52. The offset of these corners away from source region 50 helps reduce current congestion at the corners. By adjusting the patterning of hard mask 22 to tailor the formation of buffer dielectric layer 30, laterally diffused metal oxide semiconductor devices with different characteristic on-resistances and nominally the same device footprint can be formed.

[0049] refer to Figure 8 , where the same reference numerals refer to Figure 2 The same features as in FIG. 1 and according to an alternative embodiment of the present invention, the patterning of the hard mask 22 may be modified to provide a plurality of openings 56 that are replaced by strips 58 of material of the hard mask 22 instead of recesses 24 ( Figure 2 In alternative embodiments, strips 58 may be widened (ie, expanded in a trapezoidal shape) and openings 56 concomitantly narrowed (ie, tapered) adjacent subsequently formed source regions 50 .

[0050] refer to Figure 9 、 10 , 10A, 10B and Figure 8 At a later stage of fabrication, doped regions 34 are formed in substrate 12 at the locations of openings 56. Strips 58 block implantation so that no doped regions 34 exist in substrate 12 below strips 58. A hard mask 22 ( Figure 9 ) A buffer dielectric layer 30 is formed by thermal oxidation, and the hard mask 22 is removed after the buffer dielectric layer 30 is formed.

[0051] Each buffer dielectric layer 30 includes a segment 70 having a thickness T3, a segment 72 having a thickness T4, and a segment 74 providing a transition between segments 70 and 72. Segments 70 of the buffer dielectric layer 30 can be formed within openings 56. Segments 72 of the buffer dielectric layer 30 can be formed below strips 58. The thickness T4 of segment 72 is less than the thickness T3 of segment 70. The shape and size of segments 70, 72 of each buffer dielectric layer 30 are at least partially determined by the shape and size of openings 56 and strips 58. In one embodiment, the thickness T3 of segment 70 of each buffer dielectric layer 30 can be uniform. In one embodiment, the thickness T4 of segment 72 of each buffer dielectric layer 30 can be uniform. In one embodiment, the thickness T3 of segment 70 of each buffer dielectric layer 30 can be substantially uniform. In one embodiment, the thickness T4 of segment 72 of each buffer dielectric layer 30 can be substantially uniform.

[0052] Segments 70 and 72 have a side-by-side arrangement and alternate across the width of each buffer dielectric layer 30. Each of the segments 72 is laterally disposed between a pair of adjacent segments 70. Segments 74 of each buffer dielectric layer 30 taper over an intermediate thickness range from a thickness T3 at the intersection with segment 70 to a thickness T4 at the intersection with segment 72. Segments 70, 72 of each buffer dielectric layer 30 also include a peripheral segment 76, represented as a bird's beak, where the dielectric material tapers to zero thickness.

[0053] Gate electrode 42 only partially overlaps segment 72 of buffer dielectric layer 30, which extends from side edge 32 to side edge 33 of buffer dielectric layer 30. Doped region 34 is located only below segment 70 of buffer dielectric layer 30. In one embodiment, doped region 34 can be coextensive with segment 70 of buffer dielectric layer 30. Doped region 34 is not located below segment 72 of buffer dielectric layer 30. Instead, portions of drift well 21 are located below segment 72 of buffer dielectric layer 30. In one embodiment, these portions of drift well 21 can be coextensive with segment 72 of buffer dielectric layer 30.

[0054] The process flow continues to complete the structure 10 as previously described.

[0055] The above method is used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. The chips can be integrated with other chips, discrete circuit components, and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smartphone with a central processing unit.

[0056] References herein to terms modified by approximate language such as "about," "approximately," and "substantially" are not limited to the precise value specified. Approximate language may correspond to the precision of an instrument used to measure the value and may indicate + / - 10% of the stated value unless the precision of the instrument is relied upon.

[0057] References herein to terms such as "vertical" and "horizontal" are made by way of example, not limitation, to establish a frame of reference. As used herein, the term "horizontal" is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. As just defined, the terms "vertical" and "normal" refer to directions perpendicular to the horizontal. The term "lateral" refers to a direction within the horizontal plane.

[0058] A feature that is “connected” or “coupled” to or “connected to” another feature may be directly connected or coupled to or “connected to” another feature, or one or more intervening features may be present. A feature may be “indirectly connected” or “indirectly coupled” to or “indirectly connected to” or “indirectly coupled to” another feature if no intervening features are present. A feature may be “indirectly connected” or “indirectly coupled” to or “indirectly connected to” or “indirectly coupled to” another feature if at least one intervening feature is present. A feature that is “located on” or “contacting” another feature may be directly located on or directly contacting another feature, or one or more intervening features may be present. A feature may be “directly located on” or “directly contacting” another feature if no intervening features are present. A feature may be “indirectly located on” or “indirectly contacting” another feature if at least one intervening feature is present. Different features may “overlap” if one feature extends over and covers a portion of another feature.

[0059] The description of various embodiments of the present invention has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the various embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a laterally diffused metal oxide semiconductor device, comprising: semiconductor substrates; a drift well located in the semiconductor substrate; a source region and a drain region located in the semiconductor substrate; a gate dielectric layer located on the semiconductor substrate; a buffer dielectric layer located on the semiconductor substrate above the drift well, the buffer dielectric layer comprising a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first segment extending from the second side edge to the first side edge, and a plurality of second segments extending from the second side edge toward the first side edge, the first segment having a first thickness, and each of the second segments having a second thickness less than the first thickness; as well as a gate electrode laterally positioned between the source region and the drain region, the gate electrode comprising a first portion overlapping the buffer dielectric layer and a second portion overlapping the gate dielectric layer, The plurality of second segments of the buffer dielectric layer alternate with portions of the first segment of the buffer dielectric layer along the second side edge.

2. The structure according to claim 1, wherein The gate electrode completely overlaps the second segment of the buffer dielectric layer.

3. The structure according to claim 1, wherein The gate electrode partially overlaps the second segment of the buffer dielectric layer.

4. The structure according to claim 1, wherein The second segment extends from the second side edge to the first side edge.

5. The structure according to claim 4, wherein The first segment of the buffer dielectric layer is included in a plurality of first segments of the buffer dielectric layer having the first thickness, and each of the second segments is laterally arranged between a pair of adjacent first segments.

6. The structure according to claim 1, wherein Each of the second segments is joined to the first segment of the buffer dielectric layer through a third segment, and the third segment has a third thickness tapering from the first thickness to the second thickness.

7. The structure according to claim 1, wherein The gate dielectric layer has a third thickness that is less than the first thickness and less than the second thickness.

8. The structure according to claim 1, wherein The first segment separates the second segment from the drain region.

9. The structure according to claim 1, further comprising: a doped region in the drift well, the doped region being located below the first segment of the buffer dielectric layer, The drift well is doped to have a first conductivity type, and the doped region is doped to have a second conductivity type different from the first conductivity type.

10. The structure according to claim 9, wherein The doped region is coextensive with the first segment of the buffer dielectric layer.

11. The structure according to claim 9, wherein The drift well is coextensive with the second segment of the buffer dielectric layer.

12. The structure according to claim 9, wherein The doped region does not exist below the second segment of the buffer dielectric layer.

13. The structure according to claim 1, wherein The second side edge of the buffer dielectric layer is adjacent to the gate dielectric layer.

14. The structure according to claim 13, wherein The gate dielectric layer is located between the second side edge of the buffer dielectric layer and the source region.

15. A method of forming a structure for a laterally diffused metal oxide semiconductor device, the method comprising: forming a drift well in a semiconductor substrate; forming a source region and a drain region in the semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a buffer dielectric layer on the semiconductor substrate above the drift well, wherein the buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first segment extending from the second side edge to the first side edge, and a plurality of second segments extending from the second side edge toward the first side edge, the first segment having a first thickness, and each of the second segments having a second thickness less than the first thickness; and forming a gate electrode laterally located between the source region and the drain region, wherein the gate electrode includes a first portion overlapping the buffer dielectric layer and a second portion overlapping the gate dielectric layer, The plurality of second segments of the buffer dielectric layer alternate with portions of the first segment of the buffer dielectric layer along the second side edge.

16. The method according to claim 15, wherein Forming a buffer dielectric layer on the semiconductor substrate above the drift well includes: forming a hard mask on the semiconductor substrate, the hard mask having openings shaped to provide the first segment and the second segment, The buffer dielectric layer is formed by a thermal oxidation process using the hard mask on the semiconductor substrate.

17. The method according to claim 16, wherein The hard mask includes a plurality of recesses alternating with a plurality of protrusions along a side edge, and the recesses and the protrusions have dimensions selected to provide the second thickness of the second segment.

18. The method according to claim 16, further comprising: forming a doped region in the drift well below the first segment of the buffer dielectric layer, The drift well is doped to have a first conductivity type, the doped region is doped to have a second conductivity type different from the first conductivity type, the doped region extends together with the first segment of the buffer dielectric layer, and the drift well extends together with the second segment of the buffer dielectric layer.

19. The method according to claim 18, wherein The doped region does not exist below the second segment of the buffer dielectric layer.

20. The method according to claim 15, wherein The gate electrode completely overlaps the second segment of the buffer dielectric layer.

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