DDR5 power management system
By designing the power management chipset and electronic fuse, a redundant power supply mechanism for DDR5 memory is implemented, which solves the problem of memory unusability caused by PMIC failure and improves the reliability and availability of memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INSPUR BUSINESS MACHINE CO LTD
- Filing Date
- 2022-12-20
- Publication Date
- 2026-07-24
AI Technical Summary
After the power supply scheme for DDR5 memory was moved from the motherboard to the memory module, a PMIC failure could render the memory module unusable, affecting the normal operation of the system. Existing technology lacks an effective redundancy mechanism.
The design employs a power management chipset and electronic fuse to ensure that when one power management chip fails, power is supplied by other chips. The actual output level is determined by the circuit component group, achieving redundancy between the power management chips and ensuring normal power supply to the DDR5 memory.
It improves the reliability and availability of DDR5 memory, avoids memory unavailability caused by a single PMIC failure, and enhances system reliability and serviceability.
Smart Images
Figure CN115729337B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer hardware technology, and in particular to a DDR5 power management system. Background Technology
[0002] In server systems, DDR4 and earlier generations of memory were typically powered by the motherboard's power chip, which converted the 12V and 3.3V electricity to the power required by the memory. However, with DDR5 memory, the power supply changed significantly. DDR5 memory only requires a 12V and 3.3V supply from the motherboard, relying on its onboard PMIC (Power Management Integrated Circuit) to convert the voltage to the necessary level. Starting with DDR5, the memory power supply solution shifted from the motherboard to the memory itself. This necessitated modifications to the memory power supply design, leading major power supply manufacturers to propose PMIC solutions.
[0003] The on-memory PMIC is an integrated buck digital converter for DDR5 On-DIMM power supply. It provides VDD (device power supply), VDDQ (memory chip output buffer supply voltage), and VPP (Virtual Power Plant) voltages to the DRAM (Dynamic Random Access Memory) chips on DIMM (Dual-Inline-Memory-Modules) modules, and has configurable current capability. See the block diagram for reference. Figure 1 As shown, a single DDR5 memory module uses a PMIC for power supply. When the PMIC malfunctions, the power supply to the entire memory module will be affected, rendering the entire memory module unusable and causing the system to lose memory. Summary of the Invention
[0004] In view of this, the purpose of this invention is to provide a DDR5 power management system that can ensure power supply to the memory by using a power management chipset and an electronic fuse, even if one power management chip fails. The specific solution is as follows:
[0005] In a first aspect, this application discloses a DDR5 power management system, comprising:
[0006] A power management chipset that includes several power management chips;
[0007] Several electronic fuses are respectively disposed between each power management chip and the power supply, so that when the current output level of any power management chip is low, the corresponding electronic fuse is triggered to blow, thereby disconnecting the electrical connection between the power management chip and the power supply.
[0008] A circuit element group is used to determine the actual output level of the power management chip group based on the current output level of each of the power management chips, so as to supply power to the DDR5 memory chip through the power supply when the actual output level is high.
[0009] Optionally, the power management chipset includes a first power management chip and a second power management chip, so that the power supply can supply power to the DDR5 memory chip through the other power management chip when a fault occurs in the line where either power management chip is located.
[0010] Optionally, the plurality of electronic fuses includes a first electronic fuse and a second electronic fuse;
[0011] The first electronic fuse is disposed between the power supply and the first power management chip; the second electronic fuse is disposed between the power supply and the second power management chip.
[0012] Optionally, the circuit element group is a group of elements built based on NOR gates and inverters, and is disposed between the power management chipset and the DDR5 memory chip.
[0013] Optionally, both the NOR gate and the inverter are devices constructed based on a number of metal-oxide-semiconductor field-effect transistors.
[0014] Optionally, the DDR5 power management system further includes:
[0015] A bidirectional two-wire synchronous serial bus connecting each of the power management chips and the DDR5 memory chips is used to determine the corresponding fault information of the power management chip whose current output level is low through address scanning operations.
[0016] Secondly, this application discloses a DDR5 power management method, applied to the aforementioned DDR5 power management system, comprising:
[0017] When the current output level of any power management chip in the DDR5 power management system is low, the corresponding electronic fuse in the DDR5 power management system is triggered to disconnect the electrical connection between the power management chip and the power supply.
[0018] The actual output level of the power management chipset is determined based on the current output level of each power management chip in the DDR5 power management system.
[0019] When the actual output level is high, power is supplied to the DDR5 memory chip through the power supply.
[0020] Thirdly, this application discloses a DDR5 power supply, including a power supply and a DDR5 power management system as described above.
[0021] Fourthly, this application discloses a DDR5 memory, including a DDR5 memory chip and a DDR5 power supply as described above.
[0022] Fifthly, this application discloses a server including the DDR5 memory described above.
[0023] As can be seen, this application provides a DDR5 power management system comprising a power management chipset including a plurality of power management chips; a plurality of electronic fuses respectively disposed between each power management chip and the power supply, so that when the current output level of any power management chip is low, the corresponding electronic fuse is triggered to blow, thereby disconnecting the electrical connection between the power management chip and the power supply; and a circuit element group for determining the actual output level of the power management chipset based on the current output level of each power management chip, so that when the actual output level is high, power is supplied to the DDR5 memory chip through the power supply. Therefore, if any power management chip in the power management chipset has a low current output level, the electrical connection between the power management chip and the power supply can be disconnected by blowing the electronic fuse. This ensures that the DDR5 memory chip is powered normally by other power management chips. In this way, by setting the power management chipset and electronic fuse, it can be ensured that the normal power supply of the DDR5 memory chip will not be affected when a power management chip fails, which increases the reliability of the system and avoids the problem of the DDR5 memory chip being affected and unable to be used when the power supply of only one power management chip fails.
[0024] This application also provides a DDR5 power management method. When the current output level of any power management chip in the DDR5 power management system is low, the method triggers a fuse operation via the corresponding electronic fuse in the DDR5 power management system to disconnect the electrical connection between the power management chip and the power supply. Then, based on the current output level of each power management chip in the DDR5 power management system, the actual output level of the power management chipset is determined. Finally, when the actual output level is high, power is supplied to the DDR5 memory chip through the power supply. Therefore, when any power management chip outputs a low level, the corresponding electronic fuse of that power management chip can be blown to disconnect the power management chip from the power supply. The current output level is determined based on each power management chip in the DDR5 power management system, and power is supplied to the DDR5 normally when the actual output level is high. This allows for redundancy among the power management chips in the chipset, and ensures normal power supply to the DDR5 memory even if one chip fails. Compared to DDR5 memory with only one power management chip, this method offers higher reliability and effectively improves memory availability and serviceability. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0026] Figure 1 This is a schematic diagram of an existing DDR5 memory structure disclosed in this application;
[0027] Figure 2 This is a schematic diagram of a DDR5 power management system disclosed in this application;
[0028] Figure 3 This is a schematic diagram of a NOR gate structure disclosed in this application;
[0029] Figure 4 This is a schematic diagram of an inverter structure disclosed in this application;
[0030] Figure 5 This is a schematic diagram of a specific DDR5 power management system structure disclosed in this application;
[0031] Figure 6 This is a flowchart of a DDR5 power management method disclosed in this application.
[0032] The markings in the diagram are explained as follows: 1 is the power management chipset; 7 is the first power management chip; 8 is the second power management chip; 2 is the circuit element group; 9 is the NOR gate; 10 is the inverter; 3 is the power supply; 4 is the DDR5 memory chip; 5 is the first electronic fuse; 6 is the second electronic fuse; 11 is the bidirectional two-wire synchronous serial bus. Detailed Implementation
[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0034] In server systems, DDR4 and earlier generations of memory typically relied on the motherboard's power chip to convert 12V and 3.3V power to the necessary voltages for the memory. However, DDR5 memory saw a significant change in power supply. DDR5 memory only requires 12V and 3.3V from the motherboard, relying instead on its own PMIC (Power Management Integrated Circuit) to convert the voltages to the required levels. Starting with DDR5, the memory power supply solution shifted from the motherboard to the memory module itself. This necessitated modifications to the memory power supply design. Each DDR5 memory module uses a single PMIC; if the PMIC malfunctions, the power supply to the entire memory module will be affected, rendering the entire module unusable and causing system memory loss.
[0035] See Figure 2As shown in the figure, this application discloses a DDR5 power management system. The DDR5 power management system includes a power management chipset 1, used to convert the voltage provided by the power supply into the voltage required by the DDR5 memory chip. It includes a first power management chip 7 and a second power management chip 8, so that when the power supply 3 experiences a fault in the line where either power management chip is located, the other power management chip can supply power to the DDR5 memory chip 4. It can be understood that the first power management chip 7 and the second power management chip 8 are two identical power management chips connected in parallel between the power supply 3 and the DDR5 memory chip 4. The two power management chips are redundant and jointly supply power to the DDR5 memory chip to ensure its normal operation. This prevents the problem of the DDR5 memory malfunctioning due to a fault in only one power management chip, thus improving the RAS (Reliability, Availability, Serviceability) characteristics of the memory.
[0036] In this embodiment, several electronic fuses are provided between each power management chip and the power supply 3. Specifically, a first electronic fuse 5 is provided between the first power management chip 7 and the power supply 3, and a second electronic fuse 6 is provided between the second power management chip 8 and the power supply 3. This ensures that when the current output level of any power management chip is low, the corresponding electronic fuse will trigger a melting operation to disconnect the electrical connection between the power management chip and the power supply. For example, if the current output level of the first power management chip 7 is low, it indicates that the first power management chip 7 has malfunctioned. In this case, the first electronic fuse 5 will be triggered to melt, disconnecting the electrical connection between the first power management chip 7 and the power supply 3, thus ensuring that the DDR5 memory chip 4 is not damaged by the first power management chip 7.
[0037] In this embodiment, the DDR5 power management system further includes a circuit element group 2, which includes a NOR gate 9 and an inverter 10, and is disposed between the power management chipset 1 and the DDR5 memory chip 4. The circuit element group 2 is used to determine the actual output level of the power management chipset 1 based on the current output level of each power management chip, so that when the actual output level is high, power is supplied to the DDR5 memory chip 4 through the power supply 3. Specifically, the actual output level to the DDR5 memory chip 4 is determined based on the current output level of the first power management chip 7 and the second power management chip 8. If the current output levels of both the first power management chip 7 and the second power management chip 8 are high, then the power management chip output... A normal PGOOD (Powergood) signal is output to the DDR5 memory chip 4 via NOR gate 9 and inverter 10, simultaneously supplying power to the DRAM chips and other chips on the DDR5 memory. If the current output level of one of the two power management chips is low and the current output level of the other power management chip is high, then the actual output level is determined to be high, and a high level is output to the DDR5 memory chip 4. However, if the current output levels of both power management chips are low, it indicates that both power management chips are faulty, and power supply to the DDR5 memory chip 4 is stopped. It should be noted that the possibility of both chips failing simultaneously is extremely small, so this solution does not consider the case of both chips failing simultaneously. The NOR gate 9 and inverter 10 can be used to ensure that as long as the current output level of one of the two power management chips is high, a high level can be output to the PCAMP pin (Personal identification number) on the DDR5 memory chip 4 interface to tell the system that the memory power supply is still normal. In this way, it can be ensured that when one power management chip fails, the other power management chip can be used to ensure the normal power supply and operation of the memory.
[0038] In this embodiment, both the NOR gate 9 and the inverter 10 are devices constructed based on several metal-oxide-semiconductor field-effect transistors (MOS). See also Figure 3 As shown, the NOR gate 9 is composed of two P-channel enhancement-mode MOSFETs connected in series and two N-channel enhancement-mode MOSFETs connected in parallel. See [link to documentation]. Figure 4As shown, the inverter 10 is composed of an N-channel enhancement-mode MOSFET and a P-channel enhancement-mode MOSFET. Based on the above embodiment, it can be seen that by combining the NOR gate 9 and the inverter 10, an OR gate can be formed and implemented, so that as long as one of the two power management chips outputs a high level, the actual output level can be determined as high.
[0039] In this embodiment, the CPU in the server manages two power management chips and some chips on the memory via I2C, i.e., a bidirectional two-wire synchronous serial bus 11. Each power management chip is connected to the DDR5 memory chip 4. When the output level of a power management chip is low, the CPU can scan the address through the I2C bus 11 to find out that a power management chip has failed and determine the corresponding fault information of the power management chip whose output level is currently low. This allows the user to perform operations such as replacement and repair of the faulty power management chip based on the fault information.
[0040] See Figure 5 As shown, in the memory design of this application, the 12V and 3.3V power supplied by the power supply are transmitted through the DIMM connector of the DDR5 memory motherboard and then through two fuses to power the PMIC (Power Management Chip) of the two memory modules respectively. Each DDR5 memory PMIC then converts the power required by other chips on the DDR5 memory and supplies them with power through circuit elements composed of MOS. At the same time, the CPU manages the two PMICs and some chips on the memory through the I2C bus to determine the relevant information of the faulty chip.
[0041] As can be seen, this application provides a power management chip group 1 comprising a plurality of power management chips in a DDR5 power management system; a plurality of electronic fuses respectively disposed between each power management chip and the power supply 3, so that when the current output level of any power management chip is low, the corresponding electronic fuse is triggered to blow, thereby disconnecting the electrical connection between the power management chip and the power supply; and a circuit element group 2, used to determine the actual output level of the power management chip group according to the level state of the current output level of each power management chip, so that when the actual output level is high, power is supplied to the DDR5 memory chip 4 through the power supply 3. Therefore, if any power management chip in the power management chipset 1 has a low current output level, the electrical connection between the power management chip and the power supply 3 can be disconnected by blowing the electronic fuse, ensuring that the DDR5 memory chip 4 is powered normally by other power management chips. In this way, by setting the power management chipset 1 and the electronic fuse, it can be ensured that when a power management chip fails, it will not affect the normal power supply of the DDR5 memory chip 4, which increases the reliability of the system and avoids the problem that the DDR5 memory chip 4 will be affected and the DDR5 memory will become unusable when the power supply of only one power management chip fails.
[0042] See Figure 6 As shown in the figure, this application discloses a DDR5 power management method, applied to a DDR5 power management system, including:
[0043] Step S11: When the current output level of any power management chip in the DDR5 power management system is low, the corresponding electronic fuse in the DDR5 power management system is triggered to disconnect the electrical connection between the power management chip and the power supply.
[0044] In this embodiment, when the current output level of any power management chip in the power management chipset 1 of the DDR5 power management system is low, it indicates that the power management chip has failed. The corresponding electronic fuse connected to the power management chip in the DDR5 power management system is then triggered to blow, disconnecting the electrical connection between the power management chip and the power supply 3. Specifically, if the first power management chip 7 outputs a low level and the second power management chip 8 outputs a high level, it indicates that the first power management chip 7 has failed. The first electronic fuse 5 connected to the first power management chip 7 will then blow, and the second power management chip 8 will supply power to the DDR5 memory chip 4 normally. In this way, when a short circuit occurs at the rear end of one of the power management chips, the electronic fuse can promptly cut off power to protect the DDR5 memory chip from damage.
[0045] Step S12: Determine the actual output level of the power management chipset based on the current output level of each power management chip in the DDR5 power management system.
[0046] In this embodiment, the NOR gate 9 and inverter 10 in circuit element group 2 can be used to determine the actual output circuit of power management chip group 1 based on the current output level of each power management chip in the DDR5 power management system. Specifically, if the output level of either the first power management chip 7 or the second power management chip 8 is high, the actual output level is determined to be high. If both the first power management chip 7 and the second power management chip 8 output low levels, the actual output level is determined to be low. This achieves redundancy between the two power management chips, ensuring that as long as one of the two power management chips is functioning correctly, the DDR5 memory can be powered normally, thus improving the memory's RAS (Reliability, Availability, and Serviceability) characteristics.
[0047] Step S13: When the actual output level is high, power is supplied to the DDR5 memory chip through the power supply.
[0048] In this embodiment, after determining the actual output level using the circuit element group 2, when the actual output level is high, power is supplied to the DDR5 memory chip 4 through the power supply 3 and the power management chip to ensure the normal operation of the DDR5 memory.
[0049] As can be seen, in this embodiment, when the current output level of any power management chip in the DDR5 power management system is low, the corresponding electronic fuse in the DDR5 power management system is triggered to blow, thereby disconnecting the electrical connection between the power management chip and the power supply 3. Then, based on the current output level of each power management chip in the DDR5 power management system, the actual output level of the power management chip group 1 is determined. Then, when the actual output level is high, power is supplied to the DDR5 memory chip 4 through the power supply 3. Therefore, when any power management chip outputs a low level, the corresponding electronic fuse of that power management chip can be blown to disconnect the power management chip from the power supply 3. Based on the current output level determined by each power management chip in the DDR5 power management system, and when the actual output level is high, power is supplied to the DDR5 normally. In this way, the power management chips in the power management chip group 1 can be redundant, and when one chip fails, other chips can ensure the normal power supply to the DDR5 memory. Compared to DDR5 memory with only one power management chip, this method offers higher reliability and effectively improves memory availability and serviceability.
[0050] Furthermore, this application also discloses a DDR5 power supply, including a power supply and the aforementioned DDR5 power management system, used to power DDR5 memory using the DDR5 power supply. For the specific structure of this device, please refer to the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0051] Furthermore, this application also discloses a DDR5 memory, including a DDR5 memory chip and the aforementioned DDR5 power supply, as well as the aforementioned DDR5 power management system, for storing CPU-processed data in the DDR5 memory powered by the DDR5 power management system. For the specific structure of this device, please refer to the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0052] Furthermore, this application also discloses a server including the aforementioned DDR5 memory, used to manage computer resources using the DDR5 memory. For details regarding the specific structure of this device, please refer to the corresponding content disclosed in the foregoing embodiments; further details will not be repeated here.
[0053] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0054] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0055] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0056] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0057] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A DDR5 power management system, characterized in that, include: A power management chipset that includes several power management chips; Several electronic fuses are respectively disposed between each power management chip and the power supply, so that when the current output level of any power management chip is low, the corresponding electronic fuse is triggered to blow, thereby disconnecting the electrical connection between the power management chip and the power supply. A circuit element group is used to determine the actual output level of the power management chip group based on the current output level of each of the power management chips, so as to supply power to the DDR5 memory chip through the power supply when the actual output level is high. The circuit element group is a group of elements built based on NOR gates and inverters, and is disposed between the power management chipset and the DDR5 memory chip. The power management chipset includes a first power management chip and a second power management chip, so that when the power supply fails in the line where either power management chip is located, the power supply can supply power to the DDR5 memory chip through the other power management chip. The plurality of electronic fuses include a first electronic fuse and a second electronic fuse; The first electronic fuse is disposed between the power supply and the first power management chip; the second electronic fuse is disposed between the power supply and the second power management chip; The NOR gate and the inverter are both devices constructed based on a number of metal-oxide-semiconductor field-effect transistors.
2. The DDR5 power management system according to claim 1, characterized in that, Also includes: A bidirectional two-wire synchronous serial bus connecting each of the power management chips and the DDR5 memory chips is used to determine the corresponding fault information of the power management chip whose current output level is low through address scanning operations.
3. A DDR5 power management method, characterized in that, The power management system described in claim 1 or 2 includes: When the current output level of any power management chip in the DDR5 power management system is low, the corresponding electronic fuse in the DDR5 power management system is triggered to disconnect the electrical connection between the power management chip and the power supply. The actual output level of the power management chipset is determined by the circuit element group based on the current output level of each power management chip in the DDR5 power management system; wherein, the circuit element group is a group of elements built based on NOR gates and inverters, and is set between the power management chipset and the DDR5 memory chip; When the actual output level is high, power is supplied to the DDR5 memory chip through the power supply. The power management chipset includes a first power management chip and a second power management chip, so that when the power supply fails in the line where either power management chip is located, the power supply can supply power to the DDR5 memory chip through the other power management chip. The plurality of electronic fuses include a first electronic fuse and a second electronic fuse; The first electronic fuse is disposed between the power supply and the first power management chip; the second electronic fuse is disposed between the power supply and the second power management chip; The NOR gate and the inverter are both devices constructed based on a number of metal-oxide-semiconductor field-effect transistors.
4. A DDR5 power supply, characterized in that, Includes a power supply and a DDR5 power management system as described in claim 1 or 2.
5. A DDR5 memory, characterized in that, Includes DDR5 memory chips and the DDR5 power supply as described in claim 4.
6. A server, characterized in that, Includes the DDR5 memory as described in claim 5.