Methods for processing the object

Abstract

This invention provides a method for processing a workpiece that suppresses deviations in the minimum linewidth with high precision during pattern formation on the workpiece. The film thickness formed in the first step of the film formation process, which is performed repeatedly using the same method as the ALD method, varies depending on the temperature of the surface on which the film is formed. Based on this, in order to reduce the deviation of trenches on the wafer surface, the film formation process is performed after adjusting the temperature for each region of the wafer surface. This reduces the deviation of trenches on the wafer surface and allows for the precise formation of a silicon oxide film on the inner surface of the trenches at a per-atom-layer height. When the trench width of the formed trench is narrower than a reference width, in order to expand the trench width, the second etching process, performed repeatedly using the same method as the ALE method, isotropically and uniformly etches the film disposed on the inner surface of the trench.

Description

[0001] This application is a divisional application of the invention entitled "Method for processing a processed object" with application number 201810971368.0 and application date of August 24, 2018. Technical Field

[0002] Embodiments of the present invention relate to a method for processing a processed object. Background Technology

[0003] In the manufacturing process of electronic devices, etching is performed to form a mask on a layer to be processed and to transfer the pattern of the mask onto the layer to be processed. Plasma etching can be used for this etching. The resist mask used for plasma etching can be formed using photolithography. Therefore, the limiting size of the pattern formed on the layer to be processed depends on the resolution of the resist mask formed by photolithography. There is a limit to the resolution of the resist mask. The increasing demand for high integration of electronic devices requires the formation of patterns smaller than the limiting resolution of the resist mask. Therefore, as described in Patent Document 1, a technique is proposed to adjust the size and shape of the resist mask to reduce the width of the opening provided by the resist mask.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2004-80033 Summary of the Invention

[0007] The technical problem the invention aims to solve

[0008] Patterning can be achieved, for example, by forming very fine trenches on a processed layer such as a SiO2 layer. When forming patterns with dimensions smaller than the limiting resolution of a resist mask, it is necessary to control the minimum linewidth (CD: Critical Dimension) of the trenches in the pattern very finely. The finer the pattern, the greater the impact of non-uniformity in the minimum linewidth. Therefore, for example, in patterning on a processed body with a processed layer such as SiO2, in order to achieve high-precision refinement, it is desirable to implement a method to suppress non-uniformity in the minimum linewidth with high precision.

[0009] Technical solutions for solving technical problems

[0010] In one approach, a method for processing a workpiece is provided. In the workpiece, a plurality of trenches are disposed on its surface. The method includes the following basic steps: a first step of measuring the trench width of the plurality of trenches; a second step of adjusting the trench width when the deviation of the trench width measured in the first step in the surface is not within a predetermined reference range; and a third step of performing an etching process to expand the trench width when the deviation is within the reference range and the trench width measured in the first step is narrower than a predetermined reference width. In the method, the surface is divided into multiple regions, and the second step includes adjusting the trench width according to each of the multiple regions. The fourth step involves adjusting the surface temperature; and the fifth step involves a film-forming process to form a film on the inner surface of the trench. In the fourth step, the surface temperature is adjusted using pre-obtained corresponding data so that deviations can be reduced through film formation. The corresponding data represents the relationship between the surface temperature during the film-forming process and the film thickness deposited on the inner surface of the trench. The film-forming process repeatedly executes the first process, which includes: a sixth step involving supplying a first gas into the processing container of a plasma processing apparatus containing the object to be processed; and after executing the sixth step, purging the space within the processing container. The second process includes: a seventh step of sweeping; an eighth step of generating a plasma of a second gas within the processing container after performing the seventh step; and a ninth step of purging the space within the processing container after performing the eighth step. The etching process is repeated in the second process, isotropically etching the film by removing it layer by layer. The second process includes: a tenth step of generating a plasma of a third gas within the processing container, and isotropically forming a mixed layer containing ions contained in the plasma of the third gas on the inner surface of the trench; and an eleventh step of purging the space within the processing container after performing the tenth step. The twelfth step involves generating a plasma of a fourth gas within the processing container after performing the eleventh step, and removing the mixed layer using free radicals contained in the plasma of the fourth gas; and the thirteenth step involves purging the space within the processing container after performing the twelfth step, wherein the membrane contains silicon, the first gas contains an aminosilane gas, the second gas includes a gas containing oxygen atoms, the third gas contains nitrogen, the fourth gas contains fluorine, the plasma of the fourth gas generated in the twelfth step contains free radicals used to remove the mixed layer containing silicon nitrides, and no plasma of the first gas is generated in the sixth step.

[0011] In the above method, the film thickness formed in the first step of the film formation process, which is performed repeatedly using the same method as the ALD (Atomic Layer Deposition) method, varies depending on the temperature of the surface on which the film is formed. Based on this, in order to reduce the deviation of the trench width of the multiple trenches provided on the surface of the workpiece (to improve the in-plane uniformity of the trench width on the surface of the workpiece), the film formation process is performed in the fourth step after adjusting the temperature for each region of the surface of the workpiece. Therefore, the deviation of the trench width of the multiple trenches provided on the surface of the workpiece can be reduced, and a silicon oxide film can be finely formed on the inner surface of the trenches at each atomic layer height. When the trench width of the formed film is narrower than the reference width, in order to expand the trench width, the etching process of the second step is performed repeatedly using the same method as the ALE (Atomic Layer Deposition) method. Therefore, the surface of the film provided on the inner surface of the trenches can be etched isotropically and uniformly, adjusting the trench width to the desired reference width. Therefore, when there is a deviation in the groove width on the surface of the object being processed, the deviation can be significantly reduced, and the groove width can be precisely adjusted to the desired reference width.

[0012] In one implementation, the basic steps return to the first step after performing the second step and the third step. Thus, after performing the second step of adjusting the trench width by forming a film and the third step of expanding the structure width by etching, the process returns to the first step of determining the trench width, allowing for more precise adjustment of the trench width.

[0013] In one embodiment, the basic steps are performed repeatedly, with the reference range gradually narrowing each time the basic steps are repeated. In this way, by repeatedly performing the basic steps while gradually narrowing the reference range of the trench width deviation, the trench width can be adjusted while the thickness of the film formed in the second step is gradually increased. Therefore, even when the trench width includes relatively narrow trenches, the situation where the trench opening is closed due to the formation of the film can be avoided.

[0014] In one embodiment, the first gas comprises a monoaminosilane. Using a first gas containing a monoaminosilane in this way enables the formation of a silicon reaction precursor.

[0015] In one embodiment, the first gas, an aminosilane-based gas, comprises an aminosilane having 1 to 3 silicon atoms. The first gas, an aminosilane-based gas, comprises an aminosilane having 1 to 3 amino groups. Thus, an aminosilane having 1 to 3 silicon atoms can be used as the first gas, an aminosilane-based gas. Alternatively, an aminosilane having 1 to 3 amino groups can be used as the first gas, an aminosilane-based gas.

[0016] In one embodiment, the fourth gas can be: a mixture of NF3 gas and O2 gas; a mixture of NF3 gas, O2 gas, H2 gas and Ar gas; or a mixture of CH3F gas, O2 gas and Ar gas. In this way, a fourth gas containing fluorine can be achieved.

[0017] Invention Effects

[0018] As explained above, a method can be provided to suppress deviations in the minimum linewidth with high precision during pattern formation on the processed object. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating a part of a method for implementing an embodiment.

[0020] Figure 2 This is an example as Figure 1 A cross-sectional view of the object to which the method is applicable.

[0021] Figure 3 It means that it is able to Figure 1 A diagram illustrating an example of the processing system used in the implementation of the method shown.

[0022] Figure 4 It means Figure 3 The diagram shows an example of a plasma processing device that the processing system can have.

[0023] Figure 5 It will be Figure 1 The diagram illustrates a portion of the multiple regions of the main surface of the object being processed, as shown in the process diagram.

[0024] Figure 6 It means Figure 1 The flowchart illustrates an example of the steps included in the method shown, specifically the steps for adjusting the deviation of the groove width.

[0025] Figure 7 It is a schematic representation in Figure 6 The graph shows the relationship between the thickness of the film formed in the steps shown and the temperature of the substrate.

[0026] Figure 8 Including parts (a), (b), and (c), it represents... Figure 6 The diagram illustrates the principle of membrane formation in the steps shown.

[0027] Figure 9 It means in Figure 6 The diagram shows a cross-sectional view of the processed body after the film has been formed in the steps shown.

[0028] Figure 10 It means Figure 1 The flowchart shows an example of the steps that can be included in the method shown, namely the step of adjusting the groove width.

[0029] Figure 11 It means in Figure 10 The diagram shows a cross-sectional view of the treated body after surface modification in the steps shown.

[0030] Figure 12 It means in Figure 10 The diagram shows how pressure can affect the isotropic and anisotropic etching processes.

[0031] Figure 13 It means in Figure 10 The graph shows the relationship between the isotropy of etching and pressure in the process shown.

[0032] Figure 14 It means in Figure 10 The diagram shows the self-limiting nature of surface modification in the process shown.

[0033] Figure 15 Including parts (a), (b), and (c), it represents... Figure 10 The diagram illustrates the etching principle of the steps shown.

[0034] Figure 16 It means in Figure 10 The diagram shows a cross-sectional view of the processed object after etching in the steps shown.

[0035] Figure 17 It means in Figure 10 The graph shows the changes in the amount of film etching and the thickness of the mixed layer formed on the film during the execution of the process.

[0036] Figure 18 It means through Figure 1 The bar chart shows the effect of the method shown.

[0037] Figure 19 Including parts (a) and (b), it indicates through Figure 1 A bar chart illustrating an example of the effect of the method shown.

[0038] Figure 20 It is a schematic representation of repeated execution. Figure 1 The diagram shows the morphology of the groove width variation when the method is shown.

[0039] Explanation of reference numerals in the attached figures

[0040] 1…processing system, 10…plasma processing device, 111…transfer chamber, 112a…unit, 112b…unit, 112c…unit, 112d…unit, 114a…receiving container, 114b…receiving container, 114c…receiving container, 114d…receiving container, 120…gas supply unit, 121…gas inlet, 122…gas supply source, 123…gas supply piping, 124…mass flow controller, 126…on / off valve, 12e…exhaust port, 134…wafer inlet / outlet, 136…gate valve, 14…support unit, 140…high frequency antenna, 14 2A…Inner antenna element, 142B…Outer antenna element, 144…Clamping body, 150A…High-frequency power supply, 150B…High-frequency power supply, 160…Shielding component, 162A…Inner shielding wall, 162B…Outer shielding wall, 164A…Inner shielding plate, 164B…Outer shielding plate, 168A…Actuator, 168B…Actuator, 18a…First plate, 18b…Second plate, 192…Processing container, 194…Plate dielectric body, 22…DC power supply, 23…Switch, 24…Cooling medium flow path, 26a…Pipeline, 26b…Pipeline, 28…Gas supply Pipe, 46…Deposit shield, 48…Exhaust plate, 50…Exhaust device, 52…Exhaust pipe, 64…High frequency power supply, 68…Matcher, Cnt…Control unit, DR…Direction, DT…Corresponding data, EL…Processed layer, EL1…Surface, ER…Area, ESC…Electrostatic chuck, FR…Focusing ring, G1…First gas, HP…Heater power supply, HT…Temperature regulator, LA…Membrane, LE…Lower electrode, LL1…Loading locking chamber, LL2…Loading locking chamber, LM…Loading assembly, Ly1…Layer, Ly2…Layer, MK…Mask, MK1…Surface, M T…method, MX…mixing layer, OC…optical observation device, P1…plasma, PD…stage, Rb1…transport robot, Rb2…transport robot, Sp…processing space, TM1…timing, TM2…timing, TR1…trench, TR2…trench, V1…interval, V2…interval, W…wafer, WF1a…film thickness, WF1b…film thickness, WF2a…film thickness, WF2b…film thickness, WW1a…trench width, WW1b…trench width, WW2a…trench width, WW2b…trench width, WW3a…trench width, WW3b…trench width. Detailed Implementation

[0041] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. In the various drawings, the same or corresponding parts are labeled with the same reference numerals. Figure 1 This is a flowchart illustrating a portion of a method (hereinafter referred to as method MT) for implementing an embodiment. Figure 1 The method MT shown is one embodiment of a method for processing a workpiece (hereinafter referred to as a wafer). Figure 2 This is an example of... Figure 1 The cross-sectional view of the object to be processed (wafer W) for which the method MT is applicable is shown.

[0042] Figure 2 The wafer W shown includes a processed layer EL, a mask MK disposed on the processed layer EL (surface EL1 of the processed layer EL), and trenches disposed on the mask MK (trenches refer to trenches TR1, trenches TR2, etc.; in this embodiment, they may include depressions, recesses, holes, or other similar shapes. The same applies hereinafter.). Multiple trenches are provided on the surface of the wafer W. In this embodiment, the trenches are disposed on the mask MK, but the structure is not limited to trenches disposed on the mask MK.

[0043] The material of the processed layer EL contains silicon oxide, and in one embodiment, it may also contain SiO2, for example. The material of the mask MK, in one embodiment, may also contain TiN, for example. In the mask MK, trenches providing the pattern of openings (meaning the same as trenches formed on the surface of the wafer W) are formed by photolithography. In one embodiment, two types of trenches with different widths are formed on the wafer W, namely... Figure 2 The trenches TR1 and TR2 are shown in the diagram. The trench widths of trenches TR1 and TR2 are different from each other. Trench TR1 has a trench width WW1a, and trench TR2 has a trench width WW1b. Figure 2 In the trenches TR1 and TR2 shown, the trench width WW1a is smaller than the trench width WW1b. Trench TR1 is formed approximately across the entire surface of wafer W at the center, middle, and end portions of the surface of wafer W (the middle portion is located between the center and the end portion). Trench TR2 is also formed approximately across the entire surface of wafer W at the center, middle, and end portions of the surface of wafer W. Furthermore, the types of trenches provided on the surface of wafer W are not limited to trenches TR1 and TR2. Figure 2 The trenches TR1 and TR2 shown are located together in the same region (the region ER, as described later, more specifically, is any one of the center of the surface of wafer W, the middle part of the surface of wafer W, or the end of the surface of wafer W).

[0044] The method MT (method for processing the object to be processed) is performed by a processing system having a plasma processing device. Figure 3 It means that it can be used Figure 1 The diagram shows an example of a processing system implementing the MT method. Figure 3The processing system 1 shown includes: a control unit Cnt, stage 112a, stage 112b, stage 112c, stage 112d, storage container 114a, storage container 114b, storage container 114c, storage container 114d, loading assembly LM, loading locking chamber LL1, loading locking chamber LL2, transfer chamber 111, optical observation device OC, and plasma processing device 10.

[0045] The control unit Cnt is a computer comprising a processor, storage unit, input device, and display device, which controls the various parts of the processing system 1 described later. The control unit Cnt is connected to the transport robotic arm Rb1, transport robotic arm Rb2, optical observation device OC, plasma processing device 10, etc., and is described later in... Figure 4 The plasma processing device 10 shown is connected to a mass flow controller 124, an on / off valve 126, a high-frequency power supply 150A, a high-frequency power supply 150B, a DC power supply 22, a switch 23, an exhaust device 50, a high-frequency power supply 64, a matching device 68, an electrostatic chuck ESC, a heater power supply HP, a cooling mechanism, etc.

[0046] The control unit Cnt operates according to the computer program (based on the input scheme) for controlling each part of the processing system 1 in each step of method MT, and issues control signals. Based on the control signals from the control unit Cnt, it controls each part of the processing system 1, such as the transport robotic arm Rb1, transport robotic arm Rb2, optical observation device OC, and plasma processing device 10. Figure 4 In the plasma processing apparatus 10 shown, the control unit Cnt can control the selection and flow rate of the gas supplied from the gas supply source 122, the exhaust from the exhaust device 50, the power supply from the high-frequency power supply 150A and 150B, the power supply from the high-frequency power supply 64, the power supply from the heater power supply HP, and the flow rate and temperature of the cooling medium from the cooling mechanism, based on control signals from the control unit Cnt. Furthermore, each step of the method MT disclosed in this specification can be executed by operating each part of the processing system 1 through the control of the control unit Cnt. The storage unit of the control unit Cnt stores in a readable manner a computer program for executing the method MT and various data (e.g., corresponding data DT described later) for executing the method MT.

[0047] Stages 112a to 112d are arranged along one edge of the loading assembly LM. Each stage 112a to 112d is provided with a storage container 114a to 114d. The storage container 114a to 114d can hold the wafer W.

[0048] A transport robotic arm Rb1 is provided in the loading assembly LM. The transport robotic arm Rb1 removes the wafer W stored in any of the storage containers 114a to 114d and transports the wafer W to the loading locking chamber LL1 or the loading locking chamber LL1.

[0049] Loading locking chambers LL1 and LL2 are disposed along the other edge of the loading assembly LM and connected to the loading assembly LM. Loading locking chambers LL1 and LL2 constitute a pre-decompression chamber. Loading locking chambers LL1 and LL2 are respectively connected to the transfer chamber 111.

[0050] The transfer chamber 111 is a pressure-reducing chamber, and a transport robotic arm Rb2 is installed inside the transfer chamber 111. A plasma processing device 10 is connected to the transfer chamber 111. The transport robotic arm Rb2 removes the wafer W from the loading locking chamber LL1 or the loading locking chamber LL2 and transports the wafer W to the plasma processing device 10.

[0051] The processing system 1 includes an optical observation device OC. The wafer W can be moved between the optical observation device OC and the plasma processing device 10 via transport robotic arms Rb1 and Rb2. The wafer W is housed in the optical observation device OC via transport robotic arm Rb1. After alignment of the wafer W in the optical observation device OC, the optical observation device OC measures the mask of the wafer W (e.g., ...). Figure 2 The trenches (e.g., those of the mask MK shown) Figure 2 The trench widths (such as trench TR1, trench TR2, etc.) shown in the figure are measured and the results are sent to the control unit Cnt. In the optical observation device OC, it is possible to measure the trench widths of multiple regions ER (refer to...) on the surface of the wafer W. Figure 5 Each measured groove width (explained below).

[0052] Figure 4 It means Figure 3 The processing system 1 shown is an example of a plasma processing device 10 that can be included. Figure 4 The cross-sectional structure of the plasma processing apparatus 10 that can be used in various embodiments of the method MT for processing wafer W is shown in the figure.

[0053] Figure 4The plasma processing apparatus 10 shown includes an ICP (Inductively Coupled Plasma) type plasma source. The plasma processing apparatus 10 has a metal (in one embodiment, for example, aluminum) cylindrical processing container 192. The processing container 192 divides a processing space Sp for plasma processing. The shape of the processing container 192 is not limited to cylindrical; in one embodiment, it may be a box-shaped or other cylindrical shape. The plasma source of the plasma processing apparatus 10 is not limited to the ICP type; for example, it may be an ECR (Electron Cyclotron Resonance) type, a CCP (Capacitively Coupled Plasma) type, a microwave-based plasma source, etc.

[0054] A mounting stage PD for mounting the wafer W is provided at the bottom of the processing container 192. The mounting stage PD includes an electrostatic chuck ESC and a lower electrode LE. The lower electrode LE includes a first plate 18a and a second plate 18b. The processing container 192 divides the processing space Sp.

[0055] A support portion 14 is disposed on the bottom of the processing container 192 inside the processing container 192. In one embodiment, the support portion 14 has a generally cylindrical shape. In another embodiment, the support portion 14 is formed of an insulating material, for example. The insulating material forming the support portion 14, such as quartz, can contain oxygen. The support portion 14 extends vertically from the bottom of the processing container 192 (from the top side of the processing container 192 (specifically, for example, the side of the plate-shaped dielectric body 194) toward the surface of the wafer W placed on the electrostatic chuck ESC).

[0056] A stage PD is disposed in the processing container 192. The stage PD is supported by a support 14. The stage PD holds the wafer W on its upper surface. The wafer W is the object to be processed. The stage PD includes a lower electrode LE and an electrostatic chuck ESC.

[0057] The lower electrode LE includes a first plate 18a and a second plate 18b. In one embodiment, the first plate 18a and the second plate 18b are formed of a metal such as aluminum. In one embodiment, the first plate 18a and the second plate 18b have a generally disk-shaped configuration. The second plate 18b is disposed on the first plate 18a. The second plate 18b is electrically connected to the first plate 18a.

[0058] An electrostatic chuck (ESC) is mounted on the second plate 18b. The ESC has an electrode structure with a conductive film disposed between a pair of insulating layers or a pair of insulating sheets. A DC power supply 22 is electrically connected to the electrodes of the ESC via a switch 23. The ESC uses the electrostatic force generated by the DC voltage from the DC power supply 22 to attract the wafer W. Thus, the ESC is able to hold the wafer W.

[0059] The focusing ring FR is disposed on the periphery of the second plate 18b in a manner that surrounds the edge of the wafer W and the electrostatic chuck ESC. The focusing ring FR is provided to improve the uniformity of etching. The focusing ring FR is formed of a material appropriately selected according to the material of the film to be etched, and in one embodiment, it can be formed of quartz, for example.

[0060] Cooling medium flow path 24 is disposed inside the second plate 18b. Cooling medium flow path 24 constitutes a temperature regulating mechanism. Cooling medium is supplied to cooling medium flow path 24 via pipe 26a from a cooling mechanism disposed outside the processing container 192. Cooling medium supplied to cooling medium flow path 24 is returned to the cooling mechanism via pipe 26b. In this way, cooling medium is supplied to cooling medium flow path 24 in a circulating manner. By controlling the temperature of this cooling medium, the temperature of the wafer W supported by the electrostatic chuck ESC can be controlled. Gas supply pipe 28 supplies heat-conducting gas from the heat-conducting gas supply mechanism, in one embodiment for example, He gas, between the upper surface of the electrostatic chuck ESC and the back surface of the wafer W.

[0061] The plasma processing apparatus 10 includes a temperature control unit HT for adjusting the temperature of the wafer W. The temperature control unit HT is integrated within the electrostatic chuck ESC. A heater power supply HP is connected to the temperature control unit HT. Power is supplied from the heater power supply HP to the temperature control unit HT, thereby adjusting the temperature of the electrostatic chuck ESC, and consequently, adjusting the temperature of the wafer W mounted on the electrostatic chuck ESC. Alternatively, the temperature control unit HT can also be embedded in the second plate 18b.

[0062] The temperature regulation unit HT includes: multiple heating elements for generating heat; and multiple temperature sensors for detecting the temperature around each of the multiple heating elements. When a wafer W is aligned and placed on an electrostatic chuck ESC, the multiple heating elements are respectively arranged for each of the multiple regions ER (described later) of the main surface FW of the wafer W. When the wafer W is aligned and placed on the electrostatic chuck ESC, the control unit Cnt identifies the heating elements and temperature sensors corresponding to each of the multiple regions ER on the surface of the wafer W in association with the region ER. In one embodiment, the control unit Cnt can identify the region ER and the heating element and temperature sensor corresponding to the region ER, for example, by using numbers or letters, according to each of the multiple regions (each of the multiple regions ER). The control unit Cnt detects the temperature of a region ER by the temperature sensor located at the location corresponding to that region ER, and adjusts the temperature of that region ER by the heating element located at the location corresponding to that region ER. Furthermore, when the wafer W is placed on the electrostatic chuck ESC, the temperature detected by a temperature sensor is the same as the temperature of the region ER on the temperature sensor in the wafer W.

[0063] A plate-shaped dielectric body 194 is disposed above and opposite the mounting stage PD. A lower electrode LE is disposed substantially parallel to the plate-shaped dielectric body 194. A processing space Sp is provided between the plate-shaped dielectric body 194 and the lower electrode LE. The processing space Sp is a spatial region used for plasma processing of the wafer W.

[0064] In the plasma processing apparatus 10, a deposit shield 46 is provided along the inner wall of the processing container 192 in a removable manner. The deposit shield 46 is provided on the outer periphery of the support portion 14. The deposit shield 46 is a component that prevents etching byproducts (deposits) from adhering to the processing container 192, and is constructed by coating aluminum with ceramic such as Y2O3. In addition to Y2O3, in one embodiment, the deposit shield can also be made of an oxygen-containing material such as quartz.

[0065] An exhaust plate 48 is disposed on the bottom side of the processing container 192 and between the support portion 14 and the side wall of the processing container 192. In one embodiment, the exhaust plate 48 is constructed, for example, of ceramic such as aluminum coated with Y2O3. An exhaust port 12e is disposed below the exhaust plate 48 in the processing container 192. An exhaust device 50 is connected to the exhaust port 12e via an exhaust pipe 52. The exhaust device 50 includes a vacuum pump such as a turbomolecular pump, capable of depressurizing the airflow inside the processing container 192 to a desired vacuum level. The high-frequency power supply 64 is a power supply that generates high-frequency power for introducing ions into the wafer W, i.e., generates high-frequency bias power, producing frequencies in the range of 400 [kHz] to 40.68 [MHz], and in one example, generating a high-frequency bias power of 13 [MHz]. The high-frequency power supply 64 is connected to the lower electrode LE via a matching device 68. The matching device 68 is a circuit for matching the output impedance of the high-frequency power supply 64 with the input impedance of the load side (lower electrode LE side).

[0066] In one embodiment, a plate-shaped dielectric body 194, made of materials such as quartz glass or ceramic, is disposed on the top portion of the processing container 192 opposite to the mounting stage PD. Specifically, in one embodiment, the plate-shaped dielectric body 194 is formed, for example, in a circular plate shape, and is hermetically mounted on the top portion of the processing container 192 to close any openings formed therein. The processing space Sp is the space where plasma is generated by a plasma source. The processing space Sp is the space where the wafer W is mounted.

[0067] A gas supply unit 120 is provided in the processing container 192 for supplying the first gas G1, the second gas, the third gas, and the fourth gas (described later). The gas supply unit 120 supplies the first gas to the fourth gas to the processing space Sp. A gas inlet 121 is formed on the side wall of the processing container 192, and the gas inlet 121 is connected to a gas supply source 122 via a gas supply pipe 123. A flow controller (e.g., a mass flow controller 124 and an on / off valve 126) for controlling the flow rate of the first gas to the fourth gas is provided midway through the gas supply pipe 123. Using such a gas supply unit 120, the first gas to the fourth gas output from the gas supply source 122 is controlled to a preset flow rate by the mass flow controller 124 and supplied to the processing space Sp of the processing container 192 through the gas inlet 121.

[0068] In addition, Figure 4 For simplicity, the gas supply unit 120 is represented by a system of gas pipelines, and the gas supply unit 120 has a structure for supplying multiple gases. For example... Figure 4 The gas supply unit 120 shown, as an example, has a structure that supplies gas from the side wall of the processing container 192. The gas supply unit 120 is not limited to... Figure 4 The structure shown is as follows. For example, the gas supply unit 120 can also have a structure that supplies gas from the top portion of the processing container 192. When the gas supply unit 120 has such a structure, for example, a gas inlet is formed in the central portion of the plate-shaped dielectric body 194, and gas can be supplied from the gas inlet.

[0069] The bottom of the processing container 192 is connected via an exhaust pipe 52 to an exhaust device 50 for discharging the atmosphere inside the processing container 192. The exhaust device 50 is, for example, a vacuum pump, capable of setting the pressure inside the processing container 192 to a preset pressure.

[0070] A wafer inlet / outlet 134 is provided on the side wall of the processing container 192, and a gate valve 136 is provided at the wafer inlet / outlet 134. For example, when a wafer W is fed in, the gate valve 136 is opened, and the wafer W is placed on the loading stage PD inside the processing container 192 by a transport mechanism such as a transport arm (not shown). Then, the gate valve 136 is closed, and the processing of the wafer W begins.

[0071] In the top portion of the processing container 192, on the upper side (outer side) of the plate-shaped dielectric body 194, a planar high-frequency antenna 140 and a shielding member 160 covering the high-frequency antenna 140 are provided. In one embodiment, the high-frequency antenna 140 includes: an inner antenna element 142A disposed in the central portion of the plate-shaped dielectric body 194; and an outer antenna element 142B disposed to surround the outer periphery of the inner antenna element 142A. In one embodiment, for example, the inner antenna element 142A and the outer antenna element 142B are conductors of copper, aluminum, stainless steel, etc., and have a spiral coil shape.

[0072] The inner antenna element 142A and the outer antenna element 142B are held together by a plurality of clamping bodies 144. In one embodiment, for example, the clamping bodies 144 have a rod-like shape. The clamping bodies 144 are arranged radially, protruding from near the center of the inner antenna element 142A toward the outer side of the outer antenna element 142B.

[0073] The shielding member 160 has an inner shielding wall 162A and an outer shielding wall 162B. The inner shielding wall 162A is disposed between the inner antenna element 142A and the outer antenna element 142B in a manner that surrounds the inner antenna element 142A. The outer shielding wall 162B is disposed in a manner that surrounds the outer antenna element 142B and has a cylindrical shape. Therefore, the upper surface of the plate-shaped dielectric body 194 is divided into a central portion (central region) inside the inner shielding wall 162A and a peripheral portion (peripheral region) between the inner shielding wall 162A and the outer shielding wall 162B.

[0074] A circular inner shielding plate 164A is provided on the inner antenna element 142A in such a way as to close the opening of the inner shielding wall 162A. An annular outer shielding plate 164B is provided on the outer antenna element 142B in such a way as to close the opening between the inner shielding wall 162A and the outer shielding wall 162B.

[0075] The shape of the shielding member 160 is not limited to a cylindrical shape. In one embodiment, the shielding member 160 may be other shapes, such as a triangular shape, or it may be a shape that matches the shape of the processing container 192. Here, in one embodiment, for example, the processing container 192 has a generally cylindrical shape, so the shielding member 160 also has a generally cylindrical shape to match this cylindrical shape. When the processing container 192 has a generally triangular shape, the shielding member 160 also has a generally triangular shape.

[0076] The inner antenna element 142A and the outer antenna element 142B are each connected to the power supplies of the high-frequency power supply 150A and the high-frequency power supply 150B, respectively. This allows for the application of high frequencies of the same or different frequencies to the inner antenna element 142A and the outer antenna element 142B. For example, in one embodiment, when a high-frequency frequency of, for example, 27 MHz, is supplied to the inner antenna element 142A from the high-frequency power supply 150A, the gas introduced into the processing container 192 is excited by the induced magnetic field formed within the processing container 192, generating a ring-shaped plasma at the center of the wafer W. Furthermore, in another embodiment, when a high-frequency frequency of, for example, 27 MHz, is supplied to the outer antenna element 142B from the high-frequency power supply 150B, the gas introduced into the processing container 192 is excited by the induced magnetic field formed within the processing container 192, generating another ring-shaped plasma at the periphery of the wafer W. The high frequencies output from high-frequency power supplies 150A and 150B are not limited to the frequencies mentioned above; various high frequencies can be supplied from high-frequency power supplies 150A and 150B respectively. Furthermore, the electrical lengths of the inner antenna element 142A and outer antenna element 142B need to be adjusted corresponding to the high frequencies output from high-frequency power supplies 150A and 150B. The heights of each inner shielding plate 164A and outer shielding plate 164B can be adjusted using actuators 168A and 168B respectively.

[0077] The following is for reference Figure 1 , Figure 6 , Figure 10The method MT will be described in detail, taking as an example its implementation in a processing system 1 having a plasma processing apparatus 10. Furthermore, the method MT can also be implemented in other processing systems different from processing system 1, such processing systems having plasma processing apparatuses other than plasma processing apparatus 10.

[0078] First, return Figure 1 The following explanation is provided. Method MT has basic steps. These basic steps include step ST1 (step 1), step ST2, step ST3 (step 2), step ST4, and step ST5 (step 3). For example... Figure 1 As shown, the basic steps return to step ST1 after executing step ST3 and step ST5. Step ST1 measures the trench widths of multiple trenches (including trench TR1, trench TR2, and so on) of the wafer W. More specifically, in step ST1, the control unit Cnt uses the optical observation device OC of the processing system 1 to measure the trench width values ​​for each trench (TR1, TR2, etc.) and for each of the multiple regions ER on the surface of the wafer W. Regarding the surface of the wafer W, in method MT (the processing performed by the control unit Cnt), as... Figure 5 The area shown is divided into multiple regions ER. Figure 5 This diagram schematically illustrates a portion of a plurality of regions ER on the surface of a wafer W, as described in one embodiment of the method MT. The regions ER do not overlap. The regions ER cover the surface of the wafer W. In one embodiment, for example, the shape of the regions ER may be a region extending approximately concentrically with respect to the center of the surface of the wafer W, or a lattice-like region, etc., but is not limited thereto.

[0079] In step ST2 following step ST1, the control unit Cnt calculates: the difference between the trench width measured in step ST1 for each region ER and a reference value for the trench width preset for each region ER (this reference value is set separately for trench TR1 and trench TR2, and for simplicity, it is simply referred to as the reference value); and the deviation of the trench width measured in step ST1 on the surface of the wafer W (more specifically, in one embodiment, for example, the deviation of this difference on the surface of the wafer W), and determines whether the deviation is within a preset reference range (this reference range is set separately for trench TR1 and trench TR2, and for simplicity, it is simply referred to as the reference range). This deviation is the deviation of the measured values ​​of the trench widths of each trench TR1 and trench TR2 measured in step ST1 for each region ER; in one embodiment, for example, a standard deviation can be used. This deviation represents the uniformity of the trench widths of each of the trenches TR1 and TR2 within the plane of the wafer W. In one embodiment, more specifically, it is represented by the standard deviation of the values ​​of the trench widths of all trenches TR1 within the plane of the wafer W and the standard deviation of the values ​​of the trench widths of all trenches TR2 within the plane of the wafer W.

[0080] The reference ranges for the aforementioned deviations of trenches TR1 and TR2 can be either a single range for each of trenches TR1 and TR2, or multiple ranges for each of trenches TR1 and TR2. Multiple reference ranges can, for example, be used in repeated operations such as... Figure 1 This is used in the case of method MT shown. In this case, a different reference range can be used each time method MT is executed. The case of repeatedly executing method MT will be explained later.

[0081] In step ST2, if it is determined that the deviation of the trench width of the trench TR1 in the surface of the wafer W and the deviation of the trench width of the trench TR2 in the surface of the wafer W are not within their respective reference ranges (step ST2: No), proceed to step ST3. If it is determined that the deviation of the trench width of the trench TR1 in the surface of the wafer W and the deviation of the trench width of the trench TR2 in the surface of the wafer W are within their respective reference ranges (step ST2: Yes), proceed to step ST4.

[0082] In step ST3, following "Step ST2: No", a process is performed to adjust the deviation of the trench width on the surface of wafer W. In step ST3, when the deviation of the trench width on the surface of wafer W measured in step ST1 is not within a pre-set reference range (Step ST2: No), the deviation is adjusted by adjusting the trench width. In step ST3, the adjustment of the deviation of the trench width on the surface of wafer W is achieved by forming a film (described later) on the surface of wafer W (particularly within each trench) in a manner that reduces the deviation. Figure 9 This is achieved using the membrane LA shown in the diagram. For details regarding step ST3, please refer to the following description. Figure 6 Let me explain in detail. After the execution of step ST3, we return to step ST1 and repeat the processing after step ST1.

[0083] In step ST4, following "Step ST2: Yes", after the deviation of the trench width on the surface of wafer W is reduced, it is determined whether the trench width is narrower than the preset reference width for each of trench TR1 and trench TR2. When the trench width of at least one of trench TR1 and trench TR2 is narrower than the reference width (Step ST4: Yes), proceed to step ST5. When the trench width of either trench TR1 or trench TR2 is greater than the reference width (Step ST4: No), the processing of method MT ends.

[0084] In step ST5, following "Step ST4: Yes", when the deviation on the surface of wafer W measured in step ST1 is within the reference range, and the trench width measured in step ST1 is narrower than a pre-set reference width in at least one of trench TR1 and trench TR2, an etching process to expand the trench width is performed. More specifically, in step ST5, the film formed on the surface of wafer W in step ST3 is etched isotropically to uniformly expand the trench width. Through the etching in step ST5, the amount of etching (the thickness of the portion of the film formed on the surface of wafer W in step ST3 that is etched in step ST5) is uniform (approximately the same) throughout all trenches. Details of step ST5 will be provided later. Figure 10 This will be explained in detail. After step ST5 is executed, the process returns to step ST1 and repeats the process after step ST1.

[0085] Next, refer to Figure 6 Explain step ST3. Figure 6 It means Figure 1The flowchart illustrates an example of step ST3, which involves adjusting the deviation of the trench width, within the method MT shown. Step ST3 includes steps ST3a, ST3b, ST3c (step 4), process SQ1 (step 1), ST3h, and ST3i. In step ST3c, the surface temperature of the wafer W is adjusted for each of the multiple regions ER. Following step ST3c, in the film formation process (step 5) of process SQ1 and step ST3h, a film formation process is performed on the surface of the wafer W after temperature adjustment using ALD (Atomic Layer Deposition) to form a film LA on the inner surface of the trenches of the wafer W. Process SQ1 includes steps ST3d (step 6), ST3e (step 7), ST3f (step 8), and ST3g (step 9).

[0086] More specifically, following "Step ST2: No" Figure 1 In step ST3a, the wafer W is moved from the optical observation device OC to the plasma processing device 10 via transport robotic arms Rb1 and Rb2, and is then placed into the processing container 192 of the plasma processing device 10. In step ST3b following step ST3a, the wafer W placed in the processing container 192 of the plasma processing device 10 is aligned on an electrostatic chuck ESC and placed on the electrostatic chuck ESC.

[0087] In the film formation process of steps SQ1 and ST3h executed after step ST3c, the thickness of the formed film increases or decreases according to the temperature of the surface of the wafer W. Therefore, in step ST3c following step ST3b, the temperature of the surface of the wafer W is adjusted by the temperature adjustment unit HT for each of the multiple regions ER on the surface of the wafer W. Figure 7 It is a schematic representation in Figure 6 The graph shows the relationship between the film thickness formed in the steps shown and the surface temperature of the wafer W. Figure 7 The line GRa in the middle represents the line in the middle. Figure 6 The relationship between the film thickness formed in the steps shown and the surface temperature of the wafer W on which the film is formed corresponds to the Arrhenius plot. Figure 7 The horizontal axis represents the surface temperature of the wafer W in which the film is formed through step ST3. Figure 7 The vertical axis represents the film thickness formed through step ST3. Specifically, Figure 7 The vertical axis represents the film thickness, which is the film thickness formed over a time period exceeding the time required to reach the self-limited region in the ALD method used in step ST3. For example... Figure 7As shown, when the surface temperature of wafer W is T1, the film thickness formed on the surface of wafer W is W1; when the surface temperature of wafer W is T2 (T2>T1), the film thickness formed on the surface of wafer W is W2 (W2>W1). Thus, using the ALD method, a higher surface temperature results in a thicker film formed on that surface. Therefore, if the film formation processes SQ1 and ST3h are performed after adjusting the surface temperature of wafer W in step ST3c, the film formed by these processes can reduce the deviation of trench width on the surface of wafer W (improving in-plane uniformity) in both trenches TR1 and TR2. In other words, the adjustment of the surface temperature of wafer W in step ST3c is performed to reduce the deviation of trench width on the surface of wafer W in both trenches TR1 and TR2 using the film formed by the film formation processes SQ1 and ST3h performed after step ST3c.

[0088] In step ST3c, the control unit Cnt uses pre-acquired corresponding data DT to adjust the surface temperature of the wafer W for each of the multiple regions ER, so that the deviation of the trench width on the surface of the wafer W in each trench TR1 and trench TR2 is reduced due to the formation of the film. The corresponding data DT represents the relationship between the surface temperature of the wafer W in the film formation process of process SQ1 and step ST3h and the film thickness of the film deposited on the inner surface of the trench (the film formed by the film formation process of process SQ1 and step ST3h and included in film LA). The corresponding data DT is obtained by depositing the film on the surface MK1 of the mask MK and the inner surface of the trenches set on the mask MK according to each surface temperature of the wafer W, under the same conditions as the film formation process of process SQ1 and step ST3h (except for the surface temperature condition of the wafer W). Figure 9 The data obtained in advance for the film LA (as shown) is stored in the storage unit of the control unit Cnt in a freely readable manner. That is, in step ST3c, the control unit Cnt adjusts the surface temperature of the wafer W by each of the multiple regions ER using the temperature adjustment unit HT and the corresponding data DT, so that the temperature of each of the multiple regions ER on the surface of the wafer W, which is sent into the processing container 192, becomes the temperature corresponding to the thickness of the difference calculated by each of the multiple regions ER in step ST2. The film formation process of process SQ1 and step ST3h is performed on the surface of the wafer W (including surface MK1 and the inner surface of the trenches of the wafer W) that has been temperature-adjusted in step ST3c, thereby reducing the deviation of the trench width on the surface of the wafer W in each trench TR1 and trench TR2.

[0089] As explained above, the series of steps following step ST3c, SQ1 and ST3h, is a film formation step in which a film (film LA) is formed on the surface of the wafer W (the surface MK1 of the mask MK and the inner surface of the trenches of the wafer W) which is fed into the processing container 192. The film formation process in SQ1 and ST3h forms a silicon oxide film (film LA) on the surface of the wafer W using the same method as the ALD method, thereby reducing the deviation of the trench width in each of the multiple regions ER on the surface of the wafer W. During step ST3d of process SQ1, the surface temperature of the wafer W, adjusted according to each of the multiple regions ER, is maintained in step ST3c. Therefore, the film (film LA) formed by the film forming process can have different film thicknesses for each of the multiple regions ER (more specifically, for example, the center of the surface of wafer W, the middle part of the surface of wafer W, and each of the ends of the surface of wafer W), and the deviation of the trench width in the surface of wafer W can be reduced in each trench TR1 and trench TR2.

[0090] This describes the detailed process of membrane formation (process SQ1 and step ST3h). In step ST3d, a first gas G1 is supplied into the processing container 192. Specifically, in step ST3d, as... Figure 8 As shown in part (a), a first gas G1 containing silicon is introduced into the processing container 192.

[0091] The first gas G1 comprises an aminosilane gas containing an organic group. As an aminosilane gas, the first gas G1 can be a gas with a molecular structure having a relatively small number of amino groups. In one embodiment, for example, a monoaminosilane (H3-Si-R (where R is an organic group, a replaceable amino group)) can be used. Furthermore, the aforementioned aminosilane gas that can be used as the first gas G1 can comprise an aminosilane having 1 to 3 silicon atoms, or an aminosilane having 1 to 3 amino groups. The aminosilane having 1 to 3 silicon atoms can be silane (monoaminosilane), silane, or propane. Moreover, the aforementioned aminosilane can have replaceable amino groups. Furthermore, the aforementioned amino groups can be replaced by any of methyl, ethyl, propyl, and butyl groups. Furthermore, the aforementioned methyl, ethyl, propyl, and butyl groups can be replaced by halogens. A first gas G1, containing an aminosilane gas with an organic group, is supplied to the processing container 192 from a gas source selected from gas supply source 122. The processing time in step ST3d is the time longer than the time required for the ALD method to reach the self-limiting region.

[0092] The molecules of the first gas G1, such as Figure 8As shown in section (b), a reaction precursor (layer Ly1) is attached to the surface of wafer W (the surface MK1 of mask MK and the inner surface of the trenches of wafer W). In step ST3d, plasma of the first gas G1 is not generated. The molecules of the first gas G1 are attached to the surface of wafer W by chemical adsorption based on chemical bonds, and plasma cannot be used. Furthermore, as the first gas G1, in step ST3c, a silicon-containing gas that can be attached to the surface of wafer W by chemical bonds can be used at the temperature adjusted for each of the multiple regions ER.

[0093] On the other hand, when a monoaminosilane is chosen for the first gas G1, the reason for choosing a monoaminosilane is that it has relatively high electronegativity and a polar molecular structure, making it easier to undergo chemisorption. The reaction precursor layer Ly1 formed by the adhesion of the molecules of the first gas G1 to the surface of the wafer W becomes close to a monolayer (monolayer) because this adhesion is chemisorption. The smaller the amino group (R) of the monoaminosilane, the smaller the molecular structure of the molecules adsorbed on the surface of the wafer W, thus reducing the steric hindrance caused by molecular size. Therefore, the molecules of the first gas G1 can be uniformly adsorbed on the surface of the wafer W according to the temperature of each of the multiple regions ER, and the layer Ly1 can be formed as a uniform film on the surface of the wafer W according to the temperature of each of the multiple regions ER.

[0094] As described above, because the first gas G1 contains an aminosilane gas with organic groups, a silicon reaction precursor (layer Ly1) is formed along the atomic layers of the surface of the wafer W through step ST3d.

[0095] Following step ST3d, step ST3e involves purging the processing space Sp within the processing container 192. Specifically, the first gas G1 supplied in step ST3d is exhausted. In step ST3e, an inert gas, such as nitrogen or a rare gas (e.g., Ar in one embodiment), is supplied to the processing container 192 as the purging gas. That is, the purging in step ST3e can be either purging with a gas that allows the inert gas to circulate within the processing container 192 or purging based on vacuum. In step ST3e, excess molecules adhering to the surface of the wafer W can also be removed. Through the above steps, the reaction precursor layer Ly1 becomes an extremely thin molecular layer formed according to the temperature of the region ER on the surface of the wafer W.

[0096] Following step ST3e in step ST3f, such as Figure 8As shown in section (b), a plasma P1 of a second gas is generated in the processing space Sp of the processing container 192. The second gas contains oxygen-containing atoms, and in one embodiment, it may contain oxygen, for example. The second gas containing oxygen-containing atoms is supplied to the processing container 192 from a gas source selected from a plurality of gas sources selected from gas supply source 122. High-frequency power is supplied from high-frequency power sources 150A and 150B. The pressure of the processing space Sp within the processing container 192 is set to a predetermined pressure by activating the exhaust device 50. In this way, a plasma P1 of the second gas is generated in the processing space Sp.

[0097] like Figure 8 As shown in section (b), when the plasma P1 that generates the second gas is generated, active species of oxygen are generated, such as oxygen free radicals in one embodiment. Figure 8 As shown in section (c), the Ly2 layer formed by the silicon oxide film (in) Figure 9 The layers contained in the LA membrane are formed as extremely thin molecular layers.

[0098] As described above, because the second gas contains oxygen atoms, in step ST3f, these oxygen atoms combine with the silicon reaction precursor (layer Ly1) disposed on the surface of wafer W, thereby forming a silicon oxide film layer Ly2 (on the surface of wafer W). Figure 9 The layers contained in the film LA can be formed with different thicknesses depending on the temperature of each of the multiple regions ER. Therefore, in process SQ1, the layer Ly2 of the silicate film (in the same way as the ALD method) can be formed with different thicknesses in each of the multiple regions ER. Figure 9 The layers contained in the film LA are formed on the surface of the wafer W with film thickness corresponding to the temperature of each of the multiple regions ER.

[0099] In step ST3g, following step ST3f, the processing space Sp within the processing container 192 is purged. Specifically, the second gas supplied in step ST3f is exhausted. In step ST3g, an inert gas such as nitrogen or a rare gas (e.g., Ar in one embodiment) can be supplied to the processing container 192 as the purging gas. That is, the purging in step ST3g can be either purging with a gas that allows the inert gas to circulate in the processing container 192 or purging based on vacuum.

[0100] In step ST3h following process SQ1, it is determined whether the number of repetitions of process SQ1 has reached a preset number. If it is determined that the number has not yet been reached (step ST3h: No), process SQ1 is executed again. If it is determined that the number has been reached (step ST3h: Yes), the process moves to step ST3i. That is, in step ST3h, process SQ1 is repeatedly executed until the number of repetitions of process SQ1 reaches the preset number, and a film with a thickness corresponding to the respective temperature of each of the multiple regions ER is formed on the surface of wafer W. The number of repetitions of process SQ1 controlled by step ST3h is set such that the trench with the smallest trench width among the multiple trenches provided on the surface of wafer W has a trench width larger than a preset reference width that is not closed by the film formation process formed by process SQ1, etc. (at least the opening of the trench is closed).

[0101] like Figure 9 As shown, a film LA is formed on the surface of wafer W (the surface MK1 of mask MK and the inner surface of the trenches of wafer W) through the film formation processes SQ1 and ST3h. After the formation of film LA, trench TR1 has a trench width WW2a, and trench TR2 has a trench width WW2b. In trench TR1, the value of the trench width WW2a after the formation of film LA is smaller than the value of the trench width WW1a before the formation of film LA; in trench TR2, the value of the trench width WW2b after the formation of film LA is smaller than the value of the trench width WW1b before the formation of film LA. Figure 9 The grooves TR1 and TR2 shown are respectively with Figure 2 The trenches TR1 and TR2 shown correspond to each other and are located in the same region ER (more specifically, for example, any of the center of the surface of wafer W, the middle part of the surface of wafer W, or the end of the surface of wafer W). The film thickness WF1a of film LA in trench TR1 and the film thickness WF1b of film LA in trench TR2 are approximately the same, regardless of the size of the trench width.

[0102] In step ST3i, following "Step ST3h: Yes", the wafer W is transported from the plasma processing device 10 to the optical observation device OC by transport robotic arms Rb1 and Rb2, and the wafer W is then placed into the optical observation device OC. After step ST3i, step ST3 ends, and the process returns to step ST1 to repeat the processing after step ST1.

[0103] Next, refer to Figure 10 Explain step ST5. Figure 10 It means Figure 1The flowchart illustrates an example of step ST5, the step for adjusting the trench width, included in method MT. Step ST5 includes: step ST5a, step ST5b, process SQ2 (second process), step ST5g, and step ST5h. Process SQ2 includes: step ST5c (tenth step), step ST5d (eleventh step), step ST5e (twelfth step), and step ST5f (thirteenth step). Processes SQ2 and ST5g perform etching using nitrogen-induced surface modification, similar to the ALE (Atomic Layer Etching) method, to adjust and expand the trench width.

[0104] More specifically, following "Step ST4: Yes" Figure 1 In step ST5a, the wafer W is moved from the optical observation device OC to the plasma processing apparatus 10 via transport robotic arms Rb1 and Rb2, and is then placed into the processing container 192 of the plasma processing apparatus 10. In step ST5b following step ST5a, the wafer W placed in the processing container 192 of the plasma processing apparatus 10 is aligned and mounted on an electrostatic chuck ESC. Furthermore, step ST5 can also be performed using a different plasma processing apparatus than the one used in step ST3.

[0105] Following step ST5b, in process SQ2, the film LA formed on the surface of wafer W in step ST3 is etched isotropically and uniformly throughout all trenches on the entire surface of wafer W using the same method as the ALE method. The amount of etching (the thickness of the portion of film LA etched in process SQ2) becomes uniform (approximately the same) across all trenches on the entire surface of wafer W. The series of steps SQ2 and ST5g involves isotropically and uniformly etching the film LA formed on the surface of wafer W in step ST3 throughout all trenches on the entire surface of wafer W until the trench width of all trenches is expanded to a predetermined reference width position.

[0106] In step ST5c, a plasma containing a third gas is generated within the processing container 192 of the plasma processing apparatus 10 housing the wafer W. A mixed layer MX containing ions from the plasma containing the third gas is isotropically and uniformly formed on the atomic layer of the film LA surface (particularly on the surface of the film LA formed on the inner surface of the trench of the wafer W). Through step ST5c, a mixed layer MX containing ions from the plasma containing the third gas can be isotropically and uniformly formed on the atomic layer of the film LA surface. In step ST5c, with the wafer W placed on an electrostatic chuck ESC, a third gas is supplied into the processing container 192 to generate a plasma containing the third gas. The third gas contains nitrogen, and in one embodiment, it may contain, for example, N2 gas. Specifically, a third gas containing N2 gas is supplied into the processing container 192 from a gas source selected from a plurality of gas sources selected from gas supply source 122. Furthermore, high-frequency power is supplied from high-frequency power supplies 150A and 150B, and high-frequency bias voltage is supplied from high-frequency power supply 64, causing the exhaust device 50 to operate, thereby setting the pressure of the processing space Sp within the processing container 192 to a preset value (set value).

[0107] The pressure setting of the processing space Sp in step ST5c is relatively high, above 200 [mTorr], and in one embodiment, for example, it can be 400 [mTorr]. When the pressure of the processing space Sp is relatively high, the nitrogen atoms contained in the plasma of the third gas (hereinafter referred to as nitrogen ions) are isotropically contacted with the surface of the membrane LA, and the surface of the membrane LA is isotropically and uniformly modified by the nitrogen ions, thereby, as Figure 11 As shown, a mixed layer MX of uniform (approximately the same) thickness is formed on the entire surface of wafer W, similar to the surface of film LA. Figure 11 The grooves TR1 and TR2 shown are respectively connected to... Figure 9 The trenches TR1 and TR2 shown correspond to each other and are located in the same region ER (more specifically, for example, the center of the surface of wafer W, the middle part of the surface of wafer W, or any of the ends of the surface of wafer W).

[0108] Figure 12 It means Figure 10 The diagram shows how the isotropic and anisotropic etching in process SQ2 is affected by pressure. Figure 12 The vertical axis on the left represents the etching amount [nm] (the thickness of the portion of film LA that has been surface-modified by step ST5c, corresponding to the thickness of the portion that can be removed by etching in process SQ2, which includes step ST5c). Figure 12 The right vertical axis represents the aspect ratio (the value obtained by dividing the amount of etching on the bottom side (vertical) of the trench by the amount of etching on the side side (horizontal) of the trench). Figure 12 The line GRb1 represents the variation in the amount of etching on the bottom (vertical) side of the trench. Figure 12 The line GRb2 represents the variation in the amount of etching on the side (lateral) side of the trench. Figure 12 The line GRb3 represents the change in aspect ratio (the value obtained by dividing the amount of etching on the bottom (vertical) side of the trench by the amount of etching on the side (horizontal) side of the trench. Figure 12 The result represented by the region GDa is the result obtained by performing step ST5c 30 times, assuming the pressure of the processing space Sp is 400 [mTorr], the value of the high-frequency power is 600 [W], the value of the high-frequency bias power is 50 [W], and the processing time is 30 [s]. Figure 12 The result represented by the region GDb is the result obtained by performing step ST5c 20 times, assuming the pressure of the processing space Sp is 20 [mTorr], the high-frequency power is 0 [W], the high-frequency bias power is 50 [W], and the processing time is 10 [s]. Figure 12 As shown, when the pressure of the processing space Sp is a relatively high pressure of 400 [mTorr] (results represented by region GDa), isotropic etching can be achieved in the process SQ2 based on surface modification using the ALE method.

[0109] Reference Figure 13 Confirm in more detail Figure 12 The results are shown. Figure 13 It means Figure 10 The graph shows the relationship between the isotropy of etching and pressure in process SQ2. Figure 13 The vertical axis represents the etching amount [nm] (the thickness of the portion of film LA that has been surface-modified by step ST5c, corresponding to the thickness of the portion that can be removed by etching in process SQ2, which includes step ST5c). Figure 13 The horizontal axis represents the pressure [mTorr] of the processing space Sp. Figure 13 The line GRc1 represents the variation in the amount of etching on the bottom (vertical) side of the trench. Figure 13 The line GRc2 represents the variation in the amount of etching on the side (lateral) side of the trench. Figure 13 The line GRc3 represents the change in aspect ratio (the value obtained by dividing the etching amount on the bottom (vertical) side of the trench by the etching amount on the side (horizontal) side of the trench. For example... Figure 13 As shown, when the pressure of the processing space Sp is a relatively high pressure of 200 [mTorr] or more (for example, 400 [mTorr] in one embodiment), fully isotropic etching can be achieved in the process SQ2 based on surface modification using the ALE method.

[0110] In step ST5c, as described above, a plasma of a third gas is generated within the processing container 192. Nitrogen ions contained in this plasma are introduced in a vertical direction (from the top side of the processing container 192 (specifically, for example, the side of the plate-shaped dielectric body 194) towards the surface of the wafer W mounted on the electrostatic chuck ESC) due to a high-frequency bias power, thereby contacting the surface of the film LA. The surface of the film LA is isotropically modified. Thus, in step ST5c, the surface of the film LA becomes a mixed layer MX of uniform thickness (approximately the same thickness) across the entire surface of the wafer W. The third gas contains nitrogen, and the film LA contains silicon oxide (e.g., SiO2 in one embodiment), therefore the composition of the mixed layer MX may, in one embodiment, be, for example, SiN / SiO2 (SiON).

[0111] The processing time in step ST5c is the time longer than the time required for the ALE method to reach the self-limiting region. Figure 14 It means in Figure 10 A diagram illustrating the self-limiting nature of surface modification in process SQ2 (particularly step ST5c). Figure 14 The horizontal axis represents the processing time [s] for surface modification (more specifically, the treatment performed in step ST5c). Figure 14 The vertical axis represents the etching amount [nm] (the thickness of the portion of film LA that has been surface modified by step ST5c). Figure 14 The results shown are the results obtained by executing step ST5c, assuming the pressure of the processing space Sp is 400 [mTorr], the high-frequency power is 600 [W], and the high-frequency bias power is 50 [W]. Figure 14 As shown, the surface modification performed by step ST5c is self-limiting. That is, if the surface modification is performed for a time longer than the time required for the self-limiting region of the ALE method, the surface modification can be performed isotropically and uniformly regardless of the location of the surface of the wafer W (more specifically, for example, the center of the surface of the wafer W, the middle part of the surface of the wafer W, and the end of the surface of the wafer W) and regardless of the size of the trench width. Similarly, an isotropic and uniform hybrid layer MX can be formed on the surface of the wafer W (the surface MK1 of the mask MK and the inner surface of the trenches (including trenches TR1 and TR2) of the wafer W).

[0112] Figure 15 Including parts (a), (b), and (c), it represents... Figure 10 A diagram illustrating the principle of etching in the steps shown. Figure 15In the diagram, blank circles (white circles) represent atoms constituting the membrane LA (e.g., atoms constituting SiO2 in one embodiment), black circles represent nitrogen ions contained in the plasma of the third gas, and "×" surrounded by circles represent free radicals contained in the plasma of the fourth gas, as described later. Figure 15 As shown in part (a), through step ST5c, nitrogen ions (circles with black centers) contained in the plasma of the third gas are isotropically supplied to the atomic layer on the surface of the membrane LA. Thus, through step ST5c, a mixed layer MX containing atoms constituting the membrane LA and nitrogen atoms of the third gas is formed on the surface of the membrane LA (see reference). Figure 15 part (a) and Figure 11 ).

[0113] As described above, since the third gas contains nitrogen, nitrogen atoms are supplied to the atomic layer (atomic layer of silicon oxide) on the surface of the membrane LA in step ST5c, which enables the formation of a mixed layer MX containing silicon oxide (e.g., SiN / SiO2 in one embodiment) on the atomic layer on the surface of the membrane LA.

[0114] In step ST5d following step ST5c, the processing space Sp within the processing container 192 is purged. Specifically, in step ST5c, the supplied third gas is exhausted. In step ST5d, an inert gas, such as a rare gas (e.g., Ar gas in one embodiment), can be supplied to the processing container 192 as the purging gas. That is, the purging in step ST5d can be either purging with a gas that allows the inert gas to circulate within the processing container 192 or purging based on vacuum.

[0115] In step ST5e, following step ST5d, a plasma of a fourth gas is generated in the processing container 192. The entire mixed layer MX is removed by chemical etching using the free radicals contained in this plasma. Thus, the film LA can be etched isotropically and uniformly across the entire surface of the wafer W (particularly in the film LA formed on the inner surface of all trenches). In step ST5e, with the wafer W after the formation of the mixed layer MX in step ST5c placed on an electrostatic chuck (ESC), a fourth gas is supplied to the processing container 192 to generate a plasma of the fourth gas. The plasma of the fourth gas generated in step ST5e contains free radicals that remove the mixed layer MX, which comprises silicon nitrides. The fourth gas contains fluorine, and in one embodiment, it may be, for example, a mixture of NF3 gas and O2 gas. Furthermore, the fourth gas may be a mixture of NF3 gas, O2 gas, H2 gas, and Ar gas, or a mixture of CH3F gas, O2 gas, and Ar gas, etc. Specifically, the fourth gas is supplied to the processing container 192 from a gas source selected from multiple gas sources of the gas supply source 122, and high-frequency power is supplied from high-frequency power sources 150A and 150B to activate the exhaust device 50, thereby setting the pressure of the processing space Sp in the processing container 192 to a preset value. In this way, plasma of the fourth gas can be generated in the processing container 192.

[0116] like Figure 15 As shown in part (b), the free radicals in the plasma of the fourth gas generated in step ST5e (in) Figure 15 In part (b), the "×" surrounded by a circle contacts the mixed layer MX on the surface of the membrane LA, and supplies free radicals of the fourth gas atoms to the mixed layer MX formed on the surface of the membrane LA. The mixed layer MX is removed from the membrane LA by chemical etching.

[0117] Figure 15 Part (c) and Figure 16 As shown, the mixed layer MX formed on the surface of membrane LA in step ST5c can be removed from the surface of membrane LA by free radicals contained in the plasma of the fourth gas. The trench width WW3a of trench TR1 after the mixed layer MX has been removed (…). Figure 16 The value of ) is greater than the trench width WW2a of the trench TR1 before the formation of the hybrid layer MX. Figure 9 The value of ) is large, and the trench width WW3b of the trench TR2 after removing the mixing layer MX is large. Figure 16 The value of ) is greater than the trench width WW2b of the trench TR2 before the formation of the hybrid layer MX. Figure 9 The value of ) is large. The film thickness WF2a of the membrane LA after removing the mixed layer MX in trench TR1 is large. Figure 16The value of ) is greater than the film thickness WF1a of the film LA before the formation of the mixing layer MX of the trench TR1. Figure 9 The value of ) is small, and the film thickness WF2b of the membrane LA after removing the mixed layer MX in trench TR2 is small. Figure 16 The value of ) is greater than the film thickness WF1b of the film LA before the formation of the mixed layer MX of trench TR2. Figure 9 The value of ) is small. Furthermore, because the thickness of the hybrid layer MX is approximately uniform (approximately the same) throughout all trenches on the surface of the wafer W, the trench width WW3a of trench TR1 is small. Figure 16 The value of ) minus the trench width WW2a( Figure 9 The value obtained is related to the trench width WW3b of trench TR2. Figure 16 The value of ) minus the trench width WW2b( Figure 9 The values ​​obtained are approximately the same, and approximately the same as twice the thickness of the mixing layer MX. Thus, due to the removal of the mixing layer MX, trenches TR1 and TR2 are extended in the direction DR, and the trench width on the surface of wafer W increases isotropically and uniformly regardless of the location of the wafer W surface (more specifically, for example, the center of the wafer W surface, the middle portion of the wafer W surface, and the ends of the wafer W surface), and regardless of the size of the trench width. Furthermore, Figure 16 The grooves TR1 and TR2 shown correspond to respectively Figure 9 The trenches TR1 and TR2 shown are located in the same region ER (more specifically, for example, the center of the surface of wafer W, the middle part of the surface of wafer W, or any of the ends of the surface of wafer W).

[0118] In step ST5f, following step ST5e, the processing space Sp within the processing container 192 is purged. Specifically, the fourth gas supplied in step ST5e is exhausted. In step ST5f, an inert gas, such as a rare gas (e.g., Ar gas in one embodiment), can be supplied to the processing container 192 as the purging gas. That is, the purging in step ST5f can be either purging with a gas that allows the inert gas to circulate within the processing container 192 or purging based on vacuum.

[0119] In step ST5g following process SQ2, it is determined whether the execution of process SQ2 has ended. Specifically, in step ST5g, it is determined whether the number of times process SQ2 has been executed has reached a preset number. The determination of the number of times process SQ2 is executed determines the etching amount of film LA. Process SQ2 can be repeatedly executed to etch film LA until the etching amount of film LA reaches the preset value. As the number of times process SQ2 is executed increases, the etching amount of film LA also increases (approximately linearly). Therefore, the number of times process SQ2 is executed can be determined in a way that the product of the thickness of film LA etched in one (unit cycle) of process SQ2 (the thickness of the mixed layer MX formed in one step ST5c) and the number of times process SQ2 is executed is the preset value.

[0120] Reference Figure 17 This illustrates the changes in the amount of etching on the film LA and the changes in the thickness of the mixed layer MX formed on the film LA during the execution of process SQ2. Figure 17 The line GL1 represents the change in the amount of etching (in arbitrary units) of the film LA produced during the execution of process SQ2. Figure 17 The line GL2 represents the change in thickness (in arbitrary units) of the hybrid layer MX generated during the execution of process SQ2. Figure 17 The horizontal axis represents the execution time of process SQ2, while the execution times of steps ST5d and ST5f are omitted for the sake of diagrammatic simplicity. Figure 17 As shown, in one execution of process SQ2 (unit cycle), as indicated by line GL2, step ST5c is executed until the thickness of the mixing layer MX reaches a preset value TW. The value TW of the thickness of the mixing layer MX formed in step ST5c is determined by the value of the bias power applied by the high-frequency power supply 64, the dose per unit time of nitrogen ions contained in the plasma of the third gas relative to the membrane LA, and the execution time of step ST5c.

[0121] like Figure 17As shown, in one execution (unit cycle) of process SQ2, as indicated by lines GL1 and GL2, step ST5e is executed until the mixed layer MX formed in step ST5c is completely removed. During the execution of step ST5e, the mixed layer MX is completely removed by chemical etching until time TI is reached. Time TI can be determined by the etching rate of the chemical etching performed in step ST5e. Time TI is generated during the execution of step ST5e. During the period from time TI to the end of step ST5e, the silicon oxide film LA after the removal of the mixed layer MX is not etched by the plasma of the fourth gas. That is, when using free radicals contained in the plasma of the fourth gas, the etching rate of the silicon oxide constituting the film LA (in one embodiment, for example, SiO2) is very small compared to the etching rate of the silicon nitride (in one embodiment, for example, SiN) contained in the mixed layer MX.

[0122] In step ST5g, if it is determined that the number of times process SQ2 has been executed has not reached the preset number (step ST5g: No), the execution of process SQ2 is repeated. On the other hand, if it is determined in step ST5g that the number of times process SQ2 has been executed has reached the preset number (step ST5g: Yes), the process moves to step ST5h. In step ST5h, the wafer W is transported from the plasma processing apparatus 10 to the optical observation apparatus OC via transport robotic arms Rb1 and Rb2, and the wafer W is placed into the optical observation apparatus OC. After step ST5h, step ST5 ends, and the process returns to step ST1, repeating the processing after step ST1.

[0123] As described above, the series of isotropic etching processes SQ2 and ST5g, using the same method as the ALE method, can remove the surface of the film LA layer by layer. Therefore, the series of etching processes SQ2 and ST5g, by repeatedly performing process SQ2 to remove the surface of the film LA layer by layer, precisely etches the film LA regardless of the location of the wafer W surface (more specifically, for example, the center of the wafer W surface, the middle portion of the wafer W surface, and the ends of the wafer W surface) and regardless of the size of the trench width. That is, by repeatedly performing process SQ2 a predetermined number of times, the film LA can be etched with high precision and isotropically across the entire surface of the wafer W with a uniform thickness (approximately the same thickness), regardless of the location of the wafer W surface (more specifically, for example, the center of the wafer W surface, the middle portion of the wafer W surface, and the ends of the wafer W surface) and regardless of the size of the trench width.

[0124] Next, the effect of one implementation of method MT is explained by examining the change in the groove width accompanying the execution of method MT. Figure 18 It means to utilize Figure 1 The bar chart shows the effect of the method shown. Figure 18 The diagram illustrates the trench width in each of trenches TR1 and TR2 before the execution of method MT, the trench width after "Step ST2: Yes" (after the deviation of the trench width converges within the reference range), and the trench width after "Step ST4: No" (after the trench width (minimum value of the trench width) is extended above the reference width). Figure 18 The bars shown in the histogram (rectangle GC1, etc.) represent the groove width of trench TR1. Additionally, Figure 18 The bar chart shows all the rectangles (rectangle GC1, etc.) representing the groove width of trench TR2.

[0125] In rectangle GC1, each of trenches TR1 and TR2 represents the trench width (whether WW1a or WW1b) before the execution of method MT, and is the trench width (whether WW1a or WW1b) at the center of the surface of wafer W (TC). Rectangle GM1 represents the trench width (whether WW1a or WW1b) before the execution of method MT in each of trenches TR1 and TR2, and is the trench width (whether WW1a or WW1b) at the middle portion of the surface of wafer W, located outside (near the end) of the surface (TM). Rectangle GE1 represents the trench width (whether WW1a or WW1b) before the execution of method MT in each of trenches TR1 and TR2, and is the trench width (whether WW1a or WW1b) at the end of the surface of wafer W (TE).

[0126] like Figure 18 As shown, in each of trenches TR1 and TR2, there is a deviation in the trench width (trench width WW1a or trench width WW1b) before the execution of method MT on the surface of wafer W (covering the center of the surface of wafer W, the middle part of the surface of wafer W, and the end of the surface of wafer W). After "Step ST2: Yes", the deviation of the trench width (trench width WW2a or trench width WW2b) can converge within the reference range.

[0127] Rectangle GC2 represents the trench width (trench width WW2a or trench width WW2b) of each of trenches TR1 and TR2 after "Step ST2: Yes" (after the trench width deviation is converged within the reference range), and is the value (TH1) of the trench width (trench width WW2a or trench width WW2b) at the center of the surface of wafer W. Rectangle GM2 represents the trench width (trench width WW2a or trench width WW2b) of each of trenches TR1 and TR2 after "Step ST2: Yes" (after the trench width deviation is converged within the reference range), and is the value (TH1) of the trench width (trench width WW2a or trench width WW2b) at the middle portion of the surface of wafer W, located outside (near the end) of the surface. Rectangle GE2 represents the trench width (trench width WW2a or trench width WW2b) in each of trenches TR1 and TR2 after "Step ST2: Yes" (after the trench width deviation is converged within the reference range) and is the value (TH1) of the trench width (trench width WW2a or trench width WW1b) at the end of the surface of wafer W.

[0128] like Figure 18 As shown, in both trenches TR1 and TR2, after "Step ST2: Yes" (after the trench width deviation converges within the reference range), the trench width (trench width WW2a or trench width WW2b) is unified into a uniform trench width (TH1), but narrower than the reference width (TH2). Therefore, after "Step ST4: No", the trench width (the minimum trench width) is extended to above the reference width (TH2).

[0129] Rectangle GC3 represents the trench width (trench width WW3a or trench width WW3b) at the center of the surface of wafer W after "Step ST4: No" (after extending the trench width (minimum trench width) above the reference width) in both trenches TR1 and TR2 (TH2). Rectangle GM3 represents the trench width (trench width WW3a or trench width WW3b) at the middle of the surface of wafer W, located outside (near the end) of the surface from the center of the surface (TH2). Rectangle GE3 represents the trench width (trench width WW3a or trench width WW3b) at the end of the surface of the wafer W after "Step ST4: No" (after extending the trench width (minimum trench width) above the reference width) in both trench TR1 and trench TR2 (TH2).

[0130] like Figure 18 As shown, in each of trenches TR1 and TR2, after "Step ST2: Yes" (after the trench width deviation is converged within the reference range), by repeatedly executing step ST5, the trench width (the minimum value of the trench width) can be made into the reference width (TH2). Therefore, in each of trenches TR1 and TR2, the trench width (trench width WW1a or trench width WW1b) that had a deviation in the surface of wafer W before executing method MT can be sufficiently eliminated and precisely unified into the reference width (TH2) by executing method MT, regardless of the location on the surface of wafer W (the center of the surface of wafer W, the middle part of the surface of wafer W, and the ends of the surface of wafer W).

[0131] Reference Figure 19 To provide a more detailed explanation. Figure 19 Including parts (a) and (b), it indicates the use of Figure 1 A bar chart illustrating an example of the effect of the method shown. Figure 19Part (a) schematically shows: the respective groove widths (groove width WW1a and groove width WW1b) of groove TR1 and groove TR2 before the execution of method MT, the respective groove widths (groove width WW2a and groove width WW2b) of groove TR1 and groove TR2 after "Step ST2: Yes" (after the deviation of the groove width is converged within the reference range), and the respective groove widths (groove width WW3a and groove width WW3b) of groove TR1 and groove TR2 after "Step ST4: No" (after the groove width (minimum value of the groove width) is extended to above the reference width).

[0132] Rectangle GCa1 represents the trench width WW1a of trench TR1 before the execution of method MT, and is the value of the trench width WW1a (WW1aC) at the center of the surface of wafer W. Rectangle GCb1 represents the trench width WW1b of trench TR2 before the execution of method MT, and is the value of the trench width WW1b (WW1bC) at the center of the surface of wafer W. The relationships WW1bC > WW1aC and WW1bC - WW1aC = Δ1 are satisfied.

[0133] Rectangle GMa1 represents the trench width WW1a of trench TR1 before the execution of method MT, and is the value (WW1aM) of the trench width WW1a in the middle part of the surface of wafer W, located outside the center (near the end) of the surface. Rectangle GMb1 represents the trench width WW1b of trench TR2 before the execution of method MT, and is the value (WW1bM) of the trench width WW1b in the middle part of the surface of wafer W, located outside the center (near the end) of the surface. The relationships WW1bM > WW1aM and WW1bM - WW1aM = Δ1 are satisfied.

[0134] Rectangle GEa1 represents the trench width WW1a of trench TR1 before the execution of method MT, and is the value of the trench width WW1a at the end of the surface of wafer W (WW1aE). Rectangle GEb1 represents the trench width WW1b of trench TR2 before the execution of method MT, and is the value of the trench width WW1b at the end of the surface of wafer W (WW1bE). The relationships WW1bE > WW1aE and WW1bE - WW1aE = Δ1 are satisfied.

[0135] Rectangle GCa2 represents the trench width WW2a of trench TR1 after "Step ST2: Yes" (after the trench width deviation is converged within the reference range), and is the value of the trench width WW2a (WW2aC) at the center of the surface of wafer W. Rectangle GCb2 represents the trench width WW2b of trench TR2 after "Step ST2: Yes" (after the trench width deviation is converged within the reference range), and is the value of the trench width WW2b (WW2bC) at the center of the surface of wafer W. The relationships WW2bC > WW2aC and WW2bC - WW2aC = Δ1 are satisfied.

[0136] Rectangle GMa2 represents the trench width WW2a of trench TR1 after "Step ST2: Yes" (after the trench width deviation is converged within the reference range), and is the value (WW2aM) of the trench width WW2a in the middle part of the surface of wafer W, located outside the center (near the end) of the surface. Rectangle GMb2 represents the trench width WW2b of trench TR2 after "Step ST2: Yes" (after the trench width deviation is converged within the reference range), and is the value (WW2bM) of the trench width WW2b in the middle part of the surface of wafer W, located outside the center (near the end) of the surface. The relationships WW2bM > WW2aM and WW2bM - WW2aM = Δ1 are satisfied.

[0137] Rectangle GEa2 represents the trench width WW2a of trench TR1 after "Step ST2: Yes" (after the trench width deviation converges within the reference range), and is the value of the trench width WW2a (WW2aE) at the end of the surface of wafer W. Rectangle GEb2 represents the trench width WW2b of trench TR2 after "Step ST2: Yes" (after the trench width deviation converges within the reference range), and is the value of the trench width WW2b (WW2bE) at the end of the surface of wafer W. The relationships WW2bE > WW2aE and WW2bE - WW2aE = Δ1 are satisfied.

[0138] In trench TR1, the relationships WW2aC=WW2aM=WW2aE are satisfied, and in trench TR2, the relationships WW2bC=WW2bM=WW2bE are satisfied.

[0139] Therefore, after "Step ST2: Yes", the deviation of the trench width of the trench TR1 on the surface of the wafer W (the deviation of the center of the surface of the wafer W, the middle part of the surface of the wafer W, and the end of the surface of the wafer W) and the deviation of the trench width of the trench TR2 on the surface of the wafer W (the deviation of the center of the surface of the wafer W, the middle part of the surface of the wafer W, and the end of the surface of the wafer W) can be maintained at the difference (Δ1) between the trench width of the trench TR2 and the trench width of the trench TR1, and the above deviations can be eliminated.

[0140] Rectangle GCa3 represents the trench width WW3a of trench TR1 after "Step ST4: No" (after the trench width (minimum trench width) is expanded to above the reference width), and is the value of the trench width WW3a (WW3aC) at the center of the surface of wafer W. Rectangle GCb3 represents the trench width WW3b of trench TR2 after "Step ST4: No" (after the trench width (minimum trench width) is expanded to above the reference width), and is the value of the trench width WW3b (WW3bC) at the center of the surface of wafer W. The relationships WW3bC > WW3aC and WW3bC - WW3aC = Δ1 are satisfied.

[0141] Rectangle GMa3 represents the trench width WW3a of trench TR1 after "Step ST4: No" (after the trench width (minimum trench width) is expanded to above the reference width), and is the value of the trench width WW3a (WW3aM) of the middle part of the surface of wafer W located outside the center (near the end) of the surface. Rectangle GMb3 represents the trench width WW3b of trench TR2 after "Step ST4: No" (after the trench width (minimum trench width) is expanded to above the reference width), and is the value of the trench width WW3b (WW3bM) of the middle part of the surface of wafer W located outside the center (near the end) of the surface. The relationships WW3bM>WW3aM and WW3bM-WW3aM=Δ1 are satisfied.

[0142] Rectangle GEa3 represents the trench width WW3a of trench TR1 after "Step ST4: No" (after expanding the trench width (minimum trench width) to above the reference width), and is the value of the trench width WW3a (WW3aE) at the end of the surface of wafer W. Rectangle GEb3 represents the trench width WW3b of trench TR2 after "Step ST4: No" (after expanding the trench width (minimum trench width) to above the reference width), and is the value of the trench width WW3b (WW3bE) at the end of the surface of wafer W. The relationships WW3bE > WW3aE and WW3bE - WW3aE = Δ1 are satisfied.

[0143] In trench TR1, the relationship WW3aC = WW3aM = WW3aE is satisfied, and in trench TR2, the relationship WW3bC = WW3bM = WW3bE is satisfied. Furthermore, in trench TR1, WW3aC (=WW3aM=WW3aE) is larger than WW2aC (=WW2aM=WW2aE), and in trench TR2, WW3bC (=WW3bM=WW3bE) is larger than WW2bC (=WW2bM=WW2bE).

[0144] Therefore, in trenches TR1 and TR2, the trench widths that deviate on the surface of wafer W before the execution of method MT can be maintained by the execution of method MT. The difference (Δ1) between the trench width of trench TR2 and the trench width of trench TR1 can be maintained, and the deviations on the surface of wafer W (the deviations existing in the center, middle, and ends of the surface of wafer W) can be fully eliminated. Moreover, the deviations can be precisely unified to the reference width.

[0145] Furthermore, in order to unify the trench width to a reference width, step ST5 was not used. Instead, the film LA was etched using an existing etching method (a method different from method MT, hereinafter referred to as etching method EM). Figure 19 As shown in part (b), the difference between the groove width of trench TR2 and the groove width of trench TR2 (Δ2) becomes larger compared to the difference between the groove width of trench TR2 and the groove width of trench TR2 before the execution of method MT (Δ1). That is, it is possible for Δ2 > Δ1.

[0146] Rectangle GCa4 represents the trench width WW3a of trench TR1 after etching method EM in the prior art, and is the value of the trench width WW3a at the center of the surface of wafer W. Rectangle GCb4 represents the trench width WW3b of trench TR2 after etching method EM in the prior art, and is the value of the trench width WW3b at the center of the surface of wafer W. Rectangle GMa4 represents the trench width WW3a of trench TR1 after etching method EM in the prior art, and is the value of the trench width WW3a at the middle portion of the surface of wafer W, located outside the center (near the end) of the surface. Rectangle GMb4 represents the trench width WW3b of trench TR2 after etching method EM in the prior art, and is the value of the trench width WW3b at the middle portion of the surface of wafer W, located outside the center (near the end) of the surface. Rectangle GEa4 represents the trench width WW3a of trench TR1 after etching method EM in the prior art, and is the value of the trench width WW3a at the end of the surface of wafer W. Rectangle GEb4 represents the trench width WW3b of trench TR2 after etching method EM in the prior art, and is the value of the trench width WW3b at the end of the surface of wafer W.

[0147] like Figure 19 As shown in part (b), in order to unify the trench width to a reference width, when etching the film LA using the existing etching method EM, the difference (Δ2) between the trench width of the trench TR2 after the etching method EM and the trench width of the trench TR2 can become larger compared to the difference (Δ1) between the trench width of the trench TR2 before the execution method MT.

[0148] Furthermore, if the film thickness LA formed through steps ST1 to ST3 is relatively thick, there is a possibility that the opening of the trench may be closed in a trench with a relatively narrow trench width. To address this, the film thickness LA formed through steps ST1 to ST3 is made relatively thin so that the trench opening is not closed, and the basic steps of method MT can be repeatedly executed. The basic steps are repeatedly executed until the trench width (more specifically, the smallest trench width among the multiple trench widths provided on the surface of wafer W) reaches the reference width. In this case, the reference range of the trench width used in step ST2 is narrowed in stages each time method MT is repeatedly executed. Figure 20 This schematically represents the repeated execution within each of trenches TR1 and TR2. Figure 1 The diagram illustrates the morphology of the groove width variation when using the method shown. More specifically, Figure 20The diagram shows the variation in trench width of trench TR1 (or trench TR2) at the center of the surface of wafer W, and the variation in trench width of trench TR1 (or trench TR2) at the ends of the surface of wafer W. Furthermore, Figure 20 The content represented in the text (lines GRd1 and GRd2) corresponds only to trench TR1 or only to trench TR2.

[0149] Figure 20 The horizontal axis represents processing time. Figure 20 The vertical axis represents the trench width. Line GRd1 shows the variation in the trench width (WC) of trench TR1 (or trench TR2) at the center of the surface of wafer W. Line GRd2 shows the variation in the trench width (WE) of trench TR1 (or trench TR2) at the ends of the surface of wafer W. When line GRd1 represents the variation in the trench width of trench TR1, line GRd2 also represents the variation in the trench width of trench TR1. Similarly, when line GRd1 represents the variation in the trench width of trench TR2, line GRd2 also represents the variation in the trench width of trench TR2.

[0150] At the start of method MT, the trench width WC of the trench TR1 (or trench TR2) at the center of the surface of wafer W is narrower than the trench width WE of the trench TR1 (or trench TR2) at the end of the surface of wafer W. In interval V1, step ST3 is executed one or more times, and at time TM1, a judgment of "Step ST2: Yes" is made. In interval V2, step ST5 is executed one or more times, and at time TM2, a judgment of "Step ST4: No" is made. The difference (H1) between the trench width WC and the trench width WE at time TM1 exists within the reference range used for the judgment at time TM1. Each time method MT is repeated, the reference range used for the judgment at time TM1 (more specifically, in step ST2) is as follows: Figure 20 The trench width narrows in stages as shown. Therefore, the difference (H1) between the trench width value WC and the trench width value WE can gradually decrease during each repetition of the basic steps. Furthermore, through the etching based on surface modification using the ALE method (step ST5) performed in interval V2, the film LA is isotropically and uniformly etched across the entire surface of the wafer W. Therefore, the difference (H1) between the trench width value WC and the trench width value WE at time TM1 is maintained from time TM1 through interval V2 until time TM2.

[0151] In the above method, the film thickness formed during the film formation process of step SQ1, which is performed repeatedly using the same method as the ALD method, varies depending on the temperature of the film formation surface (the surface of the wafer W, particularly the inner surface of the trench). Based on this, in order to reduce the deviation of the trench width of the multiple trenches provided on the surface of the wafer W (and to improve the in-plane uniformity of the trench width on the surface of the wafer W), in step ST3c, the film formation process is performed after adjusting the temperature of each region ER on the surface of the wafer W. This reduces the deviation of the trench width of the multiple trenches provided on the surface of the wafer W and allows for the precise formation of a silicon oxide film LA on the inner surface of the trench at every atomic layer height. Furthermore, when the trench width of the trench where the film LA is formed is narrower than the reference width, in order to expand the trench width, the etching process of step SQ2 is performed repeatedly using the same method as the ALE method. Therefore, the surface of the film LA provided on the inner surface of the trench can be etched isotropically and uniformly, and the trench width can be adjusted to the desired reference width. Therefore, when there is a deviation in the trench width on the surface of wafer W, the deviation can be significantly reduced, and the trench width can be precisely adjusted to the desired reference width.

[0152] Furthermore, the basic steps of method MT return to step ST1 after performing step ST3 and step ST5. In this way, after performing step ST3 to adjust the trench width by forming film LA and step ST5 to expand the trench width by etching film LA, the process returns to step ST1 to measure the trench width, thus enabling more precise adjustment of the trench width.

[0153] Furthermore, the basic steps of method MT are repeatedly performed, with the reference range narrowing progressively with each repetition of the basic steps. In this way, by repeatedly performing the basic steps while progressively narrowing the reference range of the trench width deviation, the trench width can be adjusted while the thickness of the film formed in step ST3 is increased progressively and relatively gently. Therefore, even if the trench width includes relatively narrow trenches, the situation where the trench opening is closed due to film formation can be avoided.

[0154] In addition, the first gas G1 contains a monoaminosilane. Thus, using the first gas G1 containing a monoaminosilane enables the formation of silicon reaction precursors.

[0155] Furthermore, the aminosilane gas in the first gas G1 can contain aminosilanes with 1 to 3 silicon atoms. Therefore, for the aminosilane gas in the first gas G1, aminosilanes with 1 to 3 silicon atoms can be used.

[0156] Alternatively, the fourth gas can be: a mixture of NF3 and O2; a mixture of NF3, O2, H2, and Ar; or a mixture of CH3F, O2, and Ar. In this way, a fourth gas containing fluorine can be achieved.

[0157] The principles of the invention have been illustrated and described above with reference to appropriate embodiments. Those skilled in the art will recognize that variations in configuration and detailed technical content can be made without departing from these principles. The invention is not limited to the specific structures disclosed in the embodiments. Therefore, all modifications and changes made within the scope and spirit of the claims are requested.

Claims

1. A plasma processing apparatus characterized by comprising: Comprising: a processing vessel having a gas introduction port and an exhaust port; a plasma source that generates plasma in the processing vessel; a stage that supports a processed object in the processing vessel; and a control section that controls the apparatus to place a processed object having a plurality of grooves each having a groove width on the stage, acquires values of the groove widths of the plurality of grooves, and deposits a film based on the acquired values of the groove widths so that a variation in groove width is within a predetermined range, thereby adjusting the groove width of each of the plurality of grooves.

2. The plasma processing apparatus according to claim 1, wherein: the control section further repeatedly adjusts the groove width so that the adjusted groove width is within the predetermined range and narrower than a reference value of the groove width.

3. The plasma processing apparatus according to claim 1, wherein: the control section further causes the adjusted groove width to be within the predetermined range by comparing the value of the groove width with at least one reference value or comparing the value of the groove width of one groove with the value of the groove width of another groove.

4. The plasma processing apparatus according to claim 1, wherein: when the film is deposited, a temperature of two or more regions on the processed object is adjusted based on the acquired value of the groove width of each of the plurality of grooves of the processed object, an adsorption layer is formed on a surface of the groove of the processed object by supplying a precursor gas to the surface of the groove, and a film is formed on the surface of the groove by supplying plasma to the adsorption layer.

5. The plasma processing apparatus according to claim 1, wherein: the control section further increases the groove width by etching after the film is deposited.

6. The plasma processing apparatus according to claim 4, wherein: the control section adjusts a temperature of two or more regions of the processed object based on the measured value of the groove width so that a thickness of the film deposited on the two or more regions of the processed object is different when the film is deposited.

7. The plasma processing apparatus according to claim 6, wherein: the control section acquires correspondence data in which information of a temperature and a film thickness is stored, and reduces a variation in groove width in the two or more regions of the processed object by adjusting the temperature in the two or more regions when the film is deposited.

8. The plasma processing apparatus according to claim 5, wherein: the etching includes a third step that repeatedly performs a first step and a second step as follows, the first step modifies a surface of the film in order to form a mixed layer, and the second step supplies plasma to the mixed layer in order to remove the mixed layer.

9. The plasma processing apparatus according to claim 5, wherein: the control section determines whether a variation in groove width exceeds a prescribed variation range based on the acquired value of the groove width, ​ ​ In a case where it is determined that the variation in the trench width exceeds the prescribed variation range, deposition of a film is performed so that the variation in the trench width is within the prescribed variation range, In a case where it is determined that the variation in the trench width is within the prescribed variation range, the etching is performed.

10. The plasma processing apparatus according to claim 1, wherein: the plurality of trenches include a first plurality of trenches having a first trench width, and a second plurality of trenches having a second trench width greater than the first trench width, the values of the trench widths include a value of the first trench width corresponding to the first plurality of trenches, and a value of the second trench width corresponding to the second plurality of trenches, the control section performs adjustment of the trench widths in a case where at least one of a variation in the value of the first trench width and a variation in the value of the second trench width exceeds a variation range set in advance.

11. A plasma processing apparatus, characterized by comprising: comprises: a processing container having a gas introduction port and an exhaust port; a plasma source that generates plasma in the processing container; a stage that supports a processed object in the processing container; and a control section, the control section controls the apparatus to place a processed object having a plurality of trenches each having a trench width on the stage, acquire values of the trench widths of the plurality of trenches, and perform a trench width adjustment step that provides a trench width adjusted based on the acquired values of the trench widths, the trench width adjustment step including at least a deposition step or an etching step, the adjusted trench width being within a variation range set in advance.

12. The plasma processing apparatus according to claim 11, wherein: in the deposition step, a film is deposited at different thicknesses in different regions of the substrate in order to reduce a variation in trench width.

13. The plasma processing apparatus according to claim 12, wherein: in order to change the thickness of the film deposited in different regions of the substrate based on data of a correlation between temperature and film thickness, the control section reduces the variation in the trench width by adjusting the temperature of the substrate in different regions of the substrate.

14. The plasma processing apparatus according to claim 11, wherein: in the trench width adjustment step, the control section determines whether the trench width is less than a width value set in advance, and performs the etching step in a case where it is determined that the trench width is less than the width value set in advance.

15. The plasma processing apparatus according to claim 11, wherein: the plurality of trenches include a first plurality of trenches having a first trench width, and a second plurality of trenches having a second trench width greater than the first trench width, the values of the trench widths include a value of the first trench width corresponding to the first plurality of trenches, and a value of the second trench width corresponding to the second plurality of trenches, the control section performs adjustment of the trench widths in a case where at least one of a variation in the value of the first trench width and a variation in the value of the second trench width exceeds a variation range set in advance. ​ 16. The plasma processing apparatus according to claim 11, wherein: the trench width adjusting step, judging whether or not a deviation of the trench width exceeds a range of a deviation set in advance, based on the obtained value of the trench width, and in the case where it is judged that the deviation of the trench width exceeds the range of the deviation set in advance, executing the depositing step so that the deviation of the trench width is within the range of the deviation set in advance, in the case where the deviation of the trench width is within the range of the deviation set in advance, judging whether or not the trench width is smaller than a value of the trench width set in advance, and in the case where it is judged that the trench width is smaller than the value of the trench width set in advance, executing the etching step.

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