A gallium oxide power transistor with low ohmic contact and a manufacturing method thereof

Abstract

This invention discloses a low-ohmic contact gallium oxide power transistor and its fabrication method. The fabrication method includes: growing a β-Ga2O3 UID layer on a β-Ga2O3 substrate; growing a lightly doped β-Ga2O3 channel layer on the β-Ga2O3 UID layer; spin-coating a heavily doped SOG dielectric layer on the β-Ga2O3 channel layer; etching away the SOG dielectric layer except for the ohmic region; growing source and drain electrodes on the SOG dielectric layer in the ohmic region; growing an Al2O3 dielectric layer on the β-Ga2O3 channel layer, source electrode, drain electrode, and SOG dielectric layer; growing a gate electrode on the Al2O3 dielectric layer outside the ohmic region; etching away the Al2O3 dielectric layer on the source and drain electrodes; and depositing interconnect metal on the source and drain electrodes. This invention features a simple fabrication process and produces devices with lower ohmic contact on-resistance.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a gallium oxide power transistor with low ohmic contact and its fabrication method. Background Technology

[0002] Because β-Ga2O3 material has an ultra-wide bandgap and a high breakdown field strength, power devices made from β-Ga2O3 have the characteristics of high voltage resistance and high power, and have the potential for application in the field of power electronics.

[0003] In recent years, numerous scholars have been drawn to study β-Ga₂O₃ crystal materials and power devices. However, due to the high bandgap of gallium oxide, the quality of its ohmic contacts is difficult to guarantee, resulting in high ohmic contact on-resistance in fabricated devices. This high ohmic contact on-resistance limits the application of gallium oxide power transistors in the field of power electronics. Therefore, fabricating transistors that balance high breakdown voltage and low ohmic contact on-resistance remains a significant challenge for gallium oxide power transistors. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a gallium oxide power transistor with low-ohmic contact and a method for fabricating the same. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, embodiments of the present invention provide a method for fabricating a gallium oxide power transistor with a low-ohmic contact, comprising:

[0006] A β-Ga2O3 UID layer is grown on a β-Ga2O3 substrate;

[0007] A lightly doped β-Ga2O3 channel layer is grown on the β-Ga2O3 UID layer;

[0008] A heavily doped SOG dielectric layer is spin-coated onto the β-Ga2O3 channel layer;

[0009] The SOG dielectric layer, excluding the ohmic region, is etched away;

[0010] Source and drain electrodes are grown on the SOG dielectric layer within the ohmic region;

[0011] An Al2O3 dielectric layer is grown on the β-Ga2O3 channel layer, the source electrode, the drain electrode, and the SOG dielectric layer;

[0012] A gate electrode is grown on the Al2O3 dielectric layer outside the ohmic region;

[0013] The Al2O3 dielectric layer on the source electrode and the drain electrode is etched away.

[0014] Interconnect metal is deposited on the source electrode, the drain electrode, and the gate electrode.

[0015] In one embodiment of the present invention, growing a β-Ga2O3 UID layer on a β-Ga2O3 substrate includes:

[0016] On the β-Ga2O3 substrate, a material with a thickness of 100 nm to 500 nm and a carrier concentration of 1 × 10⁻⁶ is grown. 14 cm -3 ~1×10 16 cm -3 The β-Ga2O3 UID layer.

[0017] In one embodiment of the present invention, a lightly doped β-Ga2O3 channel layer is grown on the β-Ga2O3 UID layer, comprising:

[0018] A Si doping concentration of 1×10⁻⁶ nm with a thickness of 200 nm to 600 nm is grown on the β-Ga₂O₃ UID layer. 17 cm -3 ~5×10 18 cm -3 The β-Ga2O3 channel layer.

[0019] In one embodiment of the present invention, a heavily doped SOG dielectric layer is grown on the β-Ga2O3 channel layer, comprising:

[0020] A spin-coating with a thickness of 100 nm to 500 nm and a doping concentration of 5 × 10⁻⁶ nm is applied to the β-Ga₂O₃ channel layer. 18 cm -3 ~5×10 19 cm -3 The SOG dielectric layer.

[0021] In one embodiment of the present invention, a Sn doping concentration of 5 × 10⁻⁶ nm is spin-coated onto the β-Ga₂O₃ channel layer with a thickness of 100 nm to 500 nm. 18 cm -3 ~5×10 19 cm -3 The SOG dielectric layer.

[0022] In a second aspect, embodiments of the present invention provide a gallium oxide power transistor with a low-ohmic contact, comprising:

[0023] β-Ga2O3 substrate;

[0024] A β-Ga2O3 UID layer and a lightly doped β-Ga2O3 channel layer are sequentially disposed on the β-Ga2O3 substrate;

[0025] A heavily doped SOG dielectric layer is disposed on the β-Ga2O3 channel layer in the ohmic region;

[0026] The source electrode and drain electrode are respectively disposed on the SOG dielectric layer at both ends of the device;

[0027] An Al2O3 dielectric layer is disposed on the β-Ga2O3 channel layer outside the ohmic region and on the SOG dielectric layer;

[0028] The gate electrode is disposed on the Al2O3 dielectric layer.

[0029] In one embodiment of the present invention, the carrier concentration of the β-Ga2O3 UID layer is 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 The thickness ranges from 100nm to 500nm.

[0030] In one embodiment of the present invention, the β-Ga2O3 channel layer is lightly doped; the thickness of the β-Ga2O3 channel layer is 200 nm to 600 nm, and the doping concentration is 1 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 .

[0031] In one embodiment of the present invention, the SOG dielectric layer is heavily doped; the thickness of the SOG dielectric layer is 100 nm to 500 nm, and the doping concentration is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 .

[0032] In one embodiment of the present invention, the SOG dielectric layer is heavily Sn-doped; the thickness of the SOG dielectric layer is 100 nm to 500 nm, and the Sn doping concentration is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 .

[0033] The beneficial effects of this invention are:

[0034] The invention proposes a method for fabricating gallium oxide power transistors with low ohmic contacts. This method employs a novel process for fabricating source and drain ohmic electrodes. Compared to the commonly used ohmic region ion implantation process, this process is simpler, easier to implement, and lower in cost. Crucially, the embodiment of this invention fabricates the source and drain ohmic electrode structure by spin-coating a heavily doped SOG dielectric layer onto the β-Ga2O3 channel layer in the ohmic region, and then growing source and drain electrodes on the heavily doped SOG dielectric layer. Spin-coating the heavily doped SOG dielectric layer directly forms a heavily doped layer, and depositing ohmic metal on it can create a good ohmic contact, thereby reducing the ohmic contact on-resistance of the device and solving the problem of high ohmic contact on-resistance in current gallium oxide transistors. Experiments have verified that the source-drain ohmic electrode structure fabricated by spin-coating a heavily doped SOG dielectric layer on a β-Ga2O3 channel layer and then designing source and drain electrodes on the heavily doped SOG dielectric layer reduces the ohmic contact on-resistance by 40% compared to the existing method of fabricating source-drain ohmic electrode structures by ion implantation. This allows gallium oxide power transistors to be better applied in the field of power electronics.

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0036] Figure 1 This is a schematic flowchart of a method for fabricating a low-ohmic contact gallium oxide power transistor according to an embodiment of the present invention;

[0037] Figure 2 (a) to 2(h) are schematic diagrams of the corresponding structures of the low-ohmic contact gallium oxide power transistor fabrication process provided in the embodiments of the present invention;

[0038] Figure 3 This is a schematic diagram of a gallium oxide power transistor with a low-ohmic contact provided in an embodiment of the present invention.

[0039] Explanation of reference numerals in the attached figures:

[0040] 1-β-Ga2O3 substrate; 2-β-Ga2O3 UID layer; 3-β-Ga2O3 channel layer; 4-SOG dielectric layer; 5-Al2O3 dielectric layer; 6-source electrode; 7-drain electrode; 8-gate electrode. Detailed Implementation

[0041] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0042] To further reduce the ohmic contact on-resistance of gallium oxide power transistors, please refer to [link to relevant documentation]. Figure 1This invention provides a method for fabricating a gallium oxide power transistor with a low-ohmic contact, specifically including the following steps:

[0043] S10. Grow a β-Ga2O3 UID layer 2 on a β-Ga2O3 substrate 1.

[0044] This invention provides an optional solution; please refer to [link / reference]. Figure 2 (a) Molecular beam epitaxy (MBE) was used to grow Fe-doped (010) oriented β-Ga2O3 substrates with a thickness of 100 nm to 500 nm and a carrier concentration of 1 × 10⁻⁶. 14 cm -3 ~1×10 16 cm -3 β-Ga2O3 UID layer 2. More preferably, a 300 nm thick β-Ga2O3 substrate 1 with a carrier concentration of 1 × 10⁻⁶ is grown on an Fe-doped (010) oriented β-Ga2O3 substrate 1. 15 cm -3 The β-Ga2O3 UID layer 2. The Fe-doped (010) oriented β-Ga2O3 substrate 1 can be a substrate with an existing structure and does not need to be fabricated.

[0045] S20. A lightly doped β-Ga2O3 channel layer 3 is grown on the β-Ga2O3 UID layer 2.

[0046] This invention provides an optional solution; please refer to [link / reference]. Figure 2 (b) Using the MBE process, a β-Ga2O3 UID layer with a thickness of 200 nm to 600 nm and a doping concentration of 1 × 10⁻⁶ nm was grown on the UID layer 2. 17 cm -3 ~5×10 18 cm -3 A lightly doped β-Ga2O3 channel layer 3 is formed. More preferably, a 400 nm thick β-Ga2O3 UID layer 2 with a doping concentration of 1 × 10⁻⁶ is grown on the β-Ga2O3 UID layer 2. 18 cm -3 The lightly doped β-Ga2O3 channel layer 3.

[0047] S30, a heavily doped SOG dielectric layer 4 is spin-coated onto the β-Ga2O3 channel layer 3.

[0048] This invention provides an optional solution; please refer to [link / reference]. Figure 2 (c) A layer with a thickness of 100 nm to 500 nm and a doping concentration of 5 × 10⁻⁶ is uniformly spin-coated onto the β-Ga₂O₃ channel layer 3. 18 cm -3 ~5×1019 cm -3 The heavily doped SOG dielectric layer 4. More preferably, a layer with a thickness of 300 nm and a doping concentration of 1 × 10⁻⁶ is uniformly spin-coated onto the β-Ga₂O₃ channel layer 3. 19 cm -3 The heavily doped SOG dielectric layer 4. At this time, the heavily doped SOG dielectric layer 4 behaves as an N-type heavily doped layer.

[0049] The inventors discovered that, in the selection of heavily doped ions, a heavily doped layer formed by heavy Sn doping can achieve a lower ohmic contact on-resistance. A layer with a thickness of 100nm–500nm and a Sn doping concentration of 5×10⁻⁶ was uniformly spin-coated onto the β-Ga₂O₃ channel layer 3. 18 cm -3 ~5×10 19 cm -3 The heavily doped SOG dielectric layer 4. More preferably, a 300 nm thick Sn doping concentration layer is uniformly spin-coated onto the β-Ga2O3 channel layer 3. 19 cm -3 4. Heavily doped SOG dielectric layer.

[0050] The SOG dielectric layer 4 is dried by heating the liner.

[0051] S40, Etch away the SOG dielectric layer except for the ohmic region 4.

[0052] This invention provides an optional solution; please refer to [link / reference]. Figure 2 (d) The SOG dielectric layer 4, excluding the ohmic region, is selectively etched using inductively coupled plasma etching (ICP) with an etching depth of 100 nm to 500 nm, i.e., etched up to the upper surface of the β-Ga2O3 channel layer 3.

[0053] S50. A source electrode 6 and a drain electrode 7 are grown on the SOG dielectric layer 4 in the ohmic region.

[0054] This invention provides an optional solution; please refer to [link / reference]. Figure 2 (e) Using an electronic evaporation process, Ti / Au metal stacks with thicknesses of 20 / 200 nm are deposited on the SOG dielectric layer 4 in the ohmic region as the source and drain metals, respectively, to form the source electrode 6 and drain electrode 7. Rapid thermal annealing is then performed to alloy the ohmic metals, completing the fabrication of the source and drain ohmic electrodes.

[0055] Typically, source and drain ohmic electrodes are fabricated via ion implantation. However, ion implantation is a complex, time-consuming, and costly process, and it cannot guarantee the quality of the ohmic contact, resulting in high ohmic contact on-resistance in the fabricated device. To fabricate gallium oxide power transistors with lower ohmic contact on-resistance, this invention proposes a novel process for fabricating source and drain ohmic electrodes. This process, implemented in steps S30-S50, eliminates ion implantation and instead directly grows a heavily doped layer in the ohmic contact region. The inventors discovered that using existing, mature sputtering processes to directly grow a heavily doped layer in the ohmic contact region results in significant interface loss defects, leading to persistently high ohmic contact on-resistance. SOG, being a liquid material, eliminates the need for sputtering growth like other materials. By spin-coating heavily doped SOG, a heavily doped layer can be directly formed in the ohmic contact region. Depositing ohmic metal on this layer creates a good ohmic contact, thereby reducing the device's ohmic contact on-resistance. Experiments have verified that the method of fabricating source and drain ohmic electrodes by spin-coating a heavily doped SOG dielectric layer 4 onto the β-Ga2O3 channel layer 3, as described in this embodiment of the invention, reduces the ohmic contact on-resistance by 40% compared to existing methods of fabricating source and drain ohmic electrodes via ion implantation. For example, devices fabricated using conventional ion implantation typically have an ohmic contact on-resistance higher than 15 mΩ·cm. 2 The ohmic contact on-resistance of the device fabricated by the method of this invention can reach 9 mΩ·cm. 2 This allows gallium oxide power transistors to be better applied in the field of power electronics. Furthermore, through research by the inventors, it has been found that the heavily doped layer formed by heavy Sn doping in the SOG dielectric layer 4 can achieve a lower ohmic contact on-resistance. Experimental verification shows that the method of fabricating source and drain ohmic electrodes by spin-coating a heavily Sn-doped SOG dielectric layer 4 onto the β-Ga2O3 channel layer 3, compared to the existing method of fabricating source and drain ohmic electrodes through ion implantation, reduces the ohmic contact on-resistance by 50%, further enabling the application of gallium oxide power transistors in the field of power electronics.

[0056] S60. An Al2O3 dielectric layer 5 is grown on the β-Ga2O3 channel layer 3, source electrode 6, drain electrode 7 and SOG dielectric layer 4.

[0057] This invention provides an optional solution; please refer to [link / reference]. Figure 2 (f) An Al2O3 dielectric layer 5 with a thickness of 10 nm to 30 nm is grown on the β-Ga2O3 channel layer 3, source electrode 6, drain electrode 7 and SOG dielectric layer 4 using the MBE process. More preferably, an Al2O3 dielectric layer 5 with a thickness of 20 nm is grown on the β-Ga2O3 channel layer 3 outside the ohmic region.

[0058] S70. A gate electrode 8 is grown on the Al2O3 dielectric layer 5 outside the ohmic region.

[0059] This invention provides an optional solution; please refer to [link / reference]. Figure 2 (g) A Ni / Au metal stack with a thickness of 45 / 400 nm is deposited on the Al2O3 dielectric layer 5 outside the ohmic region using an electronic evaporation process to form the gate electrode 8.

[0060] S80, etch away the Al2O3 dielectric layer 5 on the source electrode 6 and the drain electrode 7.

[0061] This invention provides an optional solution; please refer to [link / reference]. Figure 2 (h) The Al2O3 dielectric layer 5 with a thickness of 10nm to 30nm on the source electrode 6 and the drain electrode 7 is selectively etched away using the ICP process, that is, selectively etched until the upper surface of the source electrode 6 and the drain electrode 7, exposing the source electrode 6 and the drain electrode 7, so as to facilitate subsequent interconnection.

[0062] S90. Interconnect metal is deposited on the source electrode 6, drain electrode 7, and gate electrode 8.

[0063] This invention provides an optional solution where interconnect metal is deposited on the source electrode 6, drain electrode 7, and gate electrode 8 using an electronic evaporation process, and the source electrode 6, drain electrode 7, and gate electrode 8 are connected via interconnect leads. The interconnect metal and interconnect leads are not illustrated here.

[0064] In summary, the method for fabricating a low-ohmic contact gallium oxide power transistor proposed in this invention presents a novel process for fabricating source and drain ohmic electrodes. Compared to the commonly used ohmic region ion implantation process, this process is simpler, easier to implement, and lower in cost. Crucially, this invention fabricates the source and drain ohmic electrode structure by spin-coating a heavily doped SOG dielectric layer 4 onto the β-Ga2O3 channel layer 3 in the ohmic region, and then growing the source electrode 6 and drain electrode 7 on the heavily doped SOG dielectric layer 4. Spin-coating the heavily doped SOG dielectric layer 4 directly forms a heavily doped layer, and depositing ohmic metal on it can form a good ohmic contact, thereby reducing the ohmic contact on-resistance of the device and solving the problem of high ohmic contact on-resistance in current gallium oxide transistors. Experiments have verified that the source-drain ohmic electrode structure fabricated by spin-coating a heavily doped SOG dielectric layer 4 onto the β-Ga2O3 channel layer 3, and then designing source electrodes 6 and drain electrodes 7 on the heavily doped SOG dielectric layer 4, reduces the ohmic contact on-resistance by 40% compared to existing methods using ion implantation. This allows gallium oxide power transistors to be better applied in the power electronics field. Furthermore, the inventors' research has shown that the heavily doped layer formed by heavy Sn doping in the SOG dielectric layer 4 can achieve even lower ohmic contact on-resistance. Experiments have verified that the source-drain ohmic electrode structure fabricated by spin-coating a heavily Sn doped SOG dielectric layer 4 onto the β-Ga2O3 channel layer 3, and then designing source electrodes 6 and drain electrodes 7 on the heavily doped SOG dielectric layer 4, reduces the ohmic contact on-resistance by 50% compared to existing methods using ion implantation. This further allows gallium oxide power transistors to be applied in the power electronics field.

[0065] Secondly, based on the above-described method for fabricating a gallium oxide power transistor with low-ohmic contacts, this invention provides a gallium oxide power transistor with low-ohmic contacts. Please refer to [link to relevant documentation]. Figure 3 ,include:

[0066] β-Ga2O3 substrate 1;

[0067] A β-Ga2O3 UID layer 2 and a lightly doped β-Ga2O3 channel layer 3 are sequentially disposed on the β-Ga2O3 substrate 1;

[0068] A heavily doped SOG dielectric layer 4 is disposed on the β-Ga2O3 channel layer 3 in the ohmic region;

[0069] The source electrode 6 and the drain electrode 7 are respectively disposed on the SOG dielectric layer 4 at both ends of the device;

[0070] Al2O3 dielectric layer 5 is disposed on the β-Ga2O3 channel layer 3 outside the ohmic region and on the SOG dielectric layer 4;

[0071] The gate electrode 8 is disposed on the Al2O3 dielectric layer 5.

[0072] Preferably, the carrier concentration of the β-Ga2O3 UID layer 2 is 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 The thickness ranges from 100nm to 500nm.

[0073] Preferably, the β-Ga2O3 channel layer 3 is lightly doped; the thickness of the β-Ga2O3 channel layer 3 is 200 nm to 600 nm, and the Si doping concentration is 1 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 .

[0074] Preferably, the SOG dielectric layer is heavily doped; the thickness of the SOG dielectric layer is 100 nm to 500 nm, and the doping concentration is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 .

[0075] Preferably, the SOG dielectric layer 4 is heavily Sn-doped; the thickness of the SOG dielectric layer 4 is 100 nm to 500 nm, and the Sn doping concentration is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 .

[0076] Preferably, the thickness of the Al2O3 dielectric layer 5 is 10nm to 30nm.

[0077] The low-ohmic-contact gallium oxide power transistor proposed in this invention presents a novel source-drain ohmic electrode structure. This structure is achieved by designing a heavily doped SOG dielectric layer 4 on the ohmic region of the β-Ga₂O₃ channel layer 3, and then designing the source electrode 6 and drain electrode 7 on the heavily doped SOG dielectric layer 4. The SOG dielectric layer 4 is directly a heavily doped layer, and depositing ohmic metal on it allows for the formation of good ohmic contacts, thereby reducing the ohmic contact on-resistance of the device and solving the problem of high ohmic contact on-resistance in current gallium oxide transistors. Experimental verification shows that, compared to existing methods that use ion implantation to form heavily doped layers to achieve the source-drain ohmic electrode structure, the method of designing a heavily doped SOG dielectric layer 4 on the β-Ga₂O₃ channel layer 3, and then designing the source electrode 6 and drain electrode 7 on the heavily doped SOG dielectric layer 4, reduces the ohmic contact on-resistance by 40%, making gallium oxide power transistors more suitable for application in power electronics. Furthermore, through the inventors' research, it has been found that the heavily doped layer formed by heavy Sn doping in the SOG dielectric layer 4 can achieve a lower ohmic contact on-resistance. Experimental verification shows that the method of designing a heavily Sn-doped SOG dielectric layer on the β-Ga2O3 channel layer 3, and then designing the source electrode 6 and drain electrode 7 on the heavily doped SOG dielectric layer 4 to realize the source-drain ohmic electrode structure, reduces the ohmic contact on-resistance by 50% compared to the existing method of forming a heavily doped layer through ion implantation to realize the source-drain ohmic electrode structure. This allows gallium oxide power transistors to be further applied in the field of power electronics.

[0078] As the device embodiment of the second aspect is basically similar to the method embodiment of the first aspect, the description is relatively simple, and relevant details can be found in the description of the method embodiment of the first aspect.

[0079] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0080] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0081] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a gallium oxide power transistor with low-ohmic contact, characterized in that, include: A β-Ga2O3 UID layer is grown on a β-Ga2O3 substrate; A lightly doped β-Ga2O3 channel layer is grown on the β-Ga2O3 UID layer; A heavily doped SOG dielectric layer is spin-coated onto the β-Ga2O3 channel layer; The SOG dielectric layer, excluding the ohmic region, is etched away; Source and drain electrodes are grown on the SOG dielectric layer within the ohmic region; An Al2O3 dielectric layer is grown on the β-Ga2O3 channel layer, the source electrode, the drain electrode, and the SOG dielectric layer; A gate electrode is grown on the Al2O3 dielectric layer outside the ohmic region; The Al2O3 dielectric layer on the source electrode and the drain electrode is etched away. Interconnect metal is deposited on the source electrode, the drain electrode, and the gate electrode.

2. The method for fabricating a gallium oxide power transistor with a low-ohmic contact according to claim 1, characterized in that, Growing a β-Ga2O3 UID layer on a β-Ga2O3 substrate includes: On the β-Ga2O3 substrate, a material with a thickness of 100 nm to 500 nm and a carrier concentration of 1 × 10⁻⁶ is grown. 14 cm -3 ~1×10 16 cm -3 The β-Ga2O3 UID layer.

3. The method for fabricating a gallium oxide power transistor with a low-ohmic contact according to claim 1, characterized in that, A lightly doped β-Ga2O3 channel layer is grown on the β-Ga2O3 UID layer, comprising: A Si doping concentration of 1×10⁻⁶ nm with a thickness of 200 nm to 600 nm is grown on the β-Ga₂O₃ UID layer. 17 cm -3 ~5×10 18 cm -3 The β-Ga2O3 channel layer.

4. The method for fabricating a gallium oxide power transistor with a low-ohmic contact according to claim 1, characterized in that, A heavily doped SOG dielectric layer is grown on the β-Ga2O3 channel layer, comprising: A spin-coating with a thickness of 100 nm to 500 nm and a doping concentration of 5 × 10⁻⁶ nm is applied to the β-Ga₂O₃ channel layer. 18 cm -3 ~5×10 19 cm -3 The SOG dielectric layer.

5. The method for fabricating a gallium oxide power transistor with a low-ohmic contact according to claim 1, characterized in that, A Sn doping concentration of 5 × 10⁻⁶ nm is spin-coated onto the β-Ga₂O₃ channel layer with a thickness of 100 nm to 500 nm. 18 cm -3 ~5×10 19 cm -3 The SOG dielectric layer.

6. A gallium oxide power transistor with a low-ohmic contact, characterized in that, include: β-Ga2O3 substrate; A β-Ga2O3 UID layer and a lightly doped β-Ga2O3 channel layer are sequentially disposed on the β-Ga2O3 substrate; A heavily doped SOG dielectric layer is disposed on the β-Ga2O3 channel layer in the ohmic region; The source electrode and drain electrode are respectively disposed on the SOG dielectric layer at both ends of the device; An Al2O3 dielectric layer is disposed on the β-Ga2O3 channel layer outside the ohmic region and on the SOG dielectric layer; The gate electrode is disposed on the Al2O3 dielectric layer.

7. The gallium oxide power transistor with low-ohmic contact according to claim 6, characterized in that, The carrier concentration of the β-Ga2O3UID layer is 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 The thickness ranges from 100nm to 500nm.

8. The gallium oxide power transistor with low-ohmic contact according to claim 6, characterized in that, The β-Ga2O3 channel layer is lightly doped; the thickness of the β-Ga2O3 channel layer is 200 nm to 600 nm, and the doping concentration is 1 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 .

9. The gallium oxide power transistor with low-ohmic contact according to claim 6, characterized in that, The SOG dielectric layer is heavily doped; the thickness of the SOG dielectric layer is 100 nm to 500 nm, and the doping concentration is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 .

10. The gallium oxide power transistor with low-ohmic contact according to claim 6, characterized in that, The SOG dielectric layer is heavily Sn-doped; the thickness of the SOG dielectric layer is 100 nm to 500 nm, and the Sn doping concentration is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 .

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