A space-based high-reliability single-photon avalanche diode timing control circuit

Abstract

A spatial high-reliability single-photon avalanche diode timing control circuit, wherein a current-sense resistor converts an avalanche current signal into a detectable voltage signal, which is then converted into a level signal by a single-photon signal readout circuit, and a single-photon pulse shaping circuit shapes the level signal; a high-side and low-side quenching timing circuit uses the level signal output by the single-photon signal readout circuit as a trigger signal to generate high-side and low-side quenching control signals; a low-side reset timing circuit uses the QCHN signal output by the high-side and low-side quenching timing circuit as a trigger signal to output a low-side reset control signal and a high-side reset timing circuit trigger signal SRN to generate a high-side reset control signal; and a global reset circuit shapes an externally input enable signal to generate a global reset signal RST, which puts the SPAD in a ready state for generating single-photon signals. The present invention can ensure that the SPAD timing is not disordered and improve the working reliability of the SPAD, and is mainly used in spatial high-reliability single-photon avalanche diode timing control occasions.

Description

Technical Field

[0001] The present invention relates to a high-reliability space single-photon avalanche diode timing control circuit, which is mainly used for the timing control of rapid quenching and resetting of single-photon avalanche diodes in space laser radar ranging applications, and belongs to the field of single-photon detection. Background Art

[0002] With the continuous advancement of science and technology, the demand for detector sensitivity in fields such as quantum communications, lidar ranging, 3D imaging, and biomedicine is increasing. Furthermore, as exploration of space targets deepens, applications such as lidar ranging and 3D imaging are rapidly developing in space exploration. Single-photon avalanche diodes (SPADs) are a relatively mature type of single-photon detector currently used on the ground, but their reliability in space applications remains a concern.

[0003] When SPAD is used on the ground, in order to pursue the ultimate dead time to obtain a large saturation count rate and independently adjust the delay time parameters of each submodule, the timing control of SPAD readout, quenching, and reset is usually controlled using a parallel architecture, such as Figure 2 As shown in the figure, the single-photon readout signal is used to simultaneously control the activation of each sequential circuit, and then the timing parameters are adjusted to achieve timing matching. The adjustment of the timing parameters of each sequential circuit does not affect the operation of other sequential circuits. The independent adjustment can achieve a high saturation count rate.

[0004] In space applications, equipment is exposed to a variety of environmental factors, including cosmic rays, solar radiation, and space radiation, including high and low temperature fluctuations, vacuum, and weightlessness. Cosmic rays and the frequent high and low temperature fluctuations are particularly detrimental to electronic components within the device. Cosmic rays primarily include solar cosmic rays, Earth's radiation belts, and galactic cosmic rays. These rays contain large numbers of charged, high-energy particles that bombard electronic equipment, causing them to fail or even be destroyed. For electronic components, these high-energy particles can lead to failure modes such as total dose effects, single event effects, displacement damage effects, and surface charge and discharge effects. For SPAD peripheral circuits, total dose effects and single event effects are the most significant and common. First, the total dose effect is a long-term cumulative process. As the total dose increases, key electronic component parameters, such as threshold voltage and delay time, can undergo unpredictable changes. Changes in these key parameters can disrupt the timing of the SPAD's peripheral circuits, leading to failure and, in severe cases, even short circuiting and damage. Secondly, because the SPAD's timing control circuit often utilizes a large number of flip-flops or latches, single-event effects can cause the voltage levels of these devices to flip or latch, triggering unpredictable states and causing the entire timing control circuit to crash. Thirdly, in a space environment, as the device orbits, the intensity of solar radiation on the device fluctuates over time, causing the device's temperature to fluctuate between high and low temperatures. This temperature change also accelerates device aging, causing the timing-related parameters of electronic components such as buffers and flip-flops to drift, which can also disrupt the SPAD's peripheral timing circuits. For example, when the high-side reset and low-side reset control signals overlap, high voltage is applied directly to the SPAD's cathode, while the anode is directly connected to ground. If a strong signal light appears at this time, a large avalanche current will be generated instantaneously, causing the SPAD to burn out due to transient overcurrent. Furthermore, if the quenching and reset signals overlap, the quenching voltage will short-circuit, causing overcurrent damage to the quenching power supply and circuit failure. Therefore, there is an urgent need to find a highly reliable SPAD timing control method that can solve the circuit failure problem caused by changes in the timing parameters of electronic components. Summary of the Invention

[0005] (1) Technical issues to be resolved

[0006] In order to solve the problem that SPAD faces in space environment applications, such as total dose effect, single particle effect, temperature alternation and other space environment effects, which cause changes in the time parameters of electronic components and lead to failure of the timing control circuit, the present invention provides a space high-reliability single-photon avalanche diode timing control circuit.

[0007] (2) Technical solution

[0008] The present invention provides a spatial high-reliability single-photon avalanche diode timing control circuit, which includes a single-photon signal readout circuit, a single-photon pulse shaping circuit, a global reset circuit, a high- and low-side quenching timing circuit, a low-side reset timing circuit, a high-side reset timing circuit, a high-voltage power supply, a single-photon avalanche diode, and a current-sense resistor Rs;

[0009] The high-side and low-side quenching sequential circuit, the low-side reset sequential circuit, and the high-side reset sequential circuit are connected in a cascade manner, and the output signal of the previous stage circuit is used as the input trigger signal of the next stage circuit;

[0010] The global reset circuit only generates a global reset once when the external enable signal becomes valid, and only resets the high-side and low-side quenching timing circuits of the first-stage timing circuit. The output signal generated by the reset controls the subsequent circuits in sequence to complete the reset of the entire circuit;

[0011] Furthermore, the single-photon signal readout circuit includes an AC coupling capacitor C1, clamping diodes D1 and D2, a comparator U1, and a buffer B1.

[0012] Furthermore, the global reset circuit includes a high-speed switching transistor Q1, a current-limiting resistor R1, a capacitor C2, a D-type flip-flop U2 with a reset function and a rising edge trigger, and buffers B7, B8, B9, B10, and B11.

[0013] Furthermore, the single-photon pulse shaping circuit includes a rising-edge-triggered D flip-flop U3 with a clear-set function, and buffers B2, B12, B13, B14, B15, and B16;

[0014] Furthermore, the high-side and low-side quenching timing circuit includes a rising-edge-triggered D flip-flop U4 with a clear-set function, and buffers B3, B4, B17, and B18.

[0015] Furthermore, the low-side reset timing circuit includes a rising-edge-triggered D flip-flop U5 with a clear-set function, and buffers B5, B19, and B20.

[0016] Furthermore, the high-side reset timing circuit includes a rising-edge-triggered D flip-flop U6 with clearing and setting functions, and buffers B6, B21, and B22.

[0017] Furthermore, in the single-photon signal readout circuit, the first end of the current-sense resistor Rs is connected to the first end of the capacitor C1 via the PHC signal, the second end of the capacitor C1 is connected to the anode of the clamping diode D1, and the cathode of the clamping diode D1 is connected to the +5V power supply; the anode of the clamping diode D2 is connected to the ground; the positive input end of the comparator U1 is connected to the second end of the capacitor C1, and the negative input end of the comparator U1 is connected to the comparison reference voltage VTH , the output end of the comparator U1 is connected to the input end of the buffer B1, the output end of the buffer B1 outputs a single photon pulse signal (PHS), and the external enable signal input end is connected to the enable end of the comparator U1;

[0018] The comparator U1 is a high-speed comparator, and its enable terminal is active at a low level; the buffer B1 is a high-speed buffer.

[0019] Furthermore, in the global reset circuit, the base of the high-speed switching transistor Q1 is connected to the external enable signal input terminal, the emitter is connected to the ground, the collector is connected to the second end of the current-limiting resistor R1, the first end of the current-limiting resistor R1 is connected to the +5V power supply, the first end of the capacitor C2 is connected to the second end of the current-limiting resistor R1, and the second end of the capacitor C2 is connected to the ground; the data input D terminal and the set PREN terminal of the D flip-flop U2 are both connected to the +5V power supply, the clock input CLK terminal of the D flip-flop U2 is connected to the first end of the capacitor C2, the positive output Q+ terminal is not connected to any signal, the negative output Q- terminal is connected to the input terminal of the buffer B7, and the output terminal of the buffer B7 is the global reset signal output (RST); the input terminal of the buffer B8 is connected to the negative output Q- terminal, the input terminal of the buffer B9 is connected to the output terminal of the buffer B8, the input terminal of the buffer B10 is connected to the output terminal of the buffer B9, the input terminal of the buffer B11 is connected to the output terminal of the buffer B10, and the output terminal of the buffer B11 is connected to the clear terminal CLRN of the D flip-flop U2;

[0020] The D flip-flop U2 is a high-speed D flip-flop with clear and set functions and is triggered on a rising edge; the external enable signal connected to the base of the high-speed switching transistor Q1 is valid at a low level; the buffers B7, B8, B9, B10, and B11 are all high-speed buffers, and the number of buffers connected in series between the negative output Q- terminal of the D flip-flop U2 and the clear CLRN terminal of the D flip-flop U2 and the delay time of a single buffer determine the effective width of the reset signal RST.

[0021] Furthermore, in the single-photon pulse shaping circuit, the data input D terminal and the set PREN terminal of the D flip-flop U3 are both connected to a +5V power supply, the clock input CLK terminal of the D flip-flop U3 is connected to the output terminal (PHS) of the buffer B1 of the single-photon readout circuit, the positive output Q+ terminal is connected to the input terminal of the buffer B12, and the output terminal of the buffer B12 is output as a single-photon pulse signal (PH_OUT), the negative output Q- terminal of the D flip-flop U3 is connected to the input terminal of the buffer B13, the input terminal of the buffer B14 is connected to the output terminal of the buffer B13, the input terminal of the buffer B15 is connected to the output terminal of the buffer B14, the input terminal of the buffer B16 is connected to the output terminal of the buffer B15, and the output terminal of the buffer B16 is connected to the clear CLRN terminal of the D flip-flop U3;

[0022] The D flip-flop U3 is a high-speed D flip-flop with clear and set functions and rising edge triggering; the buffers B12, B13, B14, B15, and B16 are all high-speed buffers. The number of buffers connected in series between the negative output Q-terminal of the D flip-flop U3 and the clear CLRN terminal of the D flip-flop U3 and the delay time of a single buffer determine the effective width of the single-photon pulse signal PH_OUT.

[0023] Furthermore, in the high-side and low-side quenching timing circuit, the data input D terminal of the D flip-flop U4 is connected to a +5V power supply, the set input PREN terminal of the D flip-flop U4 is connected to the output terminal of the global reset circuit buffer B7, the clock input CLK terminal of the D flip-flop U4 is connected to the output terminal (PHS) of the buffer B1 of the single-photon readout circuit, the positive output Q+ terminal (QCHP) of the D flip-flop U4 is connected to the input terminal of the buffer B3, the output terminal of the buffer B3 is output as a high-side quenching control signal, the negative output Q- terminal (QCHN) of the D flip-flop U4 is connected to the input terminal of the buffer B4, and the output terminal of the buffer B4 is output as a low-side quenching control signal; the input terminal of the buffer B17 is connected to the negative output Q- terminal of the D flip-flop U4, the input terminal of the buffer B18 is connected to the output terminal of the buffer B17, and the output terminal of the buffer B18 is connected to the clear input CLRN terminal of the D flip-flop U4;

[0024] The D flip-flop U4 is a high-speed D flip-flop with a clear and set function and is triggered by a rising edge; the buffers B3, B4, B17, and B18 are all high-speed buffers. The number of buffers connected in series between the negative output Q- terminal of the D flip-flop U4 and the clear CLRN terminal of the D flip-flop U4 and the delay time of a single buffer determine the effective width of the high and low side quenching control signals.

[0025] Further, in the low-side reset timing circuit, the data input D terminal and the set PREN terminal of the D flip-flop U5 are both connected to a +5V power supply, the clock input CLK terminal of the D flip-flop U5 is connected to the Q- output terminal (QCHN) of the high-low side quenching timing circuit D flip-flop U4, the positive output Q+ terminal (SRP) of the D flip-flop U5 is connected to the input terminal of the buffer B5, the output terminal of the buffer B5 is output as a low-side reset control signal, the negative output Q- terminal (SRN) of the D flip-flop U5 is connected to the input terminal of the buffer B19, the input terminal of the buffer B20 is connected to the output terminal of the buffer B19, and the output terminal of the buffer B20 is connected to the clear CLRN terminal of the D flip-flop U5;

[0026] The D flip-flop U5 is a high-speed D flip-flop with a clear and set function and a rising edge trigger; the buffers B5, B19, and B20 are all high-speed buffers, and the number of buffers connected in series between the negative output Q- terminal of the D flip-flop U5 and the clear CLRN terminal of the D flip-flop U5 and the delay time of a single buffer determine the effective width of the low-side reset control signal;

[0027] Furthermore, the data input D terminal and the set PREN terminal of the D flip-flop U6 are both connected to a +5V power supply, the clock input CLK terminal of the D flip-flop U6 is connected to the Q- output terminal (SRN) of the low-side reset timing circuit D flip-flop U5, the positive output Q+ terminal of the D flip-flop U6 is not connected to any signal, the negative output Q- terminal (SRH) of the D flip-flop U6 is connected to the input terminal of the buffer B6, the output terminal of the buffer B6 outputs a high-side reset control signal, the input terminal of the buffer B21 is connected to the negative output Q- terminal (SRH) of the D flip-flop U6, the input terminal of the buffer B22 is connected to the output terminal of the buffer B21, and the output terminal of the buffer B22 is connected to the clear CLRN terminal of the D flip-flop U6;

[0028] The D flip-flop U6 is a high-speed D flip-flop with clear and set functions and is triggered by a rising edge; the buffers B6, B21, and B22 are all high-speed buffers. The number of buffers connected in series between the negative output Q- terminal of the D flip-flop U6 and the clear CLRN terminal of the D flip-flop U6 and the delay time of a single buffer determine the effective width of the high-side reset control signal.

[0029] (3) Beneficial effects

[0030] The present invention connects the SPAD timing circuits in series, controls them step by step, and adds a global reset circuit, which has the following advantages:

[0031] (1) By connecting the timing circuits in series and controlling them step by step, it is possible to ensure that the SPAD timing control circuit does not become disordered and cause the SPAD timing circuit to fail under the total space radiation dose effect, even if the parameters such as the delay time and voltage threshold of the timing circuit change. This improves the adaptability of the SPAD timing circuit to the total space radiation dose effect.

[0032] (2) Add the enable control terminal and global reset circuit of SPAD, and use the global reset circuit to reset the entire timing circuit when the enable control terminal becomes effective, so as to prevent the timing circuit from locking due to single-particle effect, and increase the ability of SPAD timing circuit to resist single-particle upset. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the timing control circuit of the present invention;

[0034] Figure 2It is a SPAD parallel timing architecture;

[0035] Figure 3 SPAD single photon readout circuit;

[0036] Figure 4 It is the SPAD single photon global reset circuit;

[0037] Figure 5 It is a SPAD single photon pulse shaping circuit;

[0038] Figure 6 It is the SPAD high and low side quenching timing circuit;

[0039] Figure 7 It is the low-side reset circuit of SPAD;

[0040] Figure 8 It is the SPAD high-side reset circuit;

[0041] Figure 9 This is the timing relationship diagram of the SPAD timing circuit. DETAILED DESCRIPTION

[0042] The specific embodiments of the present invention are described below with reference to the accompanying drawings.

[0043] like Figure 1 As shown, the present invention describes a spatial high-reliability single-photon avalanche diode timing control circuit, comprising a single-photon signal readout circuit, a single-photon pulse shaping circuit, a global reset circuit, a high- and low-side quenching timing circuit, a low-side reset timing circuit, a high-side reset timing circuit, a high-voltage power supply, a single-photon avalanche diode, and a current-sense resistor; the high- and low-side quenching timing circuit, the low-side reset timing circuit, and the high-side reset timing circuit in the single-photon avalanche diode timing control circuit are connected in a cascade manner, and the output signal of the previous stage circuit is used as the input trigger signal of the next stage circuit; the global reset circuit in the single-photon avalanche diode timing control circuit only generates a global reset once when the external enable signal starts to be effective, and only resets the high- and low-side quenching timing circuits of the first-stage timing circuit, and the output signal generated by the reset controls the subsequent circuits in sequence to complete the reset of the entire circuit;

[0044] The single-photon signal readout circuit includes an AC coupling capacitor C1, clamping diodes D1 and D2, a comparator U1, and a buffer B1; the global reset circuit includes a high-speed switching transistor Q1, a current-limiting resistor R1, a capacitor C2, a D-type flip-flop U2 with a clearing and setting function and a rising edge trigger, and buffers B7, B8, B9, B10, and B11; the single-photon pulse shaping circuit includes a D-type flip-flop U3 with a clearing and setting function and a rising edge trigger, and buffers B2, B12, B13, B14, B15, and B16; the high- and low-side quenching timing circuit includes a D-type flip-flop U4 with a clearing and setting function and a rising edge trigger, and buffers B3, B4, B17, and B18; the low-side reset timing circuit includes a D-type flip-flop U5 with a clearing and setting function and a rising edge trigger, and buffers B5, B19, and B20; the high-side reset timing circuit includes a D-type flip-flop U6 with a clearing and setting function and a rising edge trigger, and buffers B6, B21, and B22;

[0045] like Figure 3 As shown, in the single photon signal readout circuit, the first end of the current-sense resistor Rs is connected to the first end of the capacitor C1, the second end of C1 is connected to the anode of the diode D1, and the cathode of D1 is connected to the +5V power supply; the anode of D2 is connected to the ground; the positive input end of the comparator U1 is connected to the second end of C1, and the negative input end of the comparator U1 is connected to the comparison reference voltage V TH , the output end of the comparator U1 is connected to the input end of the buffer B1, the output end of the buffer B1 outputs a single photon pulse signal (PHS), and the external enable signal input end is connected to the enable end of the comparator U1; the comparator U1 is a high-speed comparator, and the enable end is valid at a low level; the buffer B1 is a high-speed buffer; wherein, after the photon signal enters the SPAD, it generates an avalanche current under the action of the high-voltage electric field. After the avalanche current passes through the current-sense resistor RS, a signal voltage PHC is formed at the first end of RS. The single-photon signal readout circuit compares the signal voltage PHC with the reference voltage VTH and identifies it as a true single-photon pulse signal. The signal is converted into a single-photon level signal PHS and output to the single-photon pulse shaping circuit. The single-photon level signal PHS is reconstructed and shaped in level width and then output after the buffer enhances the driving capability;

[0046] like Figure 4As shown, in the global reset circuit, the base of the high-speed switching transistor Q1 is connected to the external enable signal input terminal, the emitter of the high-speed switching transistor Q1 is connected to the ground, the collector of the high-speed switching transistor Q1 is connected to the second end of the current limiting resistor R1, the first end of the current limiting resistor R1 is connected to the +5V power supply, the first end of the capacitor C2 is connected to the second end of the current limiting resistor R1, and the second end of the capacitor C2 is connected to the ground; the data input D terminal and the set PREN terminal of the D flip-flop U2 are both connected to the +5V power supply, the clock input CLK terminal of the D flip-flop U2 is connected to the first end of the capacitor C2, the positive output Q+ terminal is not connected to any signal, the negative output Q- terminal is connected to the input terminal of the buffer B7, and the output terminal of the buffer B7 is the global reset signal output (RST); the input terminal of the buffer B8 is connected to the negative output Q- terminal, the input terminal of the buffer B9 is connected to the output terminal of the buffer B8, the input terminal of the buffer B10 is connected to the output terminal of the buffer B9, and the output terminal of the buffer B11 is connected to the negative output Q- terminal. The input end is connected to the output end of the buffer B10, and the output end of the buffer B11 is connected to the clear CLRN end of the D flip-flop U2; the D flip-flop U2 is a high-speed D flip-flop with a clear and set function and is triggered on a rising edge; the external enable signal connected to the base of the high-speed switching transistor Q1 is valid at a low level; the buffers B7, B8, B9, B10, and B11 are all high-speed buffers, and the negative output Q-end of the D flip-flop U2 is connected in series with the clear CLRN end of the D flip-flop U2. The number of buffers in series and the delay time of a single buffer determine the effective width of the reset signal RST; wherein, a low-level valid enable signal forms a global reset pulse signal RST at the falling edge of the enable signal, which resets the high and low-side quenching timing circuits of the SPAD timing control circuit, and the high and low-side quenching timing circuits generate "pseudo single photon signals" to trigger the subsequent timing circuit to work, thereby preventing the single particle event from deadlocking the timing circuit and causing the timing circuit function to fail;

[0047] like Figure 5As shown, the single-photon pulse shaping circuit, the data input D terminal and the set PREN terminal of the D flip-flop U3 are both connected to the +5V power supply, the clock input CLK terminal of the D flip-flop U3 is connected to the output terminal (PHS) of the buffer B1 of the single-photon readout circuit, the positive output Q+ terminal is connected to the input terminal of the buffer B12, the output terminal of the buffer B12 is output as a single-photon pulse signal (PH_OUT), the negative output Q- terminal is connected to the input terminal of the buffer B13, the input terminal of the buffer B14 is connected to the output terminal of the buffer B13, and the input terminal of the buffer B15 is connected to The output end of buffer B14 and the input end of buffer B16 are connected to the output end of buffer B15, and the output end of buffer B16 is connected to the clear CLRN end of D flip-flop U3; D flip-flop U3 is a high-speed D flip-flop with a clear-set function and a rising edge trigger; the buffers B12, B13, B14, B15, and B16 are all high-speed buffers, and the buffer connected in series between the negative output Q-end of D flip-flop U3 and the clear CLRN end of D flip-flop U3. The number of buffers connected in series and the delay time of a single buffer determine the effective width of the single-photon pulse signal PH_OUT;

[0048] like Figure 6 As shown, in the high-side and low-side quenching timing circuit, the data input D terminal of the D flip-flop U4 is connected to the +5V power supply, the set input PREN terminal of the D flip-flop U4 is connected to the output terminal of the global reset circuit buffer B7, the clock input CLK terminal of the D flip-flop U4 is connected to the output terminal (PHS) of the buffer B1 of the single-photon readout circuit, the positive output Q+ terminal (QCHP) of the D flip-flop U4 is connected to the input terminal of the buffer B3, and the output terminal of the buffer B3 is output as the high-side quenching control signal, the negative output Q- terminal (QCHN) of the D flip-flop U4 is connected to the input terminal of the buffer B4, and the output terminal of the buffer B4 is output as the low-side quenching control signal; the input terminal of the buffer B17 is connected to the negative output Q- terminal of the D flip-flop U4, and the buffer B1 The input end of 8 is connected to the output end of the buffer B17, and the output end of the buffer B18 is connected to the clear input CLRN end of the D flip-flop U4; the D flip-flop U4 is a high-speed D flip-flop with a clear-set function and rising edge triggering; the buffers B3, B4, B17, and B18 are all high-speed buffers, and the number of buffers connected in series between the negative output Q-end of the D flip-flop U4 and the clear CLRN end of the D flip-flop U4 and the delay time of a single buffer determine the effective width of the high-side and low-side quenching control signals; wherein, the high-side and low-side quenching timing circuit receives the single-photon pulse PHS signal output by the single-photon signal readout circuit as a trigger signal, and synchronously generates a high-side quenching control signal QCHP and a low-side quenching control signal QCHN of fixed width and outputs them after the buffer driving capability is enhanced;

[0049] like Figure 7As shown, in the low-side reset timing circuit, the data input D terminal and the set PREN terminal of the D flip-flop U5 are both connected to the +5V power supply, the clock input CLK terminal of the D flip-flop U5 is connected to the Q- output terminal (QCHN) of the high-low side quenching timing circuit D flip-flop U4, the positive output Q+ terminal (SRP) of the D flip-flop U5 is connected to the input terminal of the buffer B5, the output terminal of the buffer B5 is output as the low-side reset control signal, the negative output Q- terminal (SRN) of the D flip-flop U5 is connected to the input terminal of the buffer B19, the input terminal of the buffer B20 is connected to the output terminal of the buffer B19, and the output terminal of the buffer B20 is connected to the Clear CLRN terminal; D flip-flop U5 is a high-speed D flip-flop with clear and set functions and rising edge triggering; the buffers B5, B19, and B20 are all high-speed buffers, and the number of buffers connected in series with the negative output Q-terminal of the D flip-flop U5 and the clear CLRN terminal of the D flip-flop U5 and the delay time of a single buffer determine the effective width of the low-side reset control signal; wherein, the low-side quenching control signal QCHN output by the high-side and low-side quenching timing circuit serves as the input trigger signal of the low-side reset timing circuit, triggering the low-side reset timing circuit to synchronously generate a low-side reset control signal SRP with a fixed width and a trigger signal SRN of the high-side reset timing circuit;

[0050] like Figure 8 As shown, in the high-side reset timing circuit, the data input D terminal and the set PREN terminal of the D flip-flop U6 are both connected to the +5V power supply, the clock input CLK terminal of the D flip-flop U6 is connected to the Q- output terminal (SRN) of the low-side reset timing circuit D flip-flop U5, the positive output Q+ terminal of the D flip-flop U6 is not connected to any signal, the negative output Q- terminal (SRH) of the D flip-flop U6 is connected to the input terminal of the buffer B6, the output terminal of the buffer B6 outputs the high-side reset control signal, the input terminal of the buffer B21 is connected to the negative output Q- terminal (SRH) of the D flip-flop U6, the input terminal of the buffer B22 is connected to the output terminal of the buffer B21, and the output terminal of the buffer B22 is connected to the clear terminal of the D flip-flop U6. CLRN terminal; the D flip-flop U6 is a high-speed D flip-flop with clear and set functions and rising edge triggering; the buffers B6, B21, and B22 are all high-speed buffers, and the number of buffers connected in series between the negative output Q-terminal of the D flip-flop U6 and the clear CLRN terminal of the D flip-flop U6 and the delay time of a single buffer determine the effective width of the high-side reset control signal; wherein, the high-side reset timing circuit generates a high-side reset control signal SRH after receiving the trigger signal SRN; so far, all the control signals with fixed timing generated by the single-photon pulse signal or the global reset signal are used to control each circuit in turn to complete the SPAD signal readout, high-side quenching, low-side quenching, low-side reset, high-side reset and other operations.

[0051] The global reset circuit, high- and low-side quenching timing circuit, low-side reset timing circuit, and high-side reset timing circuit are connected in cascade mode. Only the output signal of the previous stage can control the generation of the signal of the next stage. Only after the output of the previous stage circuit is complete can the next stage circuit be triggered. In this way, even if the key time delay parameters or threshold voltage of an electronic component in the timing chain change, resulting in a change in the output signal pulse width, this change will not affect the generation of the correct timing signal by the next stage circuit, thereby not causing the entire timing circuit to work in disorder and causing the SPAD circuit to fail. The timing process of the SPAD timing control signal, such as Figure 9 shown.

[0052] At time t1, when the external SPAD enable signal is active at a low level, the global reset circuit is stimulated to generate a reset signal RST with a pulse width of △t1. At the same time, the single-photon pulse readout circuit is activated, and single-photon detection can begin. The reset signal RST enters the high-side and low-side quenching timing circuit to reset the circuit, generating a high-side quenching control signal QCHP and a low-side quenching control signal QCHN with the same pulse width as the reset signal RST, quenching the high and low sides of the SPAD at the same time. At time t2, the quenching ends; the low-side quenching The control signal QCHN is transmitted to the low-side reset timing circuit, triggering the low-side reset control signal SRP with a pulse width of △t2 and the trigger signal SRN for the next-level high-side reset timing circuit, generating a high-side reset signal SRH with a pulse width of △t3. At this point, the reset generated by the external SPAD enable signal performs a global reset on the entire timing circuit, and performs a full-process operation on both ends of the SPAD: simultaneous quenching of the high and low sides, low-side reset, and high-side reset. At this time, the SPAD is fully ready for the next single-photon pulse conversion and output.

[0053] At time t5, the first single-photon signal is detected. Except that the pulse width of the high-side quenching control signal QCHP and the low-side quenching control signal QCHN becomes Δt4, other control sequences and pulse widths are consistent with the global reset.

[0054] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person familiar with the technology can understand and think of any changes or replacements within the technical scope disclosed by the present invention, which should be included in the scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A spatial high-reliability single-photon avalanche diode timing control circuit, characterized in that: The circuit includes a single-photon signal readout circuit, a single-photon pulse shaping circuit, a global reset circuit, a high-side and low-side quenching timing circuit, a low-side reset timing circuit, a high-side reset timing circuit, a high-voltage power supply, a single-photon avalanche diode, and a current-sense resistor Rs; The high-side and low-side quenching sequential circuit, the low-side reset sequential circuit, and the high-side reset sequential circuit are connected in a cascade manner, and the output signal of the previous stage circuit is used as the input trigger signal of the next stage circuit; The global reset circuit only generates a global reset once when the external enable signal becomes valid, and only resets the high-side and low-side quenching timing circuits of the first-stage timing circuit. The output signal generated by the reset controls the subsequent circuits in sequence to complete the reset of the entire circuit; The global reset circuit includes a high-speed switching transistor Q1, a current-limiting resistor R1, a capacitor C2, a D-type flip-flop U2 with a reset function and a rising edge trigger, and buffers B7, B8, B9, B10, and B11; In the global reset circuit, the base of the high-speed switching transistor Q1 is connected to the external enable signal input terminal, the emitter is connected to the ground, the collector is connected to the second end of the current-limiting resistor R1, the first end of the current-limiting resistor R1 is connected to the +5V power supply, the first end of the capacitor C2 is connected to the second end of the current-limiting resistor R1, and the second end of the capacitor C2 is connected to the ground; the data input D terminal and the set PREN terminal of the D flip-flop U2 are both connected to the +5V power supply, the clock input CLK terminal of the D flip-flop U2 is connected to the first end of the capacitor C2, the positive output Q+ terminal is not connected to any signal, the negative output Q- terminal is connected to the input terminal of the buffer B7, and the output terminal of the buffer B7 is the global reset signal output RST; the input terminal of the buffer B8 is connected to the negative output Q- terminal, the input terminal of the buffer B9 is connected to the output terminal of the buffer B8, the input terminal of the buffer B10 is connected to the output terminal of the buffer B9, the input terminal of the buffer B11 is connected to the output terminal of the buffer B10, and the output terminal of the buffer B11 is connected to the clear terminal CLRN of the D flip-flop U2; The D flip-flop U2 is a high-speed D flip-flop with clear and set functions and is triggered by a rising edge. The external enable signal connected to the base of the high-speed switching transistor Q1 is active low. The buffers B7, B8, B9, B10, and B11 are all high-speed buffers. The number of buffers connected in series between the negative output Q- terminal of the D flip-flop U2 and the clear CLRN terminal of the D flip-flop U2 and the delay time of each buffer determine the effective width of the reset signal RST. The single photon signal readout circuit includes an AC coupling capacitor C1, clamping diodes D1 and D2, a comparator U1, and a buffer B1; In the single-photon signal readout circuit, the first end of the current-sense resistor Rs is connected to the first end of the capacitor C1 via the PHC signal, the second end of the capacitor C1 is connected to the anode of the clamping diode D1, and the cathode of the clamping diode D1 is connected to the +5V power supply; the anode of the clamping diode D2 is connected to the ground; the positive input end of the comparator U1 is connected to the second end of the capacitor C1, and the negative input end of the comparator U1 is connected to the comparison reference voltage V TH , the output end of the comparator U1 is connected to the input end of the buffer B1, the output end of the buffer B1 outputs the single photon pulse signal PHS, and the external enable signal input end is connected to the enable end of the comparator U1; The comparator U1 is a high-speed comparator, and its enable terminal is active at a low level; the buffer B1 is a high-speed buffer.

2. The spatial high-reliability single-photon avalanche diode timing control circuit according to claim 1, characterized in that: The single-photon pulse shaping circuit includes a rising-edge-triggered D-type flip-flop U3 with a reset function, and buffers B2, B12, B13, B14, B15, and B16.

3. The spatial high-reliability single-photon avalanche diode timing control circuit according to claim 1, characterized in that: The high-side and low-side quenching timing circuit includes a rising-edge triggered D flip-flop U4 with a clearing and setting function, and buffers B3, B4, B17, and B18.

4. The spatial high-reliability single-photon avalanche diode timing control circuit according to claim 1, characterized in that: The low-side reset timing circuit includes a rising-edge-triggered D flip-flop U5 with a clearing and setting function, and buffers B5, B19, and B20.

5. The spatial high-reliability single-photon avalanche diode timing control circuit according to claim 1, characterized in that: The high-side reset timing circuit includes a rising-edge-triggered D flip-flop U6 with a clear-set function, and buffers B6, B21, and B22.

6. The spatial high-reliability single-photon avalanche diode timing control circuit according to claim 2, characterized in that: In the single-photon pulse shaping circuit, the data input D terminal and the set PREN terminal of the D flip-flop U3 are both connected to a +5V power supply, the clock input CLK terminal of the D flip-flop U3 is connected to the output terminal of the buffer B1 of the single-photon signal readout circuit, the positive output Q+ terminal is connected to the input terminal of the buffer B12, the output terminal of the buffer B12 is output as the single-photon pulse signal PH_OUT, the negative output Q- terminal of the D flip-flop U3 is connected to the input terminal of the buffer B13, the input terminal of the buffer B14 is connected to the output terminal of the buffer B13, the input terminal of the buffer B15 is connected to the output terminal of the buffer B14, the input terminal of the buffer B16 is connected to the output terminal of the buffer B15, and the output terminal of the buffer B16 is connected to the clear CLRN terminal of the D flip-flop U3; The D flip-flop U3 is a high-speed D flip-flop with clear and set functions and rising edge triggering; the buffers B12, B13, B14, B15, and B16 are all high-speed buffers. The number of buffers connected in series between the negative output Q-terminal of the D flip-flop U3 and the clear CLRN terminal of the D flip-flop U3 and the delay time of a single buffer determine the effective width of the single-photon pulse signal output PH_OUT.

7. The spatial high-reliability single-photon avalanche diode timing control circuit according to claim 3, characterized in that: In the high- and low-side quenching timing circuit, the data input D terminal of the D flip-flop U4 is connected to a +5V power supply, the set input PREN terminal of the D flip-flop U4 is connected to the output terminal of the global reset circuit buffer B7, the clock input CLK terminal of the D flip-flop U4 is connected to the output terminal PHS of the buffer B1 of the single-photon readout circuit, the positive output Q+ terminal QCHP of the D flip-flop U4 is connected to the input terminal of the buffer B3, the output terminal of the buffer B3 is output as a high-side quenching control signal, the negative output Q- terminal QCHN of the D flip-flop U4 is connected to the input terminal of the buffer B4, and the output terminal of the buffer B4 is output as a low-side quenching control signal; the input terminal of the buffer B17 is connected to the negative output Q- terminal of the D flip-flop U4, the input terminal of the buffer B18 is connected to the output terminal of the buffer B17, and the output terminal of the buffer B18 is connected to the clear input CLRN terminal of the D flip-flop U4; The D flip-flop U4 is a high-speed D flip-flop with a clear and set function and is triggered by a rising edge; the buffers B3, B4, B17, and B18 are all high-speed buffers. The number of buffers connected in series between the negative output Q- terminal of the D flip-flop U4 and the clear CLRN terminal of the D flip-flop U4 and the delay time of a single buffer determine the effective width of the high and low side quenching control signals.

8. The spatial high-reliability single-photon avalanche diode timing control circuit according to claim 4, characterized in that: In the low-side reset timing circuit, the data input D terminal and the set PREN terminal of the D flip-flop U5 are both connected to a +5V power supply, the clock input CLK terminal of the D flip-flop U5 is connected to the Q- output terminal QCHN of the high-low side quenching timing circuit D flip-flop U4, the positive output Q+ terminal SRP of the D flip-flop U5 is connected to the input terminal of the buffer B5, the output terminal of the buffer B5 is output as a low-side reset control signal, the negative output Q- terminal SRN of the D flip-flop U5 is connected to the input terminal of the buffer B19, the input terminal of the buffer B20 is connected to the output terminal of the buffer B19, and the output terminal of the buffer B20 is connected to the clear CLRN terminal of the D flip-flop U5; The D flip-flop U5 is a high-speed D flip-flop with clear and set functions and is triggered by a rising edge; the buffers B5, B19, and B20 are all high-speed buffers. The number of buffers connected in series between the negative output Q- terminal of the D flip-flop U5 and the clear CLRN terminal of the D flip-flop U5 and the delay time of a single buffer determine the effective width of the low-side reset control signal.

9. The spatial high-reliability single-photon avalanche diode timing control circuit according to claim 1, characterized in that: The data input D terminal and the set PREN terminal of the D flip-flop U6 are both connected to a +5V power supply, the clock input CLK terminal of the D flip-flop U6 is connected to the Q- output terminal SRN of the low-side reset timing circuit D flip-flop U5, the positive output Q+ terminal of the D flip-flop U6 is not connected to any signal, the negative output Q- terminal SRH of the D flip-flop U6 is connected to the input terminal of the buffer B6, the output terminal of the buffer B6 outputs a high-side reset control signal, the input terminal of the buffer B21 is connected to the negative output Q- terminal SRH of the D flip-flop U6, the input terminal of the buffer B22 is connected to the output terminal of the buffer B21, and the output terminal of the buffer B22 is connected to the clear CLRN terminal of the D flip-flop U6; The D flip-flop U6 is a high-speed D flip-flop with clear and set functions and is triggered by a rising edge; the buffers B6, B21, and B22 are all high-speed buffers. The number of buffers connected in series between the negative output Q- terminal of the D flip-flop U6 and the clear CLRN terminal of the D flip-flop U6 and the delay time of a single buffer determine the effective width of the high-side reset control signal.

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