Resistive random access memory (RRAM) device-based in-memory computing circuit and in-memory data processing method

Abstract

This invention relates to the field of data processing, specifically to a memory-based computing circuit and a memory-based data processing method based on RRAM devices. The memory-based computing circuit includes multiple cascaded memory-based computing units. Each memory-based computing unit includes: an RRAM storage array for performing simulation calculations on multiple simulated voltage signals to obtain simulated current signals; an integrator connected to the RRAM storage array for integrating the simulated current signals and outputting them as voltage signals; and a voltage buffer circuit module connected to the integrator for receiving the voltage signals sent by the integrator and transmitting them to the RRAM storage array of the next-level memory-based computing unit or outputting them to an analog-to-digital converter. By incorporating voltage buffer circuit modules in each level of the memory-based computing unit, this circuit avoids the problem of large quantization errors caused by excessive analog-to-digital conversion during data processing, thereby improving the accuracy of neural network circuits.

Description

Technical Field

[0001] This invention relates to the field of data processing, and specifically to an in-memory computing circuit and an in-memory computing data processing method based on an RRAM device. Background Technology

[0002] In in-memory computing circuits, data transmission between different layers typically occurs via digital signals. After processing the data, each layer needs to convert the resulting analog voltage signal into a digital signal before transmitting it to the next layer. The next layer then converts the digital signal back into an analog signal for further processing. Due to this mechanism, the more layers the circuit has, the more times the signal needs to be converted between layers. Furthermore, the quantization loss during analog-to-digital conversion can reduce computational accuracy, making it difficult for neural network chips to achieve high data processing accuracy. Therefore, it is necessary to provide a new in-memory computing technology. Summary of the Invention

[0003] The purpose of this invention is to provide an in-memory computing circuit and an in-memory computing data processing method based on RRAM devices, thereby overcoming, at least to some extent, the aforementioned problems caused by the limitations and defects of related technologies.

[0004] According to one aspect of the present invention, a memory computing circuit based on an RRAM device is provided, comprising a plurality of cascaded memory computing units, wherein the memory computing unit comprises:

[0005] An RRAM storage array is used to perform simulation calculations on multiple simulated voltage signals to obtain simulated current signals.

[0006] An integrator, connected to the RRAM storage array, is used to integrate the analog current signal and output it as a voltage signal;

[0007] A voltage buffer circuit module, connected to the integrator, is used to receive the voltage signal sent by the integrator and transmit it to the RRAM storage array of the next-level in-memory computing unit or output it to the analog-to-digital converter.

[0008] In an exemplary embodiment, the in-memory computing circuit based on RRAM devices further includes a digital-to-analog converter (DAC) connected to the RRAM storage array of the first-stage in-memory computing unit, which is used to convert digital signals input to the in-memory computing circuit into simulated voltage signals.

[0009] In an exemplary embodiment, the in-memory computing circuit based on an RRAM device further includes a delay circuit module connected between the integrator and the voltage buffer circuit module, which is used to buffer the timing output data of the integrator.

[0010] In one exemplary embodiment, the delay circuit module is composed of an even number of inverters cascaded in sequence.

[0011] In an exemplary embodiment, the in-memory computing circuit based on RRAM devices further includes an analog-to-digital converter (ADC), which, together with a voltage buffer circuit module of the last-stage in-memory computing unit, is used to convert the analog voltage signal output by the voltage buffer circuit module into a digital signal and output it.

[0012] In an exemplary embodiment, the voltage buffer circuit module includes: cascaded inverters 10 and 11, transistors M8 and M5 connected sequentially to the output terminal of inverter 10, and transistors M7 and M6 connected sequentially to the output terminal of inverter 11; wherein, when a low-level signal is input to inverter 10, a low-level signal is output through transistor M8 and a high-level signal is output through transistor M6; when a high-level signal is input to inverter 10, a low-level signal is output through transistor M7 and a high-level signal is output through transistor M5.

[0013] According to another aspect of the present invention, a memory computing data processing method based on an RRAM device is provided, comprising:

[0014] Simulation calculations are performed on multiple simulated voltage signals using an RRAM storage array to obtain simulated current signals;

[0015] The analog current signal is integrated by an integrator connected to the RRAM storage array and output as a voltage signal.

[0016] The voltage signal sent by the integrator is received by the voltage buffer circuit module connected to the integrator and transmitted to the RRAM storage array of the next-level in-memory computing unit or output to the analog-to-digital converter.

[0017] In one exemplary embodiment, before performing simulation calculations on multiple simulated voltage signals via an RRAM storage array, the method further includes: converting digital signals input to the in-memory computing circuit into simulated voltage signals via a digital-to-analog converter.

[0018] In an exemplary embodiment, the in-memory computing data processing method based on RRAM devices further includes: converting the analog voltage signal output by the voltage buffer circuit module into a digital signal and outputting it through an analog-to-digital converter connected to the voltage buffer circuit module of the last-stage in-memory computing unit.

[0019] In an exemplary embodiment, the in-memory computing data processing method based on RRAM devices further includes: performing neural network training on the array circuit based on RRAM devices according to specific data to obtain the RRAM memory array.

[0020] This invention provides a memory computing circuit and a memory computing data processing method based on RAM devices. The circuit, by setting voltage buffer circuit modules in each level of the memory computing unit, can directly transmit the analog voltage signal obtained from the data processing of one level to the next level of the memory computing unit, avoiding the problem of large quantization errors caused by excessive analog-to-digital conversion in data processing, thereby effectively improving the accuracy of the neural network circuit. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a memory computing circuit based on a RAM device in an exemplary embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of a neural network structure according to an exemplary embodiment of the present invention;

[0023] Figure 3 This is a memory computing circuit diagram based on a RAM device in an exemplary embodiment of the present invention;

[0024] Figure 4 This is a circuit diagram of a voltage buffer circuit module according to an exemplary embodiment of the present invention;

[0025] Figure 5 This is a schematic flowchart of an in-memory computing data processing method based on RAM devices, according to an exemplary embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, features, and advantages of the present invention more apparent and understandable, the technical solutions of the embodiments and examples of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. However, the exemplary embodiments and examples can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments and examples are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments and examples to those skilled in the art. The features, structures, or characteristics described in the present invention can be combined in any suitable manner in one or more embodiments and examples. In the following description, numerous specific details are provided to give a full understanding of the embodiments and examples of the present invention. However, those skilled in the art will recognize that the technical solutions of the present invention can be practiced by omitting one or more of the specific details, or other methods, components, apparatus, steps, etc. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present invention.

[0027] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Although the steps of the method in this invention are described in a specific order in the drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. The flowcharts shown in the drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while others may be combined or partially combined; therefore, the actual order of execution may change depending on the circumstances. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0028] Influenced by the von Neumann architecture of computers, computation and storage are typically designed to be separate in data processing. However, with the rise of data-centric, data-intensive technologies in the big data era, data applications are no longer limited to computation and processing, but increasingly emphasize the "transportation" of data—fundamentally eliminating unnecessary data flow. This has spurred the practical application of in-memory computing (IMC) design, achieving maximum data processing efficiency through holistic consideration of storage and computation. IMC embeds computing power into memory, performing two-dimensional and three-dimensional matrix multiplication / addition operations using a new computing architecture. It integrates data storage and computation within the same chip area by utilizing memory for data processing or computation. IMC can completely eliminate the bottlenecks of the von Neumann architecture, making it particularly suitable for large-scale parallel applications such as deep learning neural networks. Resistive Random Access Memory (RRAM) devices, with their high speed, low voltage, high storage density, and ease of integration, are widely used in neural network circuits. Neural network circuits based on RRAM devices can significantly improve computational efficiency and are one of the key technologies for realizing high-performance artificial intelligence chips in the future. Therefore, neural network circuits based on RRAM devices have been widely used in in-memory computing technology. Neural network circuits typically process data through a multi-tiered hierarchical structure. For example, they can be divided into output layers, intermediate layers (hidden layers), and so on, with each layer potentially containing multiple sub-layers. The target data to be processed is first input to the first layer of the neural network circuit, processed, and then input to the next layer, and so on, until the output data is completed. However, since data can only be transmitted between layers in the form of digital signals, each layer needs to convert the obtained analog voltage signal into a digital signal after processing the data and transmit it to the next layer. The next layer then converts the digital signal back into an analog signal for further simulation processing. The more layers a neural network circuit has, the more times the signal is converted between layers, and the computational accuracy is lost due to quantization during analog-to-digital conversion, thus reducing the accuracy of the neural network circuit.

[0029] In view of the above-mentioned problems existing in related technologies, the present invention provides a memory computing circuit based on RAM devices, comprising multiple cascaded memory computing units. Each memory computing unit includes: an RRAM storage array for performing simulation calculations on multiple simulated voltage signals to obtain simulated current signals; an integrator connected to the RRAM storage array for integrating the simulated current signals and outputting them as voltage signals; and a voltage buffer circuit module connected to the integrator for receiving the voltage signals sent by the integrator and transmitting them to the RRAM storage array of the next-level memory computing unit or outputting them to an analog-to-digital converter. By setting voltage buffer circuit modules in each level of the memory computing unit, the circuit can directly transmit the simulated voltage signals obtained from data processing at one level to the next level of the memory computing unit, avoiding the problem of large quantization errors caused by excessive analog-to-digital conversion during data processing, thereby effectively improving the accuracy of the neural network circuit.

[0030] An exemplary embodiment of the present invention provides a memory computing circuit based on a RAM device. Figure 1 This is a schematic diagram of a memory computing circuit based on a RAM device according to an exemplary embodiment of the present invention; as shown below. Figure 1 As shown, the in-memory computing circuit based on RRAM devices includes multiple cascaded in-memory computing units, each of which includes:

[0031] An RRAM storage array is used to perform simulation calculations on multiple simulated voltage signals to obtain simulated current signals.

[0032] An integrator, connected to the RRAM storage array, is used to integrate the analog current signal and output it as a voltage signal;

[0033] A voltage buffer circuit module, connected to the integrator, is used to receive the voltage signal sent by the integrator and transmit it to the RRAM storage array of the next-level in-memory computing unit or output it to the analog-to-digital converter.

[0034] Resistive Random Access Memory (RRAM) devices utilize voltages of varying magnitudes or polarities applied across a resistive random access material (RRAM) to control the material's resistance between high and low resistance states. RRAMs operate in two modes: unipolar and bipolar. Unipolar RRAMs apply a voltage of a single polarity across the device, using different voltage magnitudes to control the resistance transitions between high and low resistance states for data writing and erasure. Bipolar RRAMs use voltages of different polarities to control the resistance transitions. The two stable states exhibited by the RRAM are called the high-resistance state and the low-resistance state. Before the first transition, a relatively large voltage is typically applied to change the device from its initial state to the low-resistance state; this process is called forming. RRAM arrays can be obtained by training a neural network on an array circuit based on RRAM devices. In the RRAM array, the neurons and RRAM weights are physically interleaved, and the connections between neurons and the RRAM array can be configured as inputs or outputs of the neurons, enabling the neural network to perform inference in various data flow directions. This allows for the processing of large amounts of data with a small circuit area and low power consumption.

[0035] In one exemplary embodiment, the in-memory computing circuit further includes a digital-to-analog converter (DAC), which is connected to the RRAM storage array of the first-stage in-memory computing unit. The DAC converts the digital signal input to the in-memory computing circuit into an analog voltage signal suitable for processing and transmits it to the first-stage in-memory computing unit for processing. Further, the in-memory computing circuit also includes an analog-to-digital converter (ADC), which is connected to a voltage buffer circuit module of the last-stage in-memory computing unit. The signal output by the last-stage in-memory computing unit is the analog voltage signal processed by the entire neural network. The ADC converts this analog voltage signal into a digital signal and outputs it to the outside of the circuit. In one exemplary embodiment, the in-memory computing circuit also includes a time delay circuit module, which can be composed of an even number of inverters connected together. Its function is to buffer the data output from the integrator's timing processing and send it to the voltage buffer circuit module when the entire signal processing is complete.

[0036] In one exemplary embodiment, the RRAM neural network structure is as follows: Figure 2 As shown, the neural network includes an input layer (nodes x1-x4), hidden layer 1 (nodes h1-h5), hidden layer 2 (nodes n1-n4), and an output layer (y1-y3), wherein each node of the hidden layer is implemented using the in-memory computing circuit based on the RAM device. For example, the in-memory computing circuit is as follows... Figure 3As shown, the system includes an RRAM memory array, an integrator, a delay circuit module, and a voltage buffer circuit module connected in sequence. The signal output from the voltage buffer circuit module is transmitted to the next stage of the RRAM memory array. The integrator includes an operational amplifier PO, transistors M0, M1, and M3, and a capacitor C0 connected in sequence, as well as a transistor M4 connected to the capacitor and an inverter INV connected to transistor M3. In an exemplary embodiment, the voltage buffer circuit module is as follows: Figure 4 As shown, the voltage buffer circuit module includes inverters 10 and 11, PMOS transistors M5 and M6, NMOS transistors M7 and M8 connected via ports. The IN port is connected to the delay circuit module. VD1, VD, and VS are the level input ports, and OUTP and OUTN can be used as output ports connected to the next-stage RRAM storage array. When the input IN is a low-level signal, the output after inverter (INV) 10 is a high-level signal. NMOS transistors M8 and M6 are turned on, outputting a low-level signal through the OUTP port and a high-level signal through the OUTN port. When the input IN is a high-level signal, the output after inverter (INV) 10 is a low-level signal. NMOS transistors M8 and M6 are not turned on. Then, inverter (INV) 11 outputs a high-level signal to NMOS transistor M7, turning on NMOS transistors M7 and M5. Thus, a high-level signal is output through the OUTP port and a low-level signal is output through the OUTN port.

[0037] Another exemplary embodiment of the present invention provides a memory-based computing data processing method based on RRAM devices. Figure 5 This is a schematic flowchart of an in-memory computing data processing method based on an RRAM device according to an exemplary embodiment of the present invention; the method applies to the in-memory computing circuit based on the RRAM device in the above embodiments, such as... Figure 5 As shown, it includes the following steps:

[0038] Step S51: Perform simulation calculations on multiple simulated voltage signals using an RRAM storage array to obtain simulated current signals;

[0039] Step S53: Integrate the analog current signal through an integrator connected to the RRAM storage array and output it as a voltage signal;

[0040] Step S55: Receive the voltage signal sent by the integrator through the voltage buffer circuit module connected to the integrator, and transmit it to the RRAM storage array of the next-level in-memory computing unit or output it to the analog-to-digital converter.

[0041] In one exemplary embodiment, before performing simulation calculations on multiple simulated voltage signals via an RRAM storage array, the method further includes: converting the digital signals input to the in-memory computing circuit into simulated voltage signals using a digital-to-analog converter. In another exemplary embodiment, the in-memory computing data processing method based on an RRAM device further includes: converting the analog voltage signal output from the voltage buffer circuit module into a digital signal and outputting it using an analog-to-digital converter connected to the voltage buffer circuit module of the last-stage in-memory computing unit. In yet another exemplary embodiment, the in-memory computing data processing method based on an RRAM device further includes: training a neural network on the RRAM-based array circuit according to specific data to obtain the RRAM storage array. Specific details of the above method steps have been described in detail in the sections on each module / unit of the corresponding device, and will not be repeated here. It should be noted that although several modules or units for the device performing the action are mentioned in the above detailed description, this division is not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0042] In addition to the methods and apparatus described above, embodiments of the present invention may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods according to various embodiments of the present invention described in the "Exemplary Methods" section above.

[0043] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of the present invention. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0044] Another embodiment of the present invention provides an electronic device that can be used to perform all or part of the steps of the method described in this exemplary embodiment. The device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the steps of the method according to various embodiments of the present invention described in the "Exemplary Methods" section above.

[0045] Another embodiment of the present invention provides a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods according to various embodiments of the present invention described in the "Exemplary Methods" section of this specification.

[0046] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0047] The basic principles of the present invention have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in the present invention are merely examples and not limitations, and should not be considered as essential features of each embodiment of the present invention. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the present invention to the necessity of employing the aforementioned specific details.

[0048] The block diagrams of devices, apparatuses, devices, and systems involved in this invention are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0049] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0050] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A RRAM device based in-memory computing circuit, characterized in that, It includes multiple cascaded in-memory computing units, each of which includes: An RRAM storage array is used to perform simulation calculations on multiple simulated voltage signals to obtain simulated current signals. An integrator, connected to the RRAM storage array, is used to integrate the analog current signal and output it as a voltage signal; A voltage buffer circuit module, connected to the integrator, is used to receive the voltage signal sent by the integrator and transmit it to the RRAM storage array of the next-level in-memory computing unit or output it to the analog-to-digital converter. The voltage buffer circuit module includes: cascaded inverters 10 and 11, transistors M8 and M5 connected in sequence to the output terminal of inverter 10, and transistors M7 and M6 connected in sequence to the output terminal of inverter 11. The input terminal of inverter 10 is connected to the integrator. When a low-level signal is input to inverter 10, a low-level signal is output through transistor M8 and a high-level signal is output through transistor M6. When a high-level signal is input to inverter 10, a low-level signal is output through transistor M7 and a high-level signal is output through transistor M5.

2. The RRAM device based in-memory computing circuit according to claim 1, wherein, It also includes a digital-to-analog converter, which is connected to the RRAM storage array of the first-stage in-memory computing unit and is used to convert digital signals input to the in-memory computing circuit into simulated voltage signals.

3. The RRAM device based in-memory computing circuit of claim 1, wherein, It also includes a time delay circuit module, which is connected between the integrator and the voltage buffer circuit module, and is used to buffer the timing output data of the integrator.

4. The RRAM device based in-memory computing circuit of claim 3, wherein, The delay circuit module is composed of an even number of inverters cascaded in sequence.

5. The in-memory computing circuit based on RRAM devices according to claim 1, characterized in that, It also includes an analog-to-digital converter, which, together with the voltage buffer circuit module of the last-stage in-memory computing unit, is used to convert the analog voltage signal output by the voltage buffer circuit module into a digital signal and output it.

6. A memory-based computing data processing method based on RRAM devices, characterized in that, include: Simulation calculations are performed on multiple simulated voltage signals using an RRAM storage array to obtain simulated current signals; The analog current signal is integrated by an integrator connected to the RRAM storage array and output as a voltage signal. The voltage signal sent by the integrator is received by the voltage buffer circuit module connected to the integrator and transmitted to the RRAM storage array of the next-level in-memory computing unit or output to the analog-to-digital converter. The voltage buffer circuit module includes: cascaded inverters 10 and 11, transistors M8 and M5 connected sequentially to the output of inverter 10, and transistors M7 and M6 connected sequentially to the output of inverter 11. The input of inverter 10 is connected to the integrator. When a low-level signal is input to inverter 10, a low-level signal is output through transistor M8 and a high-level signal is output through transistor M6. When a high-level signal is input to inverter 10, a low-level signal is output through transistor M7 and a high-level signal is output through transistor M5.

7. The in-memory computing data processing method based on RRAM devices according to claim 6, characterized in that, Before performing simulation calculations on multiple simulated voltage signals using an RRAM storage array, the method further includes converting the digital signals input to the in-memory computing circuit into simulated voltage signals using a digital-to-analog converter.

8. The in-memory computing data processing method based on RRAM devices according to claim 6, characterized in that, Also includes: An analog-to-digital converter connected to the voltage buffer circuit module of the last-stage in-memory computing unit converts the analog voltage signal output by the voltage buffer circuit module into a digital signal and outputs it.

9. The in-memory computing data processing method based on RRAM devices according to claim 6, characterized in that, Also includes: The RRAM storage array is obtained by training a neural network on an array circuit based on specific data.

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