Method for improving interface quality between SiGe channel of MOS transistor and high-k dielectric layer

Abstract

The application relates to the field of semiconductors and discloses a method for improving the interface quality of a SiGe channel and a high-K dielectric layer of a MOS transistor, which comprises the following steps: S1: providing a wafer, wherein the wafer is provided with a first region for manufacturing a Core PMOS, and the top of the first region is provided with a SiGe layer; S2: manufacturing a Si layer with a first thickness on the top of the SiGe layer; and S3: manufacturing a high-K dielectric layer on the Si layer. In actual use, the application can improve the interface quality of the SiGe layer and the high-K dielectric layer, reduce the interface state density, and thus improve the mobility of the device and reduce low-frequency noise by growing a Si layer on the SiGe layer first and then growing a high-K dielectric layer on the Si layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a method for improving the interface quality between SiGe channel and high-K dielectric layer of MOS transistor. BACKGROUND

[0002] For some MOS transistors made by front-gate process, such as PMOS transistor made by FDSOI structure, SiGe is needed to be used to reduce the threshold voltage of PMOS, and the performance of PMOS is improved by using the high mobility of SiGe.

[0003] Currently, in order to reduce gate leakage and avoid tunneling effect, high-K dielectric layer (such as HfO2) is used to replace SiO2 as gate dielectric layer. However, due to the instability of GeOx, if high-K dielectric layer is directly grown on SiGe, it will result in very high interface state density, thereby degrading the mobility and performance of PMOS, such as increasing the low-frequency noise of the device, affecting the analog and radio frequency performance of the device. In order to solve this problem, as shown in Figure 1 , the existing process will first grow a thin oxide layer on SiGe, then perform nitrogenization of the interface layer by NH3 annealing, and finally grow high-K dielectric layer on the thin oxide layer after nitrogenization. Although this solution can inhibit GeOx, the interface state density obtained finally still cannot meet the requirements of device development, and nitrogenization will also affect the mobility. SUMMARY

[0004] In view of the deficiencies in the background art, the present application provides a method for improving the interface quality between SiGe channel and high-K dielectric layer of MOS transistor to solve the deficiencies in the prior art that high-K dielectric layer is grown on SiGe layer.

[0005] To solve the above technical problems, the present application provides the following technical scheme: a method for improving the interface quality between SiGe channel and high-K dielectric layer of MOS transistor, comprising the following steps:

[0006] S1: providing a wafer, wherein the wafer is provided with a first region for making Core PMOS, and the top of the first region is provided with a SiGe layer;

[0007] S2: making a Si layer with a first thickness on the top of the SiGe layer;

[0008] S3: making a high-K dielectric layer on the Si layer.

[0009] In some embodiments, the wafer is further provided with a second region for making Core NMOS / SRAM and a third region for making IO;

[0010] In step S2, first, a Si layer of a first thickness is formed on top of the first region, on top of the second region and on top of the third region;

[0011] Or in step S2, first, an oxide layer of a second thickness is formed on top of the third region, and then a Si layer of a first thickness is formed on top of the first region and on top of the second region;

[0012] Or in step S2, first, a hard mask layer is formed on top of the wafer, then the hard mask layer at the first region is removed, and finally a Si layer of a first thickness is grown on the first region by epitaxy.

[0013] In some embodiments, after step S1 is performed and before step S2 is performed, an isolation trench is formed on top of the wafer.

[0014] In some embodiments, the step of forming the isolation trench is as follows:

[0015] A pad oxide layer, a pad nitride layer, an anti-reflective layer and a photoresist layer are formed on top of the wafer;

[0016] Then, the pattern of the isolation trench is transferred to the anti-reflective layer by an exposure and development process;

[0017] Then, the anti-reflective layer, the pad nitride layer, the pad oxide layer and the wafer are etched in sequence by an etching process to form the isolation trench;

[0018] Then, an oxide layer is formed on the inner wall surface of the isolation trench;

[0019] Then, the isolation trench is filled with oxide;

[0020] Then, the surface of the pad nitride layer is planarized by a CMP process;

[0021] Finally, the pad nitride layer is removed.

[0022] In some embodiments, when a Si layer of a first thickness is formed on top of the first region and on top of the second region after an oxide layer of a second thickness is formed on top of the third region in step S2, the Si layer is deposited on top of the first region and on top of the second region of the wafer by epitaxy after the oxide layer is formed.

[0023] In some embodiments, when a hard mask layer is formed on top of the wafer in step S2, the hard mask layer at the first region is removed, and then a Si layer of a first thickness is grown on the first region by epitaxy, the remaining hard mask layer on the wafer is removed after the Si layer is formed.

[0024] As a further technical solution, the amount of Si layer thickness consumed when the remaining hard mask layer on the wafer is removed is obtained, assuming it is X nm. If the required thickness of the Si layer before depositing the high-k dielectric layer is N nm, then the first thickness is the sum of X and N.

[0025] In one embodiment, the Si layer is fabricated in step S2 using a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process; and the high-k dielectric layer is fabricated in step S3 using a PVD or CVD process.

[0026] The beneficial effects of this invention compared with the prior art are as follows: by first growing a Si layer on the SiGe layer and then growing a high-k dielectric layer on the Si layer, this invention can improve the interface quality between the SiGe layer and the high-k dielectric layer, reduce the interface state density, thereby improving the device mobility and reducing low-frequency noise. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of a high-k dielectric layer grown on a SiGe layer using existing technology;

[0028] Figure 2 The flowchart of the present invention in the embodiments is shown below.

[0029] Figure 3 This is a schematic diagram of the structure in which different devices are grown in different regions on the wafer in the embodiment;

[0030] Figure 4 For the first type in Figure 3 A schematic diagram of the structure after the Si layer has been grown on the wafer.

[0031] Figure 5 For the second type in Figure 3 A schematic diagram of the structure after the Si layer has been grown on the wafer.

[0032] Figure 6 The flowchart of the invention for creating the isolation trench is shown in the embodiment.

[0033] In the figure: 1. Wafer, 2. SiGe layer, 3. Thin oxide layer, 4. High-K dielectric layer, 5. Si layer, 6. Oxide layer, 11. First region, 12. Second region, 13. Third region. Detailed Implementation

[0034] The illustrative embodiments of this application include, but are not limited to, methods for improving the interface quality between the SiGe channel and the high-k dielectric layer of a MOSFET.

[0035] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description of the exemplary embodiments is intended to apply to any embodiment of the application, unless specifically stated otherwise. It is to be understood that other embodiments can be utilized, and structural or procedural changes can be made without departing from the scope of the present application. Therefore, the following detailed description is not meant to limit the application or the protective scope thereof.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. "Includes," "including," "has," "having," "contains," "containing," or other similar words mean encompassed in the listed items and equivalents thereof and does not exclude the addition of further items. "Coupled" or "connected" or similar words does not mean only physically or mechanically connected, but can include electrically connected, whether directly or indirectly.

[0037] As shown in the figure, the method for improving the interface quality between the SiGe channel of the MOS transistor and the high-K dielectric layer includes the following steps: Figure 2

[0038] S1: providing a wafer 1, the wafer is provided with a first area for making a Core PMOS, and the top of the first area 1 is provided with a SiGe layer;

[0039] S2: making a Si layer with a first thickness on the top of the SiGe layer;

[0040] S3: making a high-K dielectric layer on the Si layer.

[0041] In actual use, the present application can improve the interface quality between the SiGe layer and the high-K dielectric layer, reduce the interface state density, and thus improve the mobility of the device and reduce the low-frequency noise, by making a Si layer with a first thickness on the SiGe layer first and then making a high-K dielectric layer. In addition, the method of the present application is not limited to the manufacture of a certain MOS device or the gate of a certain MOS transistor, and can be flexibly applied to the manufacture of various existing MOS devices.

[0042] In actual use, the Si layer is made by a physical vapor deposition process or a chemical vapor deposition process in step S2, and the high-K dielectric layer is made by a physical vapor deposition process or a chemical vapor deposition process in step S3. ​

[0043] In addition, as the integration of integrated circuits is increasingly high, more and more devices are integrated on the same wafer. For example, different parts of the wafer are used to manufacture Core PMOS, Core NMOS / SRAM or IO. The area of the wafer used to manufacture Core NMOS / SRAM is taken as the second area, the area of the wafer used to manufacture Core PMOS is taken as the first area, and the area of the wafer used to manufacture IO is taken as the third area. For the areas of the wafer used to manufacture different devices, the interlayer structure at the top of the wafer is also different. For example, as shown in FIG. 1, the top of the first area of the wafer is SiGe, and the top of the second area and the third area of the wafer is Si. Figure 3

[0044] Since the second area of the wafer used to manufacture Core NMOS / SRAM and the third area of the wafer used to manufacture IO are also provided, and different devices are manufactured in different areas of the wafer, in step S2, the Si layer of the first thickness can be first manufactured on the top of the first area, the top of the second area and the top of the third area at the same time. The structure of the wafer after the Si layer is manufactured in the first area, the second area and the third area is shown in FIG. 2. Figure 4 After the Si layer is grown on the whole wafer, the oxide layer needs to be grown on the third area in the subsequent process, which will cause the loss of the grown Si layer. If the Si loss is too much, the performance of the finally generated device will be affected. In order to avoid too much Si loss, the Si layer can also be grown on the SiGe layer in the following manner: in step S2, the oxide layer of the second thickness is first manufactured on the top of the third area, and then the Si layer of the first thickness is manufactured on the top of the first area and the top of the second area. The structure of the wafer after the oxide layer and the Si layer are manufactured in this manner is shown in FIG. 3. Figure 5 In addition, in step S2, the Si layer can also be manufactured on the first area of the wafer in the following manner: in step S2, the hard mask layer is first manufactured on the top of the wafer, then the hard mask layer at the first area is removed, and finally the Si layer of the first thickness is grown on the first area by epitaxy process.

[0045] In some embodiments, the Si layer can be deposited on the top of the whole upper surface of the wafer.

[0046] Specifically, when the oxide layer of the second thickness is first manufactured on the top of the third area, and then the Si layer of the first thickness is manufactured on the top of the first area and the top of the second area in step S2, after the oxide layer is manufactured, the Si layer is deposited on the top of the first area and the top of the second area of the wafer by epitaxy process.

[0047] ​Specifically, in step S2, a hard mask layer is first formed on the top of the wafer, then the hard mask layer at the first region is removed, and finally the remaining hard mask layer on the wafer is removed after growing the Si layer with the first thickness at the first region through an epitaxial process.

[0048] In actual use, in order to ensure that the thickness of the finally prepared Si layer meets the requirements, the consumption of the thickness of the Si layer when the remaining hard mask layer on the wafer is removed is obtained, which is assumed to be X nm, and if the thickness of the Si layer before the high-K dielectric layer is deposited is required to be N nm, then the first thickness is the sum of X and N.

[0049] When the wafer is used to manufacture a device, an isolation trench is formed on the wafer to ensure the insulation between devices. When the present application is actually implemented, if the Si layer is formed on the wafer before the isolation trench is formed, the prepared Si layer will also be lost when the isolation trench is formed. In order to ensure that the thickness of the finally prepared Si layer meets the requirements, the thickness of the Si layer is increased when the Si layer is prepared, and the increase of the thickness of the Si layer will lead to the lengthening of the production cycle of the device. Therefore, in the present embodiment, after step S1 is performed and before step S2 is performed, an isolation trench is formed on the top of the wafer.

[0050] Specifically, as shown in Figure 6 In the present embodiment, the step of forming the isolation trench is as follows:

[0051] A pad oxide layer, a pad nitride layer, an anti-reflection layer and a photoresist layer are formed on the top of the wafer;

[0052] Then the pattern of the isolation trench is transferred to the anti-reflection layer through an exposure and development process;

[0053] Then the anti-reflection layer, the pad nitride layer, the pad oxide layer and the wafer are etched in sequence through an etching process to form the isolation trench;

[0054] Then an oxide layer is formed on the inner wall surface of the isolation trench;

[0055] Then the isolation trench is filled with oxide;

[0056] Then the surface of the pad nitride layer is planarized through a CMP process;

[0057] Finally, the pad nitride layer is removed.

[0058] In conclusion, the application can improve the interface quality of SiGe layer and high-K dielectric layer, reduce the interface state density, and thus improve the mobility of the device and reduce the low-frequency noise. In addition, when different devices are grown in different regions on the wafer, the application can reduce the Si loss by growing the oxide layer in the third region first and then growing the Si layer in the first and second regions. Similarly, the application can also reduce the Si loss by growing the isolation trench on the wafer first and then growing the Si layer, thereby avoiding the increase of the device production cycle.

[0059] Based on the above disclosure, relevant personnel can make various changes and modifications without deviating from the technical concept of the application. The technical scope of the application is not limited to the content of the specification, and must be determined by the scope of the claims.

Claims

1. A method for improving the interface quality between the SiGe channel and the high-k dielectric layer of a MOSFET, characterized in that, Includes the following steps: S1: A wafer is provided, the wafer having a first region for fabricating Core PMOS, and a SiGe layer is provided on top of the first region; S2: A Si layer of first thickness is formed on top of the SiGe layer; S3: Fabricate a high-k dielectric layer on the Si layer; The wafer also has a second region for fabricating Core NMOS / SRAM and a third region for fabricating I / O; In step S2, a hard mask layer is first fabricated on the top of the wafer, then the hard mask layer in the first region is removed, and then a Si layer of the first thickness is grown in the first region through an epitaxial process. Finally, the remaining hard mask layers on the wafer are removed. The amount of Si layer thickness consumed when the remaining hard mask layer on the wafer is removed is obtained, assuming it is X nm. If the required thickness of the Si layer before depositing the high-k dielectric layer is N nm, then the first thickness is the sum of X and N. After performing step S1 and before performing step S2, an isolation trench is formed on the top of the wafer. The steps for forming the isolation trench are as follows: A pad oxide layer, a pad nitride layer, an anti-reflection layer, and a photoresist layer are fabricated on the top of the wafer; The pattern of the isolation trenches is then transferred onto the anti-reflective layer through exposure and development processes; Then, the anti-reflective layer, pad nitride layer, pad oxide layer and wafer are etched sequentially through an etching process to form an isolation trench; Next, an oxide layer is formed on the inner wall surface of the isolation trench; Then, the isolation trench is filled with oxide; Next, the surface of the pad nitride layer is planarized using a CMP process; Finally, the nitrided pad layer is removed.

2. The method for improving the interface quality between the SiGe channel and the high-k dielectric layer of a MOS transistor according to claim 1, characterized in that, In step S2, the Si layer is fabricated using physical vapor deposition or chemical vapor deposition; in step S3, the high-k dielectric layer is fabricated using physical vapor deposition or chemical vapor deposition.

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