A method of information transmission and a computing device

Abstract

Embodiments of the present application disclose an information transmission method and a computing device, which are used to manage multiple VRs by a BMC chip through a complex programmable logic device (CPLD) and reduce the adaptation workload. The present application is applied to a computing device, which can include a BMC chip, a CPLD and multiple VRs. The BMC chip is connected to the CPLD, and the CPLD is connected to the multiple VRs. When the CPLD receives information sent by the BMC chip, the destination address of the information is a first BMC defined address of a first VR, and the first VR is one of the multiple VRs. Then, the CPLD can determine a first CPLD defined address corresponding to the first BMC defined address, and send the information to the first VR based on the first CPLD defined address. Therefore, the first VR and the first BMC defined address need to be adapted only once on the BMC chip, and if the address of the first VR needs to be modified subsequently, the modification can be made in the CPLD, thereby reducing the adaptation workload and shortening the development cycle.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computers, and in particular to an information transmission method and a computing device. BACKGROUND

[0002] With the rapid development of the computing industry, the demand for servers is also increasing. In order to ensure the stable supply of servers, the implementation of multiple compatible schemes needs to be considered at the beginning of the design of the server, and in particular, the compatibility of different voltage regulator (VR) combination schemes is an important measure of the compatibility of the motherboard in the server.

[0003] Currently, the management of multiple VRs in the server is mainly achieved by directly connecting multiple VRs through a baseboard management controller (BMC) chip on the motherboard (for example, the management content can include online upgrade of the VR, temperature and voltage acquisition, etc.), wherein the address of the VR is set through peripheral hardware, and is achieved by setting the pull-down resistance of the peripheral hardware. Therefore, when replacing a component (such as a motherboard, network card or backplane) in the server, it is necessary to replace the combination scheme of a group of VRs corresponding to the component, and a large number of resistance values need to be modified on the peripheral hardware, and VR address adaptation also needs to be performed on the BMC chip, which is a huge workload and increases the development cycle. SUMMARY

[0004] Embodiments of the present application provide an information transmission method and a computing device, which are used to implement management of multiple VRs by a BMC chip through a complex programmable logic device (CPLD), thereby reducing the adaptation workload.

[0005] The first aspect of the present application provides an information transmission method for a computing device, the computing device comprising a baseboard management controller (BMC) chip, a complex programmable logic device (CPLD) and multiple VRs, wherein the BMC chip is connected to the CPLD, and the CPLD is connected to the multiple VRs; the method comprises: the CPLD receiving information sent by the BMC chip, the destination address of the information being a first BMC defined address of a first VR, and the first VR being one of the multiple VRs; the CPLD determining a first CPLD defined address corresponding to the first BMC defined address; and the CPLD sending the information to the first VR based on the first CPLD defined address.

[0006] In the present application, since the CPLD is programmable, after the first VR and the corresponding first BMC defined address are adapted in the BMC chip, the correspondence between the first BMC defined address and the first CPLD defined address can be written in the CPLD. When the address of the first VR needs to be changed, only the CPLD defined address corresponding to the first BMC defined address needs to be changed in the CPLD, without the need to change the first VR and the corresponding first BMC defined address in the BMC chip, that is, the first VR and the first BMC defined address only need to be adapted once on the BMC chip, reducing the adaptation workload and shortening the development cycle.

[0007] In some possible implementation manners, the CPLD stores a second mapping table, the second mapping table including a mapping of the first BMC defined address to the first CPLD defined address, and the CPLD determining the first CPLD defined address corresponding to the first BMC defined address includes: the CPLD determining the first CPLD defined address corresponding to the first BMC defined address according to the second mapping table.

[0008] In some possible implementation manners, before the CPLD determines the first CPLD defined address corresponding to the first BMC defined address, the method further includes: the CPLD obtaining a first address allocation scheme, the first address allocation scheme including a mapping of the first VR to the first CPLD defined address, so that the CPLD can set an address of the first VR based on the first address allocation scheme, and the CPLD can send the information to the first VR based on the first CPLD defined address.

[0009] In some possible implementation manners, the computing device includes a memory for storing a first version number, and the memory is connected to the CPLD, so that the CPLD can obtain the first version number from the memory and determine the first address allocation scheme corresponding to the first version number from a plurality of address allocation schemes.

[0010] In some possible implementation manners, before the CPLD determines the first address allocation scheme corresponding to the first version number, the method further includes: the CPLD obtaining a plurality of address allocation schemes and corresponding version numbers, to obtain a first mapping table, so that the CPLD can determine the first address allocation scheme corresponding to the first version number based on the first mapping table.

[0011] In some possible implementation manners, before the CPLD determines the first CPLD-defined address corresponding to the first BMC-defined address, the method further includes: determining, by the CPLD, the first BMC-defined address corresponding to the first VR; and determining, by the CPLD, a second mapping table based on the first BMC-defined address and the first address allocation scheme, the second mapping table including a mapping of the first BMC-defined address to the first CPLD-defined address. Then the CPLD can determine the first CPLD-defined address corresponding to the first BMC-defined address according to the second mapping table.

[0012] In some possible implementation manners, after the CPLD sends the information to the first VR based on the first CPLD-defined address, the method further includes: receiving, by the CPLD, the related data sent by the first VR; and sending, by the CPLD, the related data to the BMC chip. Thus, the CPLD obtains the required related data.

[0013] In some possible implementation manners, the information includes upgrade data, and the upgrade data is used to instruct the first VR to upgrade firmware based on the upgrade data, the firmware being used to obtain related data, so that the first VR can upgrade the firmware.

[0014] In some possible implementation manners, the related data includes one or more of a current, a voltage and / or a temperature, so that the CPLD can evaluate the health of components set by the first VR based on the related data.

[0015] The second aspect of the present application provides a computing device, including: a baseboard management controller (BMC) chip, a complex programmable logic device (CPLD) and a plurality of voltage regulators (VRs), wherein the BMC chip is connected to the CPLD, and the CPLD is connected to the plurality of VRs; the BMC chip is configured to send information to the CPLD, the information having a destination address of a first BMC-defined address of a first VR, the first VR being one of the plurality of VRs; and the CPLD is configured to determine a first CPLD-defined address corresponding to the first BMC-defined address, and send the information to the first VR based on the first CPLD-defined address.

[0016] In the present application, since the CPLD is programmable, after the first VR and the corresponding first BMC defined address are adapted in the BMC chip, the correspondence between the first BMC defined address and the first CPLD defined address can be written in the CPLD. When the address of the first VR needs to be changed, only the CPLD defined address corresponding to the first BMC defined address needs to be changed in the CPLD, without the need to change the first VR and the corresponding first BMC defined address in the BMC chip, that is, the first VR and the first BMC defined address only need to be adapted once on the BMC chip, reducing the adaptation workload and shortening the development cycle.

[0017] In some possible implementation manners, the CPLD stores a second mapping table, and the second mapping table includes a mapping of the first BMC defined address to the first CPLD defined address; and the CPLD is further configured to determine the first CPLD defined address corresponding to the first BMC defined address according to the second mapping table.

[0018] In some possible implementation manners, the computing device further includes a mainboard, a backboard and a network card; wherein the BMC chip and the CPLD are both arranged on the mainboard, the network card and the backboard are both electrically connected to the mainboard, and at least one of the plurality of VRs is arranged on the mainboard, the backboard and the network card respectively.

[0019] In some possible implementation manners, the CPLD is further configured to obtain a first address allocation scheme, the first address allocation scheme includes a mapping of the first VR to the first CPLD defined address, and the first VR is set with an address based on the first address allocation scheme.

[0020] In some possible implementation manners, the computing device further includes a memory connected to the CPLD; the memory is configured to store a first version number; the CPLD is further configured to obtain the first version number from the memory; and the CPLD is further configured to determine the first address allocation scheme corresponding to the first version number, the first address allocation scheme being one of the plurality of address allocation schemes.

[0021] In some possible implementation manners, the CPLD is further configured to obtain a plurality of address allocation schemes and version numbers corresponding to the plurality of address allocation schemes, obtain a first mapping table, and determine the first address allocation scheme corresponding to the first version number based on the first mapping table.

[0022] In some possible implementation manners, the information is used to request corresponding related data from the first VR, and the first VR is configured to send the related data to the CPLD based on the information, and the CPLD is further configured to send the related data to the BMC chip.

[0023] The third aspect of the present application provides a computer readable storage medium, which stores instructions, and when the instructions are executed on a computer, the computer executes the method in any one of the first aspect.

[0024] The fourth aspect of the present application provides a computer program product, which includes computer execution instructions stored in a computer readable storage medium; at least one processor of a device can read the computer execution instructions from the computer readable storage medium, and the at least one processor executes the computer execution instructions to make the device implement the method provided in the first aspect or any possible implementation manner of the first aspect.

[0025] The fifth aspect of the present application provides a communication device, which can include at least one processor, a memory and a communication interface. The at least one processor is coupled with the memory and the communication interface. The memory is configured to store instructions, the at least one processor is configured to execute the instructions, and the communication interface is configured to communicate with other communication devices under the control of the at least one processor. The instructions, when executed by the at least one processor, cause the at least one processor to execute the method in the first aspect or any possible implementation manner of the first aspect.

[0026] The sixth aspect of the present application provides a chip system, which includes a processor configured to support the functions involved in the first aspect or any possible implementation manner of the first aspect.

[0027] In a possible design, the chip system can further include a memory configured to store necessary program instructions and data. The chip system can be composed of a chip, or can include the chip and other discrete devices.

[0028] The technical effects brought by the second to sixth aspects or any possible implementation manner thereof can be referred to the technical effects brought by the first aspect or different possible implementation manners of the first aspect, which will not be described herein. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 FIG. 1 is a structural schematic diagram of a computing device;

[0030] Figure 2 FIG. 1 is a structural schematic diagram of a computing device;

[0031] Figure 3 A flowchart of an information transmission method provided by an embodiment of the present application is shown in FIG. 1.

[0032] Figure 4 A structural diagram of a computing device provided by an embodiment of the present application is shown in FIG. 2.

[0033] Figure 5 A structural diagram of a communication device provided by an embodiment of the present application is shown in FIG. 3. DETAILED DESCRIPTION

[0034] An address setting method for multiple VRs is provided by an embodiment of the present application, which is used to realize decoupling of a BMC chip and multiple VRs, improve fault tolerance, and reduce adaptation workload.

[0035] Embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0036] The terms "first", "second", and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, and this is only a way of distinguishing the objects with the same attributes used in the description of the embodiments of the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, so that the processes, methods, systems, products or devices containing a series of units do not have to be limited to those units, but can include other units not clearly listed or inherent to these processes, methods, products or devices.

[0037] Referring to Figure 1 A structural diagram of a computing device is shown in FIG. 2, which can include a BMC chip 110 and multiple VRs 120.

[0038] The BMC chip 110 is a kind of single board controller, which is usually used to manage various hardware constituting a server, thereby managing the server. For example, in the embodiments of the present application, the BMC chip 110 can be used to manage the multiple VRs 120 in the VR control system 100.

[0039] The computing device 100 can include a mainboard, a backboard, a network card, and the like, and each component can be provided with one or more VRs 120. The VR 120 can be provided in the components in the computing device 100 for health monitoring and voltage regulation of the components. Among them, the worker can obtain the firmware for monitoring the corresponding components in the VR 120 through programming, which can be used to obtain the voltage, current, temperature and the like related data in the components, and then the related data can be stored in the register. Then, the BMC chip can obtain the related data by accessing the register of the VR 120, thereby realizing the monitoring of the health status of the components in the computing device 100.

[0040] It should be noted that the mainboard is also called mainboard, system board or motherboard, which is one of the most basic and important components of a computer. The mainboard is generally a rectangular circuit board on which the main circuit system of the computer is installed, and generally has a basic input output system (BIOS) chip, an input output (I / O) control chip, a keyboard and a panel control switch interface, an indicator light connector, an expansion slot, a mainboard and a card DC power supply connector and the like. The backboard is used to support other circuit boards, components and the interconnection between components, and provides a circuit board or frame for the supported components. The network card is a computer hardware designed to allow the computer to communicate on a computer network. The network card has a unique media access control (MAC) address, which allows other devices to be connected to the computing device 100 through a cable or wirelessly.

[0041] With the rapid development of the computing industry, the demand for servers is also increasing. In order to ensure the stable supply of servers, the server needs to consider the implementation of multiple compatible schemes at the beginning of design, especially the compatibility of different VR combination schemes, which is an important measure of the compatibility of the mainboard in the server.

[0042] Currently, the management of multiple VRs in the server is mainly achieved by directly connecting multiple VRs through the BMC chip on the mainboard (for example, the management content can include online upgrade of the VR, temperature and voltage acquisition, etc.), wherein the address of the VR is set through the peripheral hardware, and the address is set through the pull-down resistance of the peripheral hardware. Then, when replacing the components (such as the mainboard, network card or backboard) in the server, it is necessary to replace the combination scheme of a group of VRs corresponding to the component, and a large number of resistance values need to be modified on the peripheral hardware, and VR address adaptation also needs to be performed on the BMC chip, which is a huge workload and has a high error rate, increasing the development cycle.

[0043] To sum up, in the technical solution, when the replacement compatible solution is implemented, the staff needs to develop new code for the BMC chip to adapt to different power combination solutions, which increases the development cycle. Moreover, the values of multiple resistors need to be changed to modify the address of the VR. Since the number of VRs is large, the modification points are multiplied, and the error rate is increased. In addition, since the BMC chip is directly connected to all VRs through an inter-integrated circuit (IIC) interface, it brings challenges to the layout of the printed circuit board (PCB) and is not conducive to the signal integrality (SI) on the transmission path.

[0044] Therefore, the present application provides an information transmission method and a computing device, which are used to manage multiple VRs by a complex programmable logic device (CPLD) to reduce the adaptation workload.

[0045] In the present application, the computing device can include a BMC chip, a CPLD, and multiple VRs. The BMC chip is connected to the CPLD, and the CPLD is connected to the multiple VRs. When the CPLD receives information sent by the BMC chip, the destination address of the information is a first BMC defined address of a first VR, and the first VR is one of the multiple VRs. Then, the CPLD can determine a first CPLD defined address corresponding to the first BMC defined address and send the information to the first VR based on the first CPLD defined address.

[0046] In the present application, since the CPLD is programmable, after the first VR and the corresponding first BMC defined address are adapted in the BMC chip, the correspondence between the first BMC defined address and the first CPLD defined address can be written in the CPLD. When the address of the first VR needs to be changed, only the CPLD defined address corresponding to the first BMC defined address needs to be changed in the CPLD, without the need to change the first VR and the corresponding first BMC defined address in the BMC chip. That is, the first VR and the first BMC defined address need to be adapted only once on the BMC chip, which reduces the adaptation workload and shortens the development cycle.

[0047] In some possible implementation manners, the computing device can be a server or a terminal device.

[0048] The server can have a large difference due to configuration or performance, and can include at least one central processing unit (CPU) (for example, at least one processor) and a memory, at least one storage medium (for example, at least one mass storage device) storing an application program or data. The memory and the storage medium can be temporary storage or persistent storage. The program stored in the storage medium can include at least one module, and each module can include a series of instruction operations in the server. Further, the central processing unit can be configured to communicate with the storage medium and execute the series of instruction operations in the storage medium on the server. The server can also include at least one power supply, at least one wired or wireless network interface, at least one input / output interface, and / or at least one operating system, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, NetWare, etc. In some possible implementations, the server can also be a cloud server, which is not limited herein.

[0049] The server can be a functional module deployed in the server, or a server, or a server cluster composed of several servers, or a cloud computing service center, and the embodiments of the present application do not limit the server. The server, also known as a server, is a device that provides computing services. Since the server needs to respond to service requests and process them, it should generally have the ability to bear and guarantee services, and the server should have strong processing capability, high stability, high reliability, high security, scalability and manageability. In the embodiments of the present application, the server can be an x86 server, which is also called a complex instruction set computer (CISC) architecture server, that is, a personal computer (PC) server commonly used. It is a server based on PC architecture, using an Intel or other compatible x86 instruction set processor chip and a Windows operating system.

[0050] A terminal device, which can also be referred to as user equipment (UE), a mobile station (MS), a mobile terminal (MT), a terminal, etc., is a device that provides voice and / or data connectivity to a user, or a chip disposed in the device, such as a handheld device having wireless connection capability, a vehicle-mounted device, etc. Currently, some examples of the terminal device are: a mobile phone, a desktop computer, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a 5G-residential gateway (5G-RG) supporting 5G access, etc.

[0051] In the embodiments of the present application, the computing device is exemplarily described by taking a server as an example.

[0052] Referring to Figure 2 A schematic diagram of a constituent structure of a computing device 200 is provided for the embodiments of the present application. The computing device 200 can include a BMC chip 210, a CPLD 220, and a plurality of components (exemplarily, the plurality of components are component 1, component 2, and component 3). Each component in the plurality of components can be a mainboard, a backboard, or a network card, etc. One or more VRs 230 are disposed on each component (for example, one or more VRs 230-1 and 230-2 are disposed on the component 1, one or more VRs 230-3 and 230-4 are disposed on the component 2, and one or more VRs 230-5 and 230-6 are disposed on the component 3, and the CPLD 220 is connected to the VRs 230-1 to 230-6, respectively). The BMC chip 110 is connected to the CPLD 220, and the CPLD 220 is connected to the plurality of VRs 230. In some possible implementation manners, the BMC chip 110 and the CPLD 220 can be disposed in the mainboard.

[0053] It should be noted that the BMC can be called differently in different scenarios. For example, in some scenarios, the BMC chip 210 can also be called integrated lights-out (iLO), and in another scenario, it can also be called integrated dell remote access controller (iDRAC). Therefore, whether it is iLO or iDRAC, it can be understood as the BMC chip 210 in the embodiments of the present application.

[0054] It should be noted that the CPLD 220 is a digital integrated circuit that users can construct logic functions according to their own needs. The basic design method is to use the integrated development software platform, use schematic diagrams, hardware description languages, etc. to generate the corresponding target file, store the code through the download cable, and realize the designed digital system. In the embodiments of the present application, the BMC chip 210 can be connected to the CPLD 220 through the IIC interface, and the CPLD 220 can be connected to each VR 230 through the IIC interface.

[0055] In some possible implementations, the CPLD 220 can also be connected to a memory 240, which is used to store the version numbers corresponding to the mainboard, backboard, network card and the like. The CPLD can match the corresponding address allocation scheme according to the version numbers corresponding to the mainboard, backboard and network card. For example, the CPLD can match the address allocation scheme of the plurality of VRs arranged on the mainboard according to the version number corresponding to the mainboard, and can match the address allocation scheme of the VR on the backboard according to the version number corresponding to the backboard. In some possible implementations, the memory can be a bill of material identity document (BOM ID) module. In some possible implementations, the CPLD 220 can be connected to the memory 240 through the IIC interface. In some possible implementations, the memory 240 can be a memristor.

[0056] In some possible implementations, the CPLD 220 can obtain a plurality of address allocation schemes and version numbers corresponding to each address allocation scheme. For example, the staff can write a plurality of address allocation schemes and version numbers corresponding to each address allocation scheme in the CPLD 220 through programming, or the CPLD 220 can obtain a plurality of address allocation schemes and version numbers corresponding to each address allocation scheme from a third-party device, which is not limited here. The memory 240 can store the version number corresponding to the current address allocation scheme. The CPLD 220 obtains the version number from the memory 240, determines the corresponding address allocation scheme based on the version number, and sets the addresses of the plurality of VRs 230 based on the address allocation scheme.

[0057] Therefore, this application proposes an information transmission method and computing device to enable the BMC chip 210 to manage multiple VR 230s through the CPLD 220, thereby reducing the workload of adaptation.

[0058] In this application, since the CPLD 220 is programmable, after adapting the first VR and its corresponding first BMC definition address in multiple VRs 230 in the BMC chip 210, the correspondence between the first BMC definition address and the first CPLD definition address can be written into the CPLD 220. When the address of the first VR needs to be changed, only the CPLD definition address corresponding to the first BMC definition address needs to be changed in the CPLD 220, without changing the first VR and its corresponding first BMC definition address in the BMC chip 210. That is, the first VR and the first BMC definition address only need to be adapted once on the BMC chip 210, reducing the adaptation workload and shortening the development cycle.

[0059] The foregoing embodiments described the computing device 200 provided in this application. Next, we will describe the information transmission method performed based on the computing device 200.

[0060] Please see Figure 3 As shown, the information transmission method provided in this application embodiment mainly includes the following steps:

[0061] 301. The CPLD obtains multiple address allocation schemes and their corresponding version numbers to obtain the first mapping table.

[0062] It should be noted that the address allocation scheme is used to indicate the CPLD defined addresses of multiple VRs within a component. For example, if a network card has VR1 and VR2, the corresponding address allocation scheme can include the CPLD defined addresses for VR1 and VR2; if a backplane has VR3 and VR4, the corresponding address allocation scheme can include the CPLD defined addresses for VR3 and VR4. It should also be noted that VRs are used to monitor relevant data on the component they are installed on, such as voltage, temperature, and current. After acquiring this relevant data, the VR can store the data in the register corresponding to the VR's CPLD address.

[0063] In some feasible implementations, an address allocation scheme can correspond to a version number. For example, address allocation scheme 1 corresponds to version number 001, and address allocation scheme 2 corresponds to version number 002. In some possible implementations, the operator can store the first version number corresponding to the first address allocation scheme to be used in memory.

[0064] In some possible implementations, the plurality of address allocation schemes and the corresponding version numbers thereof can be determined by the staff or by a third party, which is not limited herein. In some possible implementations, the staff can program the plurality of address allocation schemes and the corresponding version numbers thereof into the CPLD, which is not limited herein.

[0065] In some possible implementations, the plurality of address allocation schemes and the corresponding version numbers thereof can constitute a first mapping table, which is exemplarily shown in Table 1 as follows:

[0066] Table 1

[0067] Version number Address allocation scheme 001 Address allocation scheme 1 002 Address allocation scheme 2 003 Address allocation scheme 3

[0068] 302. The CPLD determines, based on the first mapping table, a first address allocation scheme corresponding to the first version number in the memory.

[0069] In some possible implementations, the first address allocation scheme can include a mapping of the first VRs to the first CPLD-defined addresses, and the first address allocation scheme is one of the plurality of address allocation schemes. For example, as shown in Table 1 (the first mapping table), the current first version number in the memory is 001, and the corresponding address allocation scheme 1.

[0070] In some possible implementations, when the staff needs to replace a component and change the address allocation scheme of the plurality of VRs provided in the component, the version number in the memory needs to be changed to a first version number, and the first version number corresponds to a first address allocation scheme, which is the address allocation scheme of the plurality of VRs provided in the replaced component. Then, the CPLD can determine from the memory that the current version number is the first version number, and determine, based on the first mapping table, the first address allocation scheme corresponding to the first version number. For example, the current version number in the memory is 001, and after replacing the component, the staff changes the version number from 001 to 002 in the memory. Then, the CPLD determines 002 from the BOM ID module, and determines, based on the first mapping table, the address allocation scheme 2.

[0071] In some possible implementations, the memory can store the version numbers corresponding to each of the plurality of components, and the CPLD can obtain the version numbers from the memory and determine the address allocation scheme corresponding to each of the plurality of components based on the version numbers. Exemplarily, in the memory, the version number corresponding to the network card is 001, and the version number corresponding to the backboard is 002. Then, the CPLD determines the address allocation scheme 1 corresponding thereto based on 001, and determines the address allocation scheme 2 corresponding thereto based on 002, and the address allocation scheme 1 is used for address equipment of the network card, and the address allocation scheme 2 is used for address equipment of the backboard.

[0072] 303、CPLD sets address of the first VR based on the first address allocation scheme.

[0073] In some possible implementation, the CPLD sets the address of a register of a VR, i.e. the CPLD defines the address. The register is used to store relevant data, which can be one or more of current, voltage and / or temperature of the component where the VR is located.

[0074] For example, the first address allocation scheme includes the address of VR1 and VR2 in component 1, VR1 corresponds to address 12, and VR2 corresponds to address 22, as shown in Table 2:

[0075] Table 2

[0076] VR CPLD-defined address VR1 Address 12 VR2 Address 22

[0077] 304、CPLD determines the first BMC defined address corresponding to the first VR.

[0078] In some possible implementation, the worker can pre-configure the correspondence between the plurality of VRs and the plurality of BMC defined addresses in the BMC chip, for example, by means of a pull-down resistor, or by other means, which is not limited here. In some possible implementation, the worker can pre-program the CPLD to write the correspondence between the VRs in each component and the BMC defined addresses into the CPLD.

[0079] For example, as shown in Table 3, the correspondence between the VRs in component 1 and the BMC defined addresses is as follows:

[0080] Table 3

[0081] VR BMC-defined address VR1 Address 11 VR2 Address 21

[0082] Then, if the first VR is VR of component 1, the CPLD can determine the first BMC defined address corresponding to the first VR based on Table 3.

[0083] Therefore, the staff only needs to adapt the VRs and the corresponding BMC definition addresses in one component in the BMC chip once, and when the component is replaced subsequently (for example, from component 1 to component 2), the staff only needs to modify the version number corresponding to the component in the memory (for example, from version number 1 corresponding to component 1 to version number 2 corresponding to component 2), and the CPLD determines a new address allocation scheme (for example, version number 1 corresponds to address allocation scheme 1, and version number 2 corresponds to address allocation scheme 2) based on the new version number (version number 2), and sets the address for the new component (component 2) based on the new address allocation scheme (address allocation scheme 2), without the need to adapt the VRs and the corresponding BMC definition addresses in the BMC chip again, thereby reducing the adaptation workload and shortening the development cycle.

[0084] 305、The CPLD determines a second mapping table based on the first BMC definition address and the first address allocation scheme, and the second mapping table includes a mapping of the first BMC definition address to the first CPLD definition address.

[0085] For example, the second mapping table can be as shown in Table 4-1:

[0086] Table 4-1

[0087] BMC-defined address CPLD-defined address Address 11 Address 12 Address 21 Address 22

[0088] For example, the first BMC definition address of the first VR is 11, and the first CPLD definition address thereof is address 12.

[0089] It should be noted that when the staff replaces the component, the staff only needs to change the old version number in the memory to the version number corresponding to the new component, so as to change the second mapping table, for example, change Table 4-1 to the second mapping table as shown in Table 4-2:

[0090] Table 4-2

[0091] BMC-defined address CPLD-defined address Address 11' Address 12 Address 21' Address 22

[0092] For example, the BMC definition address of the first VR is 11', and the CPLD definition address thereof is address 12.

[0093] 306、The BMC chip sends information to the CPLD, and the destination address of the information is the first BMC definition address of the first VR, and the first VR is one of the plurality of VRs.

[0094] For example, when the CPLD receives the information sent by the BMC chip, the information is directed to the first BMC definition address of the first VR, and the CPLD can determine the first CPLD definition address of the first VR based on the first BMC definition address and the second mapping table, and forward the information to the first VR based on the first CPLD definition address.

[0095] It should be noted that since the BMC chip does not perceive the change of the address allocation scheme, i.e., does not perceive the change of the first BMC defined address of the first VR, when the BMC chip sends information to the first VR, the information is still sent based on the first BMC defined address of the first VR. For example, as shown in Table 3, if the first VR is VR1 and the first BMC defined address is address 11.

[0096] In some possible implementation manners, the information can be request information for requesting to acquire relevant data of components set by the first VR, such as current, voltage, and / or temperature. The relevant data is stored in a set register, and the BMC defined address can be an originally set address of the register, or can be an arbitrary address, which does not have to be an actually used address of the first VR, but can be an arbitrary address corresponding to the first VR, which is not limited here.

[0097] 307. The CPLD determines a first CPLD defined address corresponding to the first BMC defined address according to a second mapping table.

[0098] For example, as shown in the second mapping table shown in Table 4-1, if the first BMC defined address is address 11, then the CPLD defined address is address 12; or, as shown in the second mapping table shown in Table 4-2, if the first BMC defined address is address 11', then the CPLD defined address is address 12.

[0099] 308. The CPLD sends information to the first VR based on the first CPLD defined address.

[0100] For example, if the first CPLD defined address is address 12, the CPLD sends information to the first VR based on address 12; if the first CPLD defined address is address 22, the CPLD sends information to the first VR based on address 22; and if the first CPLD defined address is address 32, the CPLD sends information to the first VR based on address 32.

[0101] In some possible implementation manners, the information can be information for upgrading the first VR. It should be noted that the first VR has a firmware, which is a program, and can implement functions such as acquiring current, voltage, and temperature, generating alarm information, and storing relevant data in a register corresponding to the first CPLD defined address. For example, the information is used to overcome some defects in the firmware; or, by improving the algorithm, the firmware can reduce the amount of calculation when running.

[0102] In some possible implementation manners, the information can also be information for requesting the first VR to acquire relevant data of set components.

[0103] In the embodiments of the present application, if the information is used to request the related data, steps 310-311 are performed; if the information is used to indicate upgrading the first VR, step 309 is performed.

[0104] 309. The first VR upgrades based on the information.

[0105] In some possible implementation manners, the information can include upgrading data, which is used to indicate to the first VR that the firmware is upgraded based on the upgrading data, and the firmware is used to obtain the related data.

[0106] In some possible implementation manners, when the first VR receives the information, the information can be information for upgrading the firmware of the first VR, and then the first VR can write the information in the register corresponding to the CPLD definition address indicated in the information. Then, the first VR can upgrade the firmware based on the information.

[0107] 310. The first VR sends the related data to the CPLD.

[0108] In some possible implementation manners, when the first VR receives the information, if the information is used to request the related data, the first VR can feed back the requested related data to the CPLD.

[0109] 311. The CPLD sends the related data to the BMC chip.

[0110] When the CPLD receives the related data sent by the first VR, the CPLD can feed back the related data to the BMC chip, and then the BMC chip can monitor the health status of the component set by the first VR based on the related data. For example, the BMC chip can determine that the component set by the first VR is abnormal based on the related data. For example, the temperature in the related data is 99℃, and it is determined that the component is overheated. The BMC chip can feed back the related alarm information.

[0111] In the present application, since the CPLD is programmable, after the first VR and the corresponding first BMC definition address are adapted in the BMC chip, the correspondence between the first BMC definition address and the first CPLD definition address can be written in the CPLD. When the address of the first VR needs to be changed, only the CPLD definition address corresponding to the first BMC definition address in the CPLD needs to be changed, and the first VR and the corresponding first BMC definition address in the BMC chip do not need to be changed. That is, the first VR and the first BMC definition address need to be adapted only once in the BMC chip, which reduces the adaptation workload and shortens the development cycle.

[0112] It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all expressed as a combination of a series of actions, but those skilled in the art should know that the present application is not limited to the order of the actions described, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily necessary for the present application.

[0113] In order to better implement the above scheme of the embodiments of the present application, the related device for implementing the above scheme is also provided below.

[0114] Please refer to Figure 4 The computing device 400 provided by the embodiments of the present application can include:

[0115] The BMC chip 410, the CPLD 420 and the plurality of VRs 430, wherein the BMC chip 410 is connected to the CPLD 420, and the CPLD 420 is connected to the plurality of VRs 430;

[0116] The BMC chip 410 is configured to send information to the CPLD 420, wherein the destination address of the information is a first BMC defined address of a first VR, and the first VR is one of the plurality of VRs.

[0117] The CPLD 420 is configured to determine a first CPLD defined address corresponding to the first BMC defined address.

[0118] The CPLD 420 is further configured to send the information to the first VR based on the first CPLD defined address.

[0119] In some possible implementation manners, the CPLD 420 is further configured to obtain a first address allocation scheme, wherein the first address allocation scheme includes a mapping of the first VR to the first CPLD defined address, and the first VR is set with an address based on the first address allocation scheme.

[0120] In some possible implementation manners, the computing device 400 further includes a memory 440 connected to the CPLD 420.

[0121] The memory 440 is configured to store a first version number.

[0122] The CPLD 420 is further configured to obtain the first version number from the memory 440.

[0123] The CPLD 420 is further configured to determine the first address allocation scheme corresponding to the first version number, the first address allocation scheme being one of the plurality of address allocation schemes.

[0124] In some possible implementation manners, the CPLD 420 is further configured to obtain a plurality of address allocation schemes and version numbers corresponding to the plurality of address allocation schemes, to obtain a first mapping table, and to determine the first address allocation scheme corresponding to the first version number based on the first mapping table.

[0125] In some possible implementation manners, the CPLD 420 is further configured to determine the first BMC-defined address corresponding to the first VR, to determine a second mapping table based on the first BMC-defined address and the first address allocation scheme, the second mapping table including a mapping from the first BMC-defined address to the first CPLD-defined address, and to determine the first CPLD-defined address corresponding to the first BMC-defined address according to the second mapping table.

[0126] In some possible implementation manners, the first VR 430 is configured to send the relevant data to the CPLD 420 based on the information, and the CPLD 420 is further configured to send the relevant data to the BMC chip 410.

[0127] In some possible implementation manners, the information includes upgrade data, and the first VR 430 is further configured to upgrade the firmware based on the upgrade data, the firmware being configured to obtain relevant data.

[0128] It should be noted that the information interaction and execution process between the modules / units of the apparatus are based on the same consideration as the method embodiments of the present application, and the technical effects brought by the same are the same as those of the method embodiments of the present application. For details, refer to the foregoing description of the method embodiments of the present application, which will not be repeated here.

[0129] The present application also provides a computer storage medium, which stores a program. The program performs some or all of the steps recorded in the foregoing method embodiments.

[0130] Next, another communication apparatus provided by the present application is introduced. Referring to FIG. 5, Figure 5 The communication apparatus 500 includes a receiver 501, a transmitter 502, a processor 503 and a memory 504.

[0131] The receiver 501, the transmitter 502, the processor 503 and the memory 504 can be connected by a bus or other means, wherein, Figure 5 In the foregoing description, the connection by the bus is taken as an example.

[0132] The memory 504 can include read-only memory and random access memory, and provide instructions and data to the processor 503. A portion of the memory 504 can also include non-volatile random access memory (NVRAM). The memory 504 stores operating systems and operation instructions, executable modules or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions can include various operation instructions for implementing various operations. The operating system can include various system programs for implementing various basic services and processing hardware-based tasks.

[0133] The processor 503 controls the operation of the communication device 500, and the processor 503 can also be referred to as a central processing unit (CPU). In specific applications, various components of the communication device 500 are coupled together through a bus system, which can include a data bus, a power bus, a control bus, and a state signal bus, etc. However, for the sake of clarity, all the buses are referred to as a bus system in the figure.

[0134] The method disclosed in the embodiments of the present application can be applied in the processor 503 or implemented by the processor 503. The processor 503 can be an integrated circuit chip with a signal processing capability. In the implementation process, each step of the above method can be completed by an integrated logic circuit or an instruction in the form of software in the processor 503. The processor 503 mentioned above can be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Each method, step and logic block diagram disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, or other mature storage media in the art. The storage medium is located in the memory 504, and the processor 503 reads the information in the memory 504 and combines the hardware to complete the steps of the above method.

[0135] The receiver 501 can be configured to receive inputted digital or character information, and generate signal input related to relevant settings and function control. The transmitter 502 can include a display device such as a display screen, and can be configured to output digital or character information through an external interface.

[0136] In an embodiment of the present application, the processor 503 is configured to perform the information transmission method described above.

[0137] In another possible design, when the computing device 400 or the communication apparatus 500 is a chip, the chip includes a processing unit, for example, a processor, and a communication unit, for example, an input / output interface, a pin, or a circuit, etc. The processing unit can execute computer-executed instructions stored in a storage unit, so as to enable the chip in the terminal to perform the wireless reporting information sending method in any one of the first aspect. Optionally, the storage unit is a storage unit in the chip, for example, a register, a cache, etc. The storage unit can also be a storage unit outside the chip in the terminal, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0138] Any processor mentioned above can be a general central processing unit, a microprocessor, an ASIC, or one or more integrated circuits used to control execution of programs for the above method.

[0139] It should be noted that the apparatus embodiments described above are merely illustrative, and the units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the connection relationship between the modules in the apparatus embodiment provided by the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines.

[0140] Those skilled in the art can clearly understand that the application can be implemented by means of software plus necessary universal hardware, and of course can also be implemented by means of dedicated hardware including special integrated circuit, special CPU, special memory, special component, etc. Generally, any function completed by computer program can be easily implemented by corresponding hardware, and the specific hardware structure for implementing the same function can also be various, such as analog circuit, digital circuit or special circuit, etc. However, for the application, the software program implementation is a better embodiment. Based on such understanding, the technical solution of the application or the part of the application which makes contribution to the prior art can be embodied in the form of software product, which is stored in a readable storage medium, such as floppy disk, U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., and includes a plurality of instructions for making a computer device (which can be personal computer, server or network device, etc.) execute the method described in various embodiments of the application.

[0141] In the above embodiments, the implementation can be achieved by software, hardware, firmware or any combination thereof, entirely or partially. When implemented by software, the implementation can be in the form of computer program product entirely or partially.

[0142] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the flow or function described in the embodiments of the application is entirely or partially generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be stored by the computer or a data storage device such as server, data center, etc. integrated with one or more available media. The available medium can be magnetic medium (such as floppy disk, hard disk, magnetic tape), optical medium (such as DVD) or semiconductor medium (such as solid state disk (SSD)) etc.

Claims

1. An information transmission method, characterized in that, A computing device, the computing device including a baseboard management controller (BMC) chip, a complex programmable logic device (CPLD) and multiple voltage regulators (VRs), wherein the BMC chip is connected to the CPLD, and the CPLD is connected to the multiple VRs; The method includes: The CPLD receives information sent by the BMC chip, the destination address of which is the first BMC defined address of the first VR, and the first VR is one of the plurality of VRs; The CPLD determines the first CPLD definition address corresponding to the first BMC definition address; The CPLD sends the information to the first VR based on the address defined by the first CPLD. The CPLD stores a second mapping table, which includes a mapping from the first BMC defined address to the first CPLD defined address. The CPLD determines the first CPLD defined address corresponding to the first BMC defined address by: The CPLD determines the first CPLD definition address corresponding to the first BMC definition address according to the second mapping table; The method further includes: The CPLD obtains a first address allocation scheme, which includes a mapping from the first VR to the address defined by the first CPLD; The CPLD sets the address of the first VR based on the first address allocation scheme.

2. The method according to claim 1, characterized in that, The computing device includes a memory for storing a first version number, and the memory is connected to the CPLD. The CPLD acquisition first address allocation scheme includes: The CPLD retrieves the first version number from the memory; The CPLD determines the first address allocation scheme corresponding to the first version number, and the first address allocation scheme is one of multiple address allocation schemes.

3. The method according to claim 2, characterized in that, The method further includes: The CPLD obtains multiple address allocation schemes and their corresponding version numbers to obtain the first mapping table; The CPLD determines the first address allocation scheme corresponding to the first version number, including: The CPLD determines the first address allocation scheme corresponding to the first version number based on the first mapping table.

4. The method according to claim 3, characterized in that, The method further includes: The CPLD determines the first BMC definition address corresponding to the first VR; The CPLD determines a second mapping table based on the first BMC defined address and the first address allocation scheme. The second mapping table includes a mapping from the first BMC defined address to the first CPLD defined address.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: The CPLD receives the relevant data sent by the first VR. The CPLD sends the relevant data to the BMC chip.

6. A computing device, characterized in that, include: The system includes a baseboard management controller (BMC) chip, a complex programmable logic device (CPLD), and multiple voltage regulators (VRs), wherein the BMC chip is connected to the CPLD, and the CPLD is connected to the multiple VRs. The BMC chip is used to send information to the CPLD, wherein the destination address of the information is the first BMC definition address of the first VR, and the first VR is one of the plurality of VRs; The CPLD is used to determine the first CPLD definition address corresponding to the first BMC definition address; The CPLD is also used to send the information to the first VR based on the address defined by the first CPLD; The CPLD stores a second mapping table, which includes a mapping from the first BMC defined address to the first CPLD defined address; The CPLD is further configured to determine the first CPLD definition address corresponding to the first BMC definition address based on the second mapping table; The CPLD obtains a first address allocation scheme, which includes a mapping from the first VR to the address defined by the first CPLD; The CPLD sets the address of the first VR based on the first address allocation scheme.

7. The computing device according to claim 6, characterized in that, The computing device further includes a motherboard, a backplane, and a network card; wherein the BMC chip and the CPLD are both located on the motherboard, the network card and the backplane are both electrically connected to the motherboard, and at least one of the plurality of VRs is respectively provided on the motherboard, the backplane and the network card.

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