Method, device, medium and equipment for determining virtual machine vCPU usage

Abstract

The present disclosure relates to a method, device, medium and equipment for determining the usage rate of a virtual machine vCPU, the method comprising: collecting register values ​​of multiple target registers corresponding to the virtual machine vCPU for multiple times within a target time period; determining the processing state corresponding to the virtual machine vCPU according to the register values, wherein the processing state includes user state, kernel state and idle state; based on the target processing state required for the target usage rate corresponding to the virtual machine vCPU, determining the target usage rate of the virtual machine vCPU according to the number of times the virtual machine vCPU corresponds to the target processing state within the target time period. Thus, it can be ensured that the processing state determined by the host machine is consistent with the actual state of the virtual machine, and while improving the accuracy of the virtual machine vCPU usage rate, the calculation process of the virtual machine vCPU usage rate is simplified, providing effective data support for real-time monitoring and scheduling of virtual machines.

Description

Technical Field

[0001] The present disclosure relates to the field of virtual machines, and in particular, to a method, device, medium and equipment for determining a virtual machine vCPU usage rate. Background Art

[0002] In cloud computing and virtualization scenarios, if you want to monitor the vCPU (Virtualised CPU) usage of a virtual machine on a host machine, you usually calculate it by collecting the CPU information of the Hypervisor process that starts the virtual machine. However, due to the idle state setting standard of the virtual machine vCPU, the state perceived inside the virtual machine may be inconsistent with that perceived on the host machine. In this case, the vCPU usage calculated by the above method is not accurate. Summary of the invention

[0003] This summary is provided to introduce concepts in a brief form that will be described in detail in the detailed description below. This summary is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0004] In a first aspect, the present disclosure provides a method for determining a virtual machine vCPU usage rate, the method comprising:

[0005] Collect register values ​​of multiple target registers corresponding to the virtual machine vCPU multiple times within a target time period;

[0006] Determine, according to the register value, a processing state corresponding to the virtual machine vCPU, wherein the processing state includes a user state, a kernel state, and an idle state;

[0007] Based on the target processing state required for the target usage rate corresponding to the virtual machine vCPU, the target usage rate of the virtual machine vCPU is determined according to the number of times the virtual machine vCPU corresponds to the target processing state within the target time period.

[0008] In a second aspect, the present disclosure provides a device for determining a virtual machine vCPU usage rate, the device comprising:

[0009] A collection module, used for collecting register values ​​of multiple target registers corresponding to the virtual machine vCPU multiple times within a target period;

[0010] A first determination module is used to determine a processing state corresponding to the virtual machine vCPU according to the register value, wherein the processing state includes a user state, a kernel state and an idle state;

[0011] The second determination module is used to determine the target usage rate of the virtual machine vCPU based on the target processing state required by the target usage rate corresponding to the virtual machine vCPU and according to the number of times the virtual machine vCPU is in the target processing state within the target time period.

[0012] In a third aspect, the present disclosure provides a computer-readable medium having a computer program stored thereon, which, when executed by a processing device, implements the steps of the method described in the first aspect.

[0013] In a fourth aspect, the present disclosure provides an electronic device, including:

[0014] a storage device having a computer program stored thereon;

[0015] A processing device is used to execute the computer program in the storage device to implement the steps of the method described in the first aspect.

[0016] Therefore, through the above technical solution, by collecting the register values ​​of multiple target registers corresponding to the virtual machine vCPU for multiple times, the processing state corresponding to the virtual machine vCPU is determined based on the register value, so that the processing state determined on the host machine can be guaranteed to be consistent with the actual state of the virtual machine, avoiding the error caused by the state identification based on the CPU information of the hypervisor process of the virtual machine, so that the perception of the processing state of the vCPU in the host machine and the virtual machine is consistent, thereby ensuring the accuracy of the utilization rate of the virtual machine vCPU determined on the host machine, while improving the accuracy of the utilization rate of the virtual machine vCPU, simplifying the calculation process of the utilization rate of the virtual machine vCPU, providing effective data support for real-time monitoring and scheduling of virtual machines, so as to be applicable to virtual machine state monitoring in cloud computing scenarios. In addition, the real and effective utilization rate of the virtual machine vCPU is collected on the host machine, which provides a reference for monitoring the operation of the virtual machine and troubleshooting virtual machine problems.

[0017] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale. In the drawings:

[0019] Figure 1 is a flowchart of a method for determining a virtual machine vCPU usage rate provided according to an embodiment of the present disclosure;

[0020] Figure 2aThis is a schematic diagram of address conversion under 5-level paging;

[0021] Figure 2b-2d This is a schematic diagram of address translation under 4-level paging;

[0022] Figure 3 is a block diagram of a device for determining a virtual machine vCPU usage rate provided according to an embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of the structure of an electronic device suitable for implementing the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0024] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0025] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0026] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0027] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0028] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0029] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0030] It is understandable that before using the technical solutions disclosed in the embodiments of the present disclosure, the types, scope of use, usage scenarios, etc. of the personal information involved in the present disclosure should be informed to the user and the user's authorization should be obtained in an appropriate manner in accordance with relevant laws and regulations.

[0031] For example, in response to receiving an active request from a user, a prompt message is sent to the user to clearly prompt the user that the operation requested to be performed will require obtaining and using the user's personal information. Thus, the user can autonomously choose whether to provide personal information to software or hardware such as an electronic device, application, server, or storage medium that performs the operation of the technical solution of the present disclosure according to the prompt message.

[0032] As an optional but non-limiting implementation, in response to receiving an active request from the user, the prompt information may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form. In addition, the pop-up window may also carry a selection control for the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0033] It is understandable that the above notification and the process of obtaining user authorization are merely illustrative and do not constitute a limitation on the implementation of the present disclosure. Other methods that meet the relevant laws and regulations may also be applied to the implementation of the present disclosure.

[0034] At the same time, it is understandable that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and relevant provisions.

[0035] Figure 1 FIG. 1 is a flow chart of a method for determining a virtual machine vCPU usage rate according to an embodiment of the present disclosure. Figure 1 As shown, the method includes:

[0036] In step 11, register values ​​of multiple target registers corresponding to the virtual machine vCPU are collected multiple times within a target time period.

[0037] Among them, the target time period can be set based on the user's usage requirements and actual application scenarios, and the present disclosure does not limit this. Similarly, the sampling interval within the target time period can also be set according to actual needs. The function of the register is to store binary code, which is composed of a combination of triggers with storage functions. In the process of the virtual machine performing corresponding operations, it is necessary to process based on the register. Therefore, in the present disclosure, the information of the target register corresponding to the virtual machine vCPU can be obtained for analysis to determine the state of the virtual machine vCPU.

[0038] In step 12, the processing state corresponding to the virtual machine vCPU is determined according to the register value, wherein the processing state includes user state, kernel state and idle state.

[0039] In the related art, in a cloud computing scenario, it is usually difficult to directly enter the client virtual machine to determine the status of the virtual machine's vCPU. In the host machine, the running status of the virtual machine is usually perceived based on the CPU information of the virtual machine's Hypervisor process. However, the applicant has found that the virtual machine may be in an idle state but has not exited the client guest mode. At this time, the virtual machine is in an idle state, but when the host machine monitors it, it will be considered that the virtual machine is always running, resulting in errors in the host machine's monitoring of the virtual machine.

[0040] Based on this, the register information in the present disclosure is associated with the instructions executed by the vCPU, and its processing status can be determined by analyzing the register value, that is, the host machine can directly analyze the register value corresponding to the virtual machine operation, thereby avoiding the host machine directly identifying the processing status of the virtual machine based on the CPU information of the Hypervisor process of the virtual machine.

[0041] In step 13, based on the target processing state required by the target usage rate corresponding to the virtual machine vCPU, the target usage rate of the virtual machine vCPU is determined according to the number of times the virtual machine vCPU is in the target processing state within the target time period.

[0042] In the actual scenario, information is collected evenly within the target period. The more times the processing state corresponds, the greater the proportion of the processing state in the target period, that is, the higher the usage rate corresponding to the processing state, so the usage rate of the virtual machine vCPU can be calculated based on the number of times. Among them, the target usage rate can be one or more, and the processing states required to calculate different target usage rates may be different. Therefore, the processing states corresponding to the calculation of different target usage rates can be pre-set, so that after determining the processing state of the virtual machine vCPU in the target period, the corresponding target usage rate can be calculated.

[0043] Therefore, through the above technical solution, by collecting the register values ​​of multiple target registers corresponding to the virtual machine vCPU for multiple times, the processing state corresponding to the virtual machine vCPU is determined based on the register value, so that the processing state determined on the host machine can be guaranteed to be consistent with the actual state of the virtual machine, avoiding the error caused by the state identification based on the CPU information of the hypervisor process of the virtual machine, so that the perception of the processing state of the vCPU in the host machine and the virtual machine is consistent, thereby ensuring the accuracy of the utilization rate of the virtual machine vCPU determined on the host machine, while improving the accuracy of the utilization rate of the virtual machine vCPU, simplifying the calculation process of the utilization rate of the virtual machine vCPU, providing effective data support for real-time monitoring and scheduling of virtual machines, so as to be applicable to virtual machine state monitoring in cloud computing scenarios. In addition, the real and effective utilization rate of the virtual machine vCPU is collected on the host machine, which provides a reference for monitoring the operation of the virtual machine and troubleshooting virtual machine problems.

[0044] In a possible embodiment, the target register includes a current process privilege level register, namely, a CPL register;

[0045] The exemplary implementation of determining the processing state corresponding to the virtual machine vCPU according to the register value is as follows, and this step may include:

[0046] Get the register value of the CPL register;

[0047] If the register value of the CPL register is a user state preset value, determining that the processing state corresponding to the virtual machine vCPU is a user state;

[0048] If the register value of the CPL register is a kernel state preset value, it is determined that the processing state corresponding to the virtual machine vCPU is the kernel state, and the target content corresponding to the target execution instruction is obtained.

[0049] Among them, the virtual machine vCPU is similar to the host machine CPU, and both have kernel state and user state processing states. In kernel state, the data of user segment and kernel segment can be accessed, while in user state, the data of user segment can be accessed but not the data of kernel segment.

[0050] In the computer field, the state can be processed by the hardware design of the processor, such as by the value of the register. In the related art, the CPL register is used to indicate the state in which the current program is executed, 0 indicates the kernel state, and 3 indicates the user state. Therefore, in this embodiment, the register value of the CPL register can be directly obtained, so that the processing state in which the program executed by the vCPU is running at the time of sampling can be determined based on the register value.

[0051] For example, the user state preset value may be set to 3, and the kernel state preset value may be set to 0, so as to distinguish the processing state of the vCPU based on the value of the CPL register.

[0052] Further, it is determined whether the virtual machine vCPU is in an idle state according to the target content.

[0053] Among them, the target content can be the most recent instruction executed by the virtual machine vCPU, so as to determine the corresponding processing state according to the most recent instruction, and ensure the consistency between the processing state and the actual state of the virtual machine vCPU. In the virtualization scenario, when the virtual machine sets idle=poll, idle=mwait or idle=halt and does not exit after executing the halt instruction, even if the virtual machine is in an idle state (i.e., idle state), it will not exit from the guest client mode. At this time, the virtual machine process is always in a running state under the perception of the host machine. Therefore, even if the virtual machine vCPU is in an idle state for a long time, that is, its actual utilization rate is very low, but the vCPU perceived on the host machine is always in a running state, the determined utilization rate will be very high, which is inconsistent with the actual state of the virtual machine. In the virtual machine, when the virtual machine vCPU is idle, it will enter an idle process. The code of the idle process belongs to the kernel code, that is, it runs in the kernel state. Therefore, when it is determined that the processing state of the virtual machine vCPU is kernel state, it may be executing meaningful code or it may be in idle state. Therefore, in this embodiment, it is necessary to further judge its actual processing state based on the target execution instruction, that is, to further determine whether it is in idle state.

[0054] Therefore, in this embodiment, when it is determined that the virtual machine is in kernel state, it can be further determined whether it is in idle state based on the most recent instruction executed by the virtual machine vCPU, thereby accurately identifying the state of the virtual machine vCPU, avoiding usage calculation errors caused by identifying the idle state of the virtual machine as the running state, and improving the accuracy of the usage calculated on the host machine.

[0055] In a possible embodiment, the target register further includes a CR0 register and an instruction RIP register, and an exemplary implementation method of obtaining the target content corresponding to the target execution instruction may include:

[0056] Get the register value of the CR0 register, where the CR0 register is one of the control registers in the system.

[0057] The control register can control some important features of the CPU. For example, in the register value of the CR0 register, bit 0 is the protection enable bit PE (Protection Enable), which is used to start the protection mode. If the PE bit is 1, the protection mode is started. If the PE bit is 0, it runs in real mode. The 31st bit is the paging enable bit PG (Paging Enable), which indicates whether the paging unit on the chip is allowed to work. If the PG bit is 1, the paging mode is started. If the PG bit is 0, the paging mode is not started.

[0058] If the register value of the CR0 register indicates that the protection mode and the paging mode are enabled, the register value of the RIP register is acquired.

[0059] When the 0th and 31st bits of the register value of the CR0 register are both 1, it indicates that the protection mode and the paging mode are started, that is, the system functions are applied normally, and the register value of the RIP register can be further obtained. If the 0th and 31st bits of the register value of the CR0 register are not all 1, it means that there may be an abnormality inside the virtual machine and it stays in the BIOS or BootLoader stage. At this time, there is no need to proceed to the subsequent stages and no analysis is performed on the sampling data this time.

[0060] A target linear address corresponding to the target content is determined according to the register value of the RIP register.

[0061] Among them, the RIP register is an instruction register, which stores the address of the current instruction, that is, the linear address of the instruction that the virtual machine vCPU is about to execute. In the present disclosure, the target content can be the most recent instruction executed by the virtual machine vCPU, that is, the most recent instruction is the previous instruction of the instruction corresponding to the linear address stored in the RIP register. Then, based on the register value of the RIP register, the address corresponding to the most recent instruction can be determined.

[0062] For example, the number of bytes corresponding to the last instruction may be preset, such as the last instruction may be set to correspond to x bytes, and the address obtained by subtracting x bytes from the linear address in the register value of the RIP register may be used as the target linear address corresponding to the most recent instruction.

[0063] Performing address conversion according to the target linear address to obtain a physical address corresponding to the target content;

[0064] The target content is acquired according to the physical address.

[0065] In the data storage of the virtual machine, it is necessary to query the physical address of the real storage based on the linear address, and then address conversion can be performed based on the target linear address so as to read the target content.

[0066] Therefore, through the above technical solution, the target linear address of the instruction most recently executed by the virtual machine vCPU can be determined by the register value of the RIP register, and then the corresponding physical address can be determined by address conversion to identify and match the most recent instruction, thereby providing effective reference data for accurately determining the processing status of the virtual machine vCPU.

[0067] In a possible embodiment, the target register further includes a CR3 register and a CR4 register, and an exemplary implementation method of performing address conversion according to the target linear address to obtain a physical address corresponding to the target content may include:

[0068] Determine the physical address of the PGD table based on the obtained register value of the CR3 register.

[0069] The CR3 register stores the page directory address of the virtual address space used by the current process. The upper 20 bits of the CR3 register are used to store the page directory address, and bits 0-11 record the mark bits. The physical address of the PGD (Page Global Directory) table can be determined based on the register value of the CR3 register, so that the PGD table can be read based on the physical address for the next step of data indexing.

[0070] The paging type is determined according to the obtained register value of the CR4 register.

[0071] The CR4 register is used to indicate the processor extended function flag, which includes a flag for indicating the paging type. In the computer field, the paging type is usually indicated based on the 12th bit LA57 of the CR4 register. If CR4.LA57 is set to 0, it means that the paging type is 4-level paging mode, which means that the Pages page is searched based on the 4-level table. If CR4.LA57 is set to 1, it means that the paging type is 5-level paging mode, which means that the Pages page is searched based on the 5-level table. The value of the 12th bit can be read according to the register value of the CR4 register obtained to determine the paging type based on the read value, so that the final physical address can be determined based on the index based on the paging type.

[0072] According to the target linear address and the physical address of the PGD table, address conversion is performed based on the paging type to obtain the physical address corresponding to the target content.

[0073] For example, for 5-level paging, 5-level mmu table mapping is required: PGD→P4D→PUD→PMD→PTE, which is exemplarily described below.

[0074] Among them, in the 5-level paging, such as Figure 2a As shown, the linear address is 57 bits (9+9+9+9+9+12), and the page size can support 4k / 2M / 1G. For example, the address conversion can be performed through the following steps to obtain the target content:

[0075] 1. Use the index represented by the [48:57] bits of the PGD table physical address + the target linear address to find the entry storing the physical address of the P4D (Page Four Directory) table from the PGD table P0, which is the black mark in P0.

[0076] 2. Use the index represented by the [39:47] bits of the P4D table physical address + the target linear address to find the entry storing the physical address of the PUD (Page Upper Directory) table from the P4D table P1, which is the black mark in P1.

[0077] 3. Find the target entry in PUD table P2, that is, the black mark in P2, through the index represented by the [30:38] bits of the PUD table physical address + target linear address.

[0078] At this time, you also need to check the PS (PageSize) flag of the target entry to determine whether large pages are enabled. If PS = 1, it means that large pages are enabled, indicating that the page table entry directly points to the physical page, that is, the target entry points to a physical page address of 1G in size, and the [0:29] bit of the target linear address is the offset within the page. The physical page address + the index represented by the [0:29] bit of the target linear address can be used to determine the physical address corresponding to the target linear address. Then, addressing can be performed based on the physical address to obtain the memory content that is actually needed, that is, the target content. The address conversion ends here. If PS = 0, it means that large pages are not enabled, then the target entry is the entry that stores the physical address of the PMD (Page Middle Directory) table, and proceed to the next step 4.

[0079] 4. Find the target entry in P3 of the PMD table, that is, the black mark in P3, through the index represented by the [21:29] bits of the PMD table physical address + target linear address.

[0080] At this time, you also need to check the PS flag of the target entry to determine whether large pages are enabled. If PS = 1, it means that large pages are enabled, then the target entry points to a physical page address of 2M in size, and the [0:20] bit of the target linear address is the offset within the page. The physical page address + the index represented by the [0:20] bit of the target linear address can be used to determine the physical address corresponding to the target linear address. Then, addressing can be performed based on the physical address to obtain the memory content that is actually needed, that is, the target content. The address conversion ends here. If PS = 0, it means that large pages are not enabled, then the target entry is the entry that stores the physical address of the PT (PageTable) table P4, and proceed to the next step 5.

[0081] 5. Use the index represented by the [12:20] bits of the PT table physical address + target linear address to find the entry that stores the address of physical page P5, which is the black mark in P4.

[0082] 6. The physical address corresponding to the target linear address is determined by the index represented by the [0:11] bit of the physical page address + the target linear address, that is, the black mark in P5. Then, addressing can be performed based on the physical address to obtain the memory content that is actually needed, that is, the target content.

[0083] The address can be converted in the above manner and the target content can be further read.

[0084] For example, for 4-level paging: 4-level mmu table mapping is required: PGD→PUD→PMD→PTE. For example, the entry storing the physical address of the PUD table can be found from the PGD table P0 through the index represented by the [39:47]bit of the PGD table physical address + the target linear address. The target entry in the PUD table P2 can be found through the index represented by the [30:38]bit of the PUD table physical address + the target linear address.

[0085] At this time, you also need to check the PS flag of the target entry to determine whether large pages are enabled. If PS = 1, it means that large pages are enabled, which means that the page table entry directly points to the physical page, that is, the target entry points to the address of the physical page P5 of size 1G. The [0:29] bit of the target linear address is the page offset. The physical page address + the index represented by the [0:29] bit of the target linear address can be used to determine the physical address corresponding to the target linear address. Then, addressing can be performed based on the physical address to obtain the memory content that is actually needed, that is, the target content. The address conversion ends here. Figure 2b shown.

[0086] If PS=0, it means that large pages are not enabled, and the target entry is the entry that stores the physical address of the PMD table. The target entry in the PMD table P3 is found through the index represented by the [21:29] bits of the PMD table physical address + the target linear address.

[0087] At this time, you also need to check the PS flag of the target entry to determine whether large pages are enabled. If PS = 1, it means that large pages are enabled, and the target entry points to the address of the physical page P5 of size 2M. The [0:20] bit of the target linear address is the page offset. The physical page address + the index represented by the [0:20] bit of the target linear address can be used to determine the physical address corresponding to the target linear address. Then, addressing can be performed based on the physical address to obtain the memory content that is actually needed, that is, the target content. The address conversion ends here. Figure 2c shown.

[0088] If PS=0, indicating that large pages are not enabled, the target entry is the entry storing the physical address of the PT table. The entry storing the address of physical page P5 is found from PT table P4 through the index represented by the [12:20]bit of the PT table physical address + the target linear address; the physical address corresponding to the target linear address is determined through the index represented by the [0:11]bit of the physical page address + the target linear address. Then, addressing can be performed based on the physical address to obtain the memory content that is actually needed, that is, the target content, such as Figure 2d shown.

[0089] In a possible embodiment, the exemplary implementation of determining whether the virtual machine vCPU is in an idle state according to the target content may include:

[0090] Matching the target content with a flag byte, wherein the flag byte is a byte included in the instruction executed by the virtual CPU in the idle state;

[0091] If any flag byte is matched in the target content, it is determined that the virtual CPU is in an idle state.

[0092] For example, the flag byte can be determined based on the instruction in the idle state. For example, for the idle=mwait situation in the idle state: the OPCODE of the MWAIT instruction is 0F 01C9. If the last three bytes of the memory in the target content are matched, which are 0x0f, 0x01, and 0xc9 respectively, that is, the flag byte is matched, it proves that the current vCPU is executing the MWAIT instruction, and the processing state of the virtual machine vCPU can be considered to be idle.

[0093] For the idle state idle = poll situation: when executing the kernel code cpu_idle_poll, it will first check the tif_need_resched flag (corresponding to the assembly command [testb$8,%al], TEST instruction OPCODE is A8), and then execute the PAUSE instruction (PAUSE instruction OPCODE is [F3 90]). If the first two of the 8 bytes in the target content are matched, they are 0xa8, 0x08, and the last two bytes are 0xf3, 0x90, that is, the flag byte is matched, and it can be considered that the processing state of the virtual machine vCPU is idle.

[0094] For the case where idle = halt in the idle state and the guest mode is not exited after executing the halt instruction: before the kernel executes the halt instruction, the interrupt bit will be set to allow interrupts. Therefore, the STI instruction (OPCODE is FB) will be executed first, and then the HLT instruction (OPCODE is F4) will be executed. If the last two bytes in the target content are matched, namely 0xfb and 0xf4, that is, the flag byte is matched, it can be considered that the processing state of the virtual machine vCPU is idle.

[0095] It should be noted that the above idle values ​​are exemplary values, and it can also be determined by determining whether the target content contains a flag byte that matches other idle processing methods.

[0096] Therefore, through the above technical scheme, the instructions most recently executed by the virtual machine vCPU can be matched to determine the actual processing state corresponding to the virtual machine vCPU, and the actual running state of the virtual machine vCPU can be detected when the virtual machine vCPU has not exited the client mode, thereby realizing accurate monitoring of the processing state of the virtual machine vCPU on the host machine, so as to facilitate the subsequent determination of the utilization rate of the virtual machine vCPU.

[0097] In a possible embodiment, the target processing state required based on the target usage rate corresponding to the virtual machine vCPU, according to the number of times the virtual machine vCPU is in the target processing state within the target time period, an exemplary implementation method of determining the target usage rate of the virtual machine vCPU is as follows, and this step may include:

[0098] If the target usage rate is the user state usage rate, the user state is used as the target processing state, and the ratio of the number of times corresponding to the user state to the total number of sampling times in the target time period is determined as the user state usage rate of the virtual machine vCPU;

[0099] If the target usage rate is the kernel state usage rate, the kernel state and the idle state are used as the target processing states, and the ratio of the number of times corresponding to the kernel state minus the number of times corresponding to the idle state to the total number of sampling times in the target time period is determined as the kernel state usage rate of the virtual machine vCPU;

[0100] If the target usage rate is the idle state ratio, the idle state is used as the target processing state, and the ratio of the number of times corresponding to the idle state to the total number of sampling times in the target time period is determined as the idle state ratio of the virtual machine vCPU.

[0101] In this embodiment, the number of times the virtual machine vCPU is in the user state, kernel state and idle state during the target time period can be determined during the sampling process of the target time period.

[0102] As an example, a sampling counter, a user state counter, a kernel state counter, and an idle state counter can be initialized, all of which are initialized to zero. Each time a sample is taken, the sampling counter performs an increment operation. If the vCPU is determined to be in the user state based on the current sampling data, the user state counter performs an increment operation. If the vCPU is determined to be in the kernel state based on the current sampling data, the kernel state counter performs an increment operation. Furthermore, in this case, if it is determined that the vCPU is in the idle state, the idle state counter performs an increment operation. In this way, the number of times in different processing states can be counted based on multiple counters, thereby improving the reliability of counting and simplifying the counting process.

[0103] Accordingly, the number of times the virtual machine vCPU is in the user state, kernel state and idle state during the target period can be obtained by reading the values ​​of the user state counter, kernel state counter and idle state counter. Similarly, the total number of samplings during the target period can be obtained by reading the values ​​of the sampling counters.

[0104] The number of times corresponding to the user state is recorded as userCount, and the total number of samples in the target period is sampleCount. The user state usage rate can be expressed as userCount / sampleCount.

[0105] The number of times corresponding to the kernel state is recorded as sysCount, and the number of times corresponding to the idle state is recorded as idleCount. Then the kernel state usage rate can be expressed as (sysCount-idleCount) / sampleCount.

[0106] Correspondingly, the idle state ratio can be expressed as idleCount / sampleCount.

[0107] Therefore, based on the above solution, during the host machine's monitoring of the virtual machine, the usage of the virtual machine's vCPU can be judged from multiple dimensions, and the real and effective usage rate of the virtual machine's vCPU can be collected on the host machine, providing data support for monitoring the operation of the virtual machine and troubleshooting virtual machine problems.

[0108] The present disclosure also provides a device for determining the virtual machine vCPU usage rate, such as Figure 3 As shown, the device 10 comprises:

[0109] The acquisition module 100 is used to acquire register values ​​of multiple target registers corresponding to the virtual machine vCPU multiple times within a target period;

[0110] A first determination module 200 is used to determine a processing state corresponding to the virtual machine vCPU according to the register value, wherein the processing state includes a user state, a kernel state and an idle state;

[0111] The second determination module 300 is used to determine the target usage rate of the virtual machine vCPU based on the target processing state required by the target usage rate corresponding to the virtual machine vCPU and according to the number of times the virtual machine vCPU is in the target processing state within the target time period.

[0112] Optionally, the target register includes a current process privilege level CPL register;

[0113] The first determining module comprises:

[0114] A first acquisition submodule is used to acquire a register value of a CPL register;

[0115] A first determination submodule, configured to determine that the processing state corresponding to the virtual machine vCPU is a user state if the register value of the CPL register is a user state preset value;

[0116] A second acquisition submodule is used to determine that the processing state corresponding to the virtual machine vCPU is the kernel state if the register value of the CPL register is a kernel state preset value, and to acquire the target content corresponding to the target execution instruction;

[0117] The second determination submodule is used to determine whether the virtual machine vCPU is in an idle state according to the target content.

[0118] Optionally, the target register further includes a CR0 register and an instruction RIP register, and the second acquisition submodule includes:

[0119] The third acquisition submodule is used to obtain the register value of the CR0 register;

[0120] A fourth acquisition submodule, configured to acquire a register value of a RIP register if the register value of the CR0 register indicates that the protection mode and the paging mode are enabled;

[0121] A third determination submodule, configured to determine a target linear address corresponding to the target content according to a register value of the RIP register;

[0122] A first conversion submodule, configured to perform address conversion according to the target linear address to obtain a physical address corresponding to the target content;

[0123] The fifth acquisition submodule is used to acquire the target content according to the physical address.

[0124] Optionally, the target register further includes a CR3 register and a CR4 register, and the first conversion submodule includes:

[0125] The fourth determination submodule is used to determine the physical address of the PGD table according to the acquired register value of the CR3 register;

[0126] A fifth determination submodule, used to determine the paging type according to the acquired register value of the CR4 register;

[0127] The second conversion submodule is used to perform address conversion based on the paging type according to the target linear address and the physical address of the PGD table to obtain the physical address corresponding to the target content.

[0128] Optionally, the second determining submodule includes:

[0129] A matching submodule, used for matching the target content with a flag byte, wherein the flag byte is a byte included in the instruction executed by the virtual CPU in the idle state;

[0130] The sixth determination submodule is configured to determine that the virtual CPU is in an idle state if any flag byte is matched in the target content.

[0131] Optionally, the second determining module includes:

[0132] a seventh determination submodule, for, if the target usage rate is a user state usage rate, using the user state as the target processing state, and determining the user state usage rate of the virtual machine vCPU as the ratio of the number of times corresponding to the user state to the total number of sampling times in the target time period;

[0133] an eighth determination submodule, for, if the target usage rate is a kernel state usage rate, using the kernel state and the idle state as the target processing states, and determining the kernel state usage rate of the virtual machine vCPU as the ratio of the number of times corresponding to the kernel state minus the number of times corresponding to the idle state to the total number of sampling times in the target time period;

[0134] The ninth determination submodule is used to determine the idle state as the target processing state if the target usage rate is the idle state ratio, and determine the idle state ratio of the virtual machine vCPU as the ratio of the number of times corresponding to the idle state to the total number of sampling times in the target time period.

[0135] Reference below Figure 4 , which shows a schematic diagram of the structure of an electronic device 600 suitable for implementing the embodiment of the present disclosure. The terminal device in the embodiment of the present disclosure may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (such as vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0136] like Figure 4 As shown, the electronic device 600 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage device 608 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the electronic device 600 are also stored. The processing device 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0137] Typically, the following devices may be connected to the I / O interface 605: an input device 606 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 607 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 608 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 609. The communication device 609 may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 4 The electronic device 600 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0138] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 609, or installed from a storage device 608, or installed from a ROM 602. When the computer program is executed by the processing device 601, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0139] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0140] In some embodiments, the client and the server may communicate using any currently known or future developed network protocol such as HTTP (HyperText Transfer Protocol), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0141] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0142] The above-mentioned computer-readable medium carries one or more programs. When the above-mentioned one or more programs are executed by the electronic device, the electronic device: collects register values ​​of multiple target registers corresponding to the virtual machine vCPU for multiple times within a target time period; determines the processing state corresponding to the virtual machine vCPU based on the register values, wherein the processing state includes user state, kernel state and idle state; based on the target processing state required for the target usage rate corresponding to the virtual machine vCPU, determines the target usage rate of the virtual machine vCPU according to the number of times the virtual machine vCPU corresponds to the target processing state within the target time period.

[0143] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including, but not limited to, object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0144] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0145] The modules involved in the embodiments described in the present disclosure may be implemented by software or hardware. The name of a module does not limit the module itself in some cases. For example, a collection module may also be described as "a module that collects register values ​​of multiple target registers corresponding to a virtual machine vCPU multiple times within a target period of time".

[0146] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0147] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0148] According to one or more embodiments of the present disclosure, Example 1 provides a method for determining a virtual machine vCPU usage rate, wherein the method includes:

[0149] Collect register values ​​of multiple target registers corresponding to the virtual machine vCPU multiple times within a target time period;

[0150] Determine, according to the register value, a processing state corresponding to the virtual machine vCPU, wherein the processing state includes a user state, a kernel state, and an idle state;

[0151] Based on the target processing state required for the target usage rate corresponding to the virtual machine vCPU, the target usage rate of the virtual machine vCPU is determined according to the number of times the virtual machine vCPU corresponds to the target processing state within the target time period.

[0152] According to one or more embodiments of the present disclosure, Example 2 provides the method of Example 1, wherein the target register includes a current process privilege level CPL register;

[0153] Determining the processing state corresponding to the virtual machine vCPU according to the register value includes:

[0154] Get the register value of the CPL register;

[0155] If the register value of the CPL register is a user state preset value, determining that the processing state corresponding to the virtual machine vCPU is a user state;

[0156] If the register value of the CPL register is a kernel state preset value, determining that the processing state corresponding to the virtual machine vCPU is kernel state, and obtaining the target content corresponding to the target execution instruction;

[0157] Determine whether the virtual machine vCPU is in an idle state according to the target content.

[0158] According to one or more embodiments of the present disclosure, Example 3 provides the method of Example 2, wherein the target register further includes a CR0 register and an instruction RIP register, and the step of obtaining the target content corresponding to the target execution instruction includes:

[0159] Get the register value of CR0 register;

[0160] If the register value of the CR0 register indicates that the protection mode and the paging mode are enabled, the register value of the RIP register is obtained;

[0161] Determining a target linear address corresponding to the target content according to a register value of the RIP register;

[0162] Performing address conversion according to the target linear address to obtain a physical address corresponding to the target content;

[0163] The target content is acquired according to the physical address.

[0164] According to one or more embodiments of the present disclosure, Example 4 provides the method of Example 3, wherein the target register further includes a CR3 register and a CR4 register, and performing address conversion according to the target linear address to obtain a physical address corresponding to the target content includes:

[0165] According to the obtained register value of CR3 register, determine the physical address of PGD table;

[0166] Determine the paging type based on the obtained register value of the CR4 register;

[0167] According to the target linear address and the physical address of the PGD table, address conversion is performed based on the paging type to obtain the physical address corresponding to the target content.

[0168] According to one or more embodiments of the present disclosure, Example 5 provides the method of Example 2, wherein determining whether the virtual machine vCPU is in an idle state according to the target content includes:

[0169] Matching the target content with a flag byte, wherein the flag byte is a byte included in the instruction executed by the virtual CPU in the idle state;

[0170] If any flag byte is matched in the target content, it is determined that the virtual CPU is in an idle state.

[0171] According to one or more embodiments of the present disclosure, Example 6 provides the method of Example 1, wherein the target processing state required for the target usage rate corresponding to the virtual machine vCPU is determined based on the number of times the virtual machine vCPU corresponds to the target processing state within the target period, and includes:

[0172] If the target usage rate is the user state usage rate, the user state is used as the target processing state, and the ratio of the number of times corresponding to the user state to the total number of sampling times in the target time period is determined as the user state usage rate of the virtual machine vCPU;

[0173] If the target usage rate is the kernel state usage rate, the kernel state and the idle state are used as the target processing states, and the ratio of the number of times corresponding to the kernel state minus the number of times corresponding to the idle state to the total number of sampling times in the target time period is determined as the kernel state usage rate of the virtual machine vCPU;

[0174] If the target usage rate is the idle state ratio, the idle state is used as the target processing state, and the ratio of the number of times corresponding to the idle state to the total number of sampling times in the target time period is determined as the idle state ratio of the virtual machine vCPU.

[0175] According to one or more embodiments of the present disclosure, Example 7 provides a device for determining a virtual machine vCPU usage rate, wherein the device includes:

[0176] A collection module, used for collecting register values ​​of multiple target registers corresponding to the virtual machine vCPU multiple times within a target period;

[0177] A first determination module is used to determine a processing state corresponding to the virtual machine vCPU according to the register value, wherein the processing state includes a user state, a kernel state and an idle state;

[0178] The second determination module is used to determine the target usage rate of the virtual machine vCPU based on the target processing state required by the target usage rate corresponding to the virtual machine vCPU and according to the number of times the virtual machine vCPU is in the target processing state within the target time period.

[0179] According to one or more embodiments of the present disclosure, Example 8 provides the apparatus of Example 7, wherein the target register includes a current process privilege level CPL register;

[0180] The first determining module comprises:

[0181] A first acquisition submodule is used to acquire a register value of a CPL register;

[0182] A first determination submodule, configured to determine that the processing state corresponding to the virtual machine vCPU is a user state if the register value of the CPL register is a user state preset value;

[0183] A second acquisition submodule is used to determine that the processing state corresponding to the virtual machine vCPU is the kernel state if the register value of the CPL register is a kernel state preset value, and to acquire the target content corresponding to the target execution instruction;

[0184] The second determination submodule is used to determine whether the virtual machine vCPU is in an idle state according to the target content.

[0185] According to one or more embodiments of the present disclosure, Example 9 provides a computer-readable medium having a computer program stored thereon, which implements the steps of any of the methods described in Examples 1-6 when executed by a processing device.

[0186] According to one or more embodiments of the present disclosure, Example 10 provides an electronic device, including:

[0187] a storage device having a computer program stored thereon;

[0188] A processing device is used to execute the computer program in the storage device to implement the steps of the method described in any one of Examples 1-6.

[0189] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.

[0190] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0191] Although the subject matter has been described in language specific to structural features and / or method logic actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims. Regarding the device in the above embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.

Claims

1. A method for determining a virtual machine vCPU usage rate, characterized in that: The method comprises: Collect register values ​​of multiple target registers corresponding to the virtual machine vCPU multiple times within a target time period; Determine, according to the register value, a processing state corresponding to the virtual machine vCPU, wherein the processing state includes a user state, a kernel state, and an idle state; Based on the target processing state required for the target usage rate corresponding to the virtual machine vCPU, determine the target usage rate of the virtual machine vCPU according to the number of times the virtual machine vCPU is in the target processing state within the target time period; Wherein, the target register includes the current process privilege level CPL register; Determining the processing state corresponding to the virtual machine vCPU according to the register value includes: Obtaining the register value of the CPL register; If the register value of the CPL register is a user state preset value, determining that the processing state corresponding to the virtual machine vCPU is a user state; If the register value of the CPL register is a kernel state preset value, determining that the processing state corresponding to the virtual machine vCPU is kernel state, and obtaining the target content corresponding to the target execution instruction; Determine whether the virtual machine vCPU is in an idle state according to the target content; The determining, according to the target content, whether the virtual machine vCPU is in an idle state includes: Matching the target content with a flag byte, wherein the flag byte is a byte included in the instruction executed by the virtual vCPU in the idle state; If any flag byte is matched in the target content, it is determined that the virtual vCPU is in an idle state.

2. The method according to claim 1, characterized in that The target register also includes a CR0 register and an instruction RIP register, and the target content corresponding to the target execution instruction is obtained, including: Get the register value of CR0 register; If the register value of the CR0 register indicates that the protection mode and the paging mode are enabled, the register value of the RIP register is obtained; Determining a target linear address corresponding to the target content according to a register value of the RIP register; Performing address conversion according to the target linear address to obtain a physical address corresponding to the target content; The target content is acquired according to the physical address.

3. The method according to claim 2, characterized in that The target register further includes a CR3 register and a CR4 register, and performing address conversion according to the target linear address to obtain a physical address corresponding to the target content includes: According to the obtained register value of CR3 register, determine the physical address of PGD table; Determine the paging type based on the obtained register value of the CR4 register; According to the target linear address and the physical address of the PGD table, address conversion is performed based on the paging type to obtain the physical address corresponding to the target content.

4. The method according to claim 1, characterized in that: The target processing state required based on the target usage rate corresponding to the virtual machine vCPU, and determining the target usage rate of the virtual machine vCPU according to the number of times the virtual machine vCPU is in the target processing state within the target time period, includes: If the target usage rate is the user state usage rate, the user state is used as the target processing state, and the ratio of the number of times corresponding to the user state to the total number of sampling times in the target time period is determined as the user state usage rate of the virtual machine vCPU; If the target usage rate is the kernel state usage rate, the kernel state and the idle state are used as the target processing states, and the ratio of the number of times corresponding to the kernel state minus the number of times corresponding to the idle state to the total number of sampling times in the target time period is determined as the kernel state usage rate of the virtual machine vCPU; If the target usage rate is the idle state ratio, the idle state is used as the target processing state, and the ratio of the number of times corresponding to the idle state to the total number of sampling times in the target time period is determined as the idle state ratio of the virtual machine vCPU.

5. A device for determining a virtual machine vCPU usage rate, characterized in that: The device comprises: A collection module, used for collecting register values ​​of multiple target registers corresponding to the virtual machine vCPU multiple times within a target period; A first determination module is used to determine a processing state corresponding to the virtual machine vCPU according to the register value, wherein the processing state includes a user state, a kernel state and an idle state; A second determination module is used to determine the target utilization rate of the virtual machine vCPU based on the target processing state required by the target utilization rate corresponding to the virtual machine vCPU and according to the number of times the virtual machine vCPU is in the target processing state within the target time period; Wherein, the target register includes the current process privilege level CPL register; The first determining module comprises: A first acquisition submodule, used to acquire the register value of the CPL register; A first determination submodule, configured to determine that the processing state corresponding to the virtual machine vCPU is a user state if the register value of the CPL register is a user state preset value; A second acquisition submodule is used to determine that the processing state corresponding to the virtual machine vCPU is the kernel state if the register value of the CPL register is a kernel state preset value, and to acquire the target content corresponding to the target execution instruction; A second determination submodule is used to determine whether the virtual machine vCPU is in an idle state according to the target content; The second determining submodule includes: A matching submodule, used to match the target content with a flag byte, wherein the flag byte is a byte included in the instruction executed by the virtual vCPU in the idle state; The sixth determination submodule is used to determine that the virtual vCPU is in an idle state if any flag byte is matched in the target content.

6. A computer readable medium having a computer program stored thereon, characterized in that: When the program is executed by a processing device, the steps of the method described in any one of claims 1 to 4 are implemented.

7. An electronic device, characterized in that: include: a storage device having a computer program stored thereon; A processing device, configured to execute the computer program in the storage device to implement the steps of the method according to any one of claims 1 to 4.

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