Substrate support with multiple embedded electrodes

Abstract

A method and apparatus for biasing regions of a substrate in a plasma assisted processing chamber is provided. Biasing the substrate (or regions of the substrate) increases the potential difference between the substrate and a plasma formed in the processing chamber, thereby accelerating ions from the plasma toward the active surface of the substrate region. The plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that facilitates managing uniformity of processing results across the substrate.

Description

[0001] This application is a divisional of the Chinese Patent Application No. 201880053380.1 filed on July 19, 2018, entitled “Substrate Support with Multiple Embedded Electrodes,” (PCT Application No. PCT / US2018 / 042956) having a filing date of July 19, 2018. TECHNICAL FIELD

[0002] Embodiments described herein relate generally to processing chambers used in semiconductor manufacturing, and in particular, to processing chambers having substrate support assemblies configured to bias a substrate and methods of biasing a substrate. BACKGROUND

[0003] Reliably producing high aspect ratio features is one of the key technical challenges for next generation very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. One method of forming high aspect ratio features uses a plasma assisted etching process to form high aspect ratio openings in a material layer of a substrate, such as a dielectric layer. In a typical plasma assisted etching process, a plasma is formed in a processing chamber and ions from the plasma are accelerated toward a substrate and an opening formed in a mask on the substrate to form an opening in the material layer below the mask surface. Typically, the ions are accelerated toward the substrate by coupling a low frequency RF power in the range of 400 kHz to 2 MHz to the substrate, which results in a bias voltage on the substrate. However, coupling the RF power to the substrate does not apply a single voltage to the substrate relative to the plasma. In a commonly used configuration, the potential difference between the substrate and the plasma oscillates from a near zero value to a maximum negative value at the frequency of the RF power. The lack of a single potential that accelerates the ions from the plasma to the substrate results in a large range of ion energies at the substrate surface and in the opening (feature) formed in the material layer of the substrate. Additionally, the different ion trajectories resulting from the RF bias result in a large angular distribution of ions relative to the substrate surface. A large range of ion energies is undesirable when etching an opening of a high aspect ratio feature because the ions do not reach the bottom of the feature with a high enough energy to maintain a desired etch rate. A large angular distribution of ions relative to the substrate surface is undesirable because it results in distortion of the feature profile, such as necking in the vertical sidewalls of the feature profile and bowing.

[0004] Accordingly, there is a need in the art to be able to provide a narrow range of high energy ions with a low angular distribution at a material surface of a substrate during a plasma assisted etching process. SUMMARY

[0005] The present disclosure relates generally to a plasma-assisted processing chamber or a plasma-enhanced processing chamber. More specifically, embodiments herein relate to an electrostatic chuck (ESC) substrate configured to provide individual pulsed (cycled) DC voltage to regions of a substrate during a plasma-assisted semiconductor manufacturing process or a plasma-enhanced semiconductor manufacturing process and a method of biasing regions of a substrate.

[0006] In one embodiment, a substrate support assembly is provided, the substrate support assembly comprising a substrate support comprising: a plurality of first electrodes within the substrate support, each electrode of the plurality of first electrodes being electrically isolated and coplanar with every other electrode of the plurality of first electrodes, wherein each electrode of the plurality of first electrodes is configured to provide pulsed DC power to a region of a substrate through capacitive coupling with the region of the substrate; and a second electrode disposed within the substrate support and electrically isolated from the plurality of first electrodes for electrically clamping the substrate to the substrate support.

[0007] Other embodiments provide a processing chamber comprising: one or more sidewalls and a bottom defining a processing volume; and a substrate support. The substrate support comprises: a plurality of first electrodes within the substrate support, each electrode of the plurality of first electrodes being electrically isolated and coplanar with every other electrode of the plurality of first electrodes, wherein each electrode of the plurality of first electrodes is configured to provide pulsed DC bias to a region of a substrate through capacitive coupling with the region of the substrate; and a second electrode disposed within the substrate support and electrically isolated from the plurality of first electrodes for electrically clamping the substrate to the substrate support.

[0008] In another embodiment, a method of biasing a substrate with a plurality of cycled DC voltages is provided. The method comprises the steps of: flowing a process gas into a processing chamber; forming a plasma from the process gas; electrically clamping a substrate to a substrate support disposed in the processing chamber; and biasing the substrate across a plurality of regions. Biasing the substrate across the plurality of regions comprises the step of: coupling a plurality of cycled DC voltages provided to a plurality of biasing electrodes disposed in the substrate support through a capacitance of a first dielectric layer of the substrate support to respective regions of the substrate by a switching system. The plurality of cycled DC voltages herein comprises a series of frequencies and / or a plurality of polarities. BRIEF DESCRIPTION OF DRAWINGS

[0009] Therefore, and in a manner that will become more apparent upon reading the following specification, the present disclosure can best be understood by reference to the following illustrative

[0010] Figure 1 is a schematic cross-sectional view of a processing chamber in which an electrostatic chuck (ESC) substrate support assembly is disposed, according to one embodiment.

[0011] Figure 2A is a close-up cross-sectional view of a substrate support assembly used in the processing chamber of Figure 1

[0012] Figure 2B is a top view of the substrate support assembly shown in Figure 2A

[0013] Figure 3 is a flowchart illustrating a method of biasing regions of a substrate during a plasma- assisted process, according to embodiments described herein. DETAILED DESCRIPTION

[0014] Embodiments of the present disclosure generally relate to plasma processing chambers, such as plasma-assisted processing chambers or plasma-enhanced processing chambers. More specifically, embodiments herein relate to electrostatic chuck (ESC) substrate supports configured to provide a capacitively coupled pulsed DC voltage to a substrate disposed on the electrostatic chuck (ESC) substrate support during a plasma-assisted semiconductor manufacturing process or a plasma-enhanced semiconductor manufacturing process. Capacitively coupling a substrate to a cyclic DC power source (placing a pulsed DC bias on the substrate) increases the potential difference between the substrate and a plasma formed in the processing chamber, thereby accelerating ions from the plasma toward the active surface of the substrate. In contrast to an RF bias, a pulsed DC bias provides a single potential for the acceleration of ions from the plasma to the substrate. Substrate supports herein include a plurality of bias electrodes, each independently coupled to a portion of a pulsed DC power supply switching system, and each configured to provide a tunable bias to a region of the substrate through capacitive coupling with the region of the substrate. The plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that facilitates managing uniformity of processing results across the substrate.

[0015] Figure 1 ​​is a schematic cross-sectional view of a processing chamber 100 having an electrostatic chuck (ESC) substrate support assembly 200 disposed in the processing chamber 100, according to one embodiment. In this embodiment, the processing chamber 100 is a plasma processing chamber, such as a plasma etch chamber, a plasma enhanced deposition chamber (e.g., a plasma enhanced chemical vapor deposition (PECVD) chamber or a plasma enhanced atomic layer deposition (PEALD) chamber), or a plasma-based ion implantation chamber (e.g., a plasma doping (PLAD) chamber).

[0016] The processing chamber 100 features a chamber lid 103, one or more sidewalls 102, and a chamber bottom 104 that define a processing volume 120. A showerhead 112 (having a plurality of openings 118 disposed therethrough) is disposed in the chamber lid 103 and is used to uniformly distribute a process gas from a gas inlet 114 into the processing volume 120. The showerhead 112 is coupled to an RF power supply 142 (or, in some embodiments, a VHF power supply), which forms a plasma 135 from the process gas through capacitive coupling therewith. The processing volume 120 is fluidly coupled to a vacuum, such as to one or more dedicated vacuum pumps, through a vacuum outlet 152 that maintains the processing volume 120 at sub-atmospheric conditions and exhausts process and other gases from the processing volume 120. A substrate support assembly 200 disposed in the processing volume 120 is disposed on a support shaft 124 that extends sealingly through the chamber bottom 104. The support shaft 124 is coupled to a controller 140 that raises and lowers the support shaft 124 and the substrate support assembly 200 disposed thereon to facilitate processing of a substrate 115 and transfer of the substrate 115 into and out of the processing chamber 100. Typically, the substrate 115 is spaced apart from the showerhead 112 by between about 0.75 inches and 1.75 inches, such as about 1.25 inches, when the substrate support assembly 200 is in a raised or processing position.

[0017] The substrate 115 is loaded into the processing volume 120 through an opening 126 in one of the one or more sidewalls 102, which is typically sealed with a door or valve (not shown) during processing of the substrate 115. A plurality of lift pins 136 disposed above a lift pin collar 134 are movably disposed through the substrate support assembly 200 to facilitate transfer of the substrate 115 to and from the substrate support assembly 200. The lift pin collar 134 is coupled to a lift collar shaft 131 that extends sealingly through the chamber bottom 104, which is raised and lowered by the lift pin collar 134 by an actuator 130. The substrate support assembly 200 has a substrate support 227 on which a substrate is disposed for processing. When the lift pin collar 134 is in a raised position, the plurality of lift pins 136 extend above the surface of the substrate support 227 to lift the substrate 115 from the surface of the substrate support 227 and enable access to the substrate 115 by a robot handler (not shown). When the lift pin collar 134 is in a lowered position, the plurality of lift pins 136 are flush with or below the surface of the substrate support 227, and the substrate 115 is disposed directly on the surface of the substrate support 227 for processing.

[0018] The substrate support assembly 200 herein includes a cooling base 125. The substrate support 227 is thermally coupled to and disposed on the cooling base 125. The cooling base 125 of the substrate support assembly 200 is used to regulate the temperature of the substrate support 227, and thereby the temperature of the substrate 115 disposed on the substrate support surface 203, during processing. Herein, the cooling base 125 can include one or more fluid conduits 137 disposed therein that are fluidically coupled to and in fluid communication with a coolant source 133, such as a refrigerant source or a water source. Typically, the cooling base 125 is formed of a corrosion resistant, thermally conductive material, such as a corrosion resistant metal, e.g., aluminum, an aluminum alloy, or stainless steel, and is thermally coupled to the substrate support 227 with an adhesive or by mechanical means.

[0019] During processing, ion bombardment of the substrate 115 will heat the substrate 115 to a high temperature that can be undesirable because the low pressure of the processing volume 120 results in poor heat conduction between the substrate 115 and the substrate support surface 203. Accordingly, in embodiments herein, a backside gas is provided between the substrate 115 and the substrate support surface 203 during processing, where the backside gas thermally couples the substrate 115 to the substrate support surface 203 and increases heat transfer therebetween. Typically, the substrate support surface 203 includes a plurality of protrusions 228 extending from the substrate support surface 203 that are capable of causing the backside gas to flow in or occupy the space between the substrate 115 and the substrate support surface 203 when the substrate 115 is disposed on the substrate support surface 203. The backside gas flows to the substrate support surface 203 through one or more gas conduits 147 disposed through the substrate support 227. In this regard, the one or more gas conduits 147 are coupled to a thermally conductive inert backside gas source 146, such as a helium gas source.

[0020] Figure 2A is a close-up cross-sectional view of the substrate support assembly 200 used in the processing chamber 100 of Figure 1 Figure 2B is a top view of the substrate support assembly 200 shown in Figure 2A In this regard, the substrate support 227 includes a first layer 227A and a second layer 227B, where each layer 227AB is formed from a dielectric material including a metal oxide or a metal nitride, or a mixture including a metal oxide or a metal nitride, such as AI2O3, AIN, Y2O3, or combinations thereof. In some embodiments, the first layer 227A is formed from a dielectric material having a breakdown voltage between about 20 V / pm and about 200 V / pm, such as between about 100 V / pm and about 200 V / pm or between about 20 V / pm and about 100 V / pm. In one embodiment, the first layer 227A is formed from 99.5% aluminum oxide having a breakdown voltage of 9 kV at about 160 pm. In some embodiments, the substrate support 227 is formed by joining a bulk dielectric material to the second layer 227B and a plurality of electrodes disposed in or on the second layer 227B prior to grinding the bulk dielectric material to a desired thickness D to form the first layer 227A. Typically, the thickness D of the first layer 227A is between about 5 pm and about 300 pm, such as between about 100 pm and about 300 pm, for example about 160 pm. In other embodiments, the first layer 227A is formed using any suitable coating method, such as CVD, PECVD, ALD, PEALD, evaporation, sputtering, plasma arc coating, aerosol coating, or combinations thereof. ​

[0021] The plurality of electrodes disposed in and / or embedded in the substrate support 227 herein includes a plurality of bias electrodes 238A-C and a single ESC electrode 222. Each electrode of the plurality of bias electrodes is electrically isolated from each other electrode of the plurality of bias electrodes and from the single ESC electrode 222. Each electrode of the plurality of bias electrodes 238A-C herein is configured to provide one or more independent pulsed DC bias to a respective region of the substrate 115 by capacitive coupling with the respective region of the substrate 115. The single ESC electrode 222 provides a clamping force between the substrate 115 and the substrate support surface 203 by providing an electrical potential between the substrate 115 and the substrate support surface 203. Typically, the ESC electrode is coupled to a static DC power supply, which herein provides between about -5000 V and about 5000 V, such as between about 100 V and about 4000 V, such as between about 1000 V and about 3000 V, for example about 2000 V.

[0022] In embodiments herein, the substrate support 227 can be configured to support 300 mm diameter substrates and can include between 2 and 20 bias electrodes, such as the three bias electrodes 238A-C shown, however, larger substrate supports for processing larger substrates and / or substrates of different shapes can include any number of bias electrodes. The plurality of bias electrodes 238A-C are each formed from one or more electrically conductive material portions, such as a metal mesh, foil, plate, or combinations thereof. In some embodiments, each of the plurality of bias electrodes 238A-C is formed from more than one discrete electrically conductive material portion, such as a plurality of metal meshes, foils, plates, or combinations thereof, which are electrically coupled with one or more connectors disposed in the substrate support 227 (not shown) such that the electrically coupled discrete material portions comprise a single electrode, such as the center bias electrode 238A, the middle bias electrode 238B, or the outer bias electrode 238C.

[0023] The plurality of bias electrodes 238A-C are spatially arranged across the substrate support 227 in a pattern that facilitates managing uniformity of processing results across the substrate 115. In some embodiments, the plurality of bias electrodes 238A-C are arranged in a pattern that facilitates managing uniformity of processing results across the substrate 115 by providing one or more independent pulsed DC bias to a respective region of the substrate 115 by capacitive coupling with the respective region of the substrate 115. In some embodiments, the plurality of bias electrodes 238A-C are arranged in a pattern that facilitates managing uniformity of processing results across the substrate 115 by providing one or more independent pulsed DC bias to a respective region of the substrate 115 by capacitive coupling with the respective region of the substrate 115. Figure 2AIn the illustrated embodiment, the circular plate of center bias electrode 238A and the discontinuous annular regions of bias electrodes 238B-C define a plurality of concentric regions. Other spatial arrangements can be used, including a spoke pattern, a grid pattern, a line pattern, a spiral pattern, a cross pattern, a random pattern, or combinations thereof. Herein, each of the plurality of bias electrodes 238A-C is coplanar with each other of the plurality of bias electrodes and the single ESC electrode 222. The single ESC electrode 222 is disposed planarly with the substrate support 227 and parallel to the substrate support surface 203. Each of the plurality of bias electrodes 238A-C is electrically isolated from the single ESC electrode 222 by openings formed in the single ESC electrode 222 and by the dielectric material of the substrate support 227 disposed therebetween. In other embodiments, each of the plurality of bias electrodes 208A-C or a portion of each of the plurality of bias electrodes 208A-C is coplanar with at least a portion of each other of the plurality of bias electrodes and the plurality of bias electrodes 208A-C is closer to the substrate support surface 203 than the single ESC electrode 222.

[0024] Herein, each of the plurality of bias electrodes 238A-C is independently electrically coupled to a portion of a DC power supply switching system 150 comprising a plurality of solid state pulse generators / switches, herein a plurality of first switches SI, S3, S5 and a plurality of second switches S2, S4, S6 are capable of converting high voltage (HV) DC power to a cyclic DC voltage having a frequency between about 10 Hz (or lower) and about 100 kHz. The plurality of first switches SI, S3, S5 and the plurality of second switches S2, S4, S6 are further capable of converting high voltage (HV) DC power to a cyclic DC voltage having a duty cycle in a range of 2% to 98%. The switches SI-S6 are cyclically operated at a frequency or on demand according to any pattern or no pattern. Each of the plurality of bias electrodes is electrically coupled to one of the plurality of first switches SI, S3, S5 and one of the plurality of second switches S2, S4, S6.

[0025] Herein, the plurality of first switches SI, S3, S5 are electrically coupled to a first DC voltage source 156B, which can be, for example, a positive (+ve) voltage source, and the plurality of second switches S2, S4, S6 are electrically coupled to a second DC voltage source 156A, which can be, for example, a negative (-ve) voltage source. In other embodiments, both voltage sources 156A and 156B can be positive sources of different voltages or negative sources of different voltages. The first and second DC voltage sources 156B and 156A herein provide a DC bias (positive or negative) between about 0 V and about 10 kV in their respective voltage amplitudes.

[0026] Each set of switches, such as S1 and S2, S3 and S4, or S5 and S6, operates independently to provide individual frequencies, patterns, or operations of the cycling DC voltage of positive or negative polarity to individual bias electrodes 238A-C of the substrate support 227, and through capacitive coupling with their respective regions of the substrate support 227, to provide individual pulsed DC bias to respective regions of the substrate 115 disposed on the substrate support 227. In general, coupling a negative DC pulse to a substrate region will increase the potential difference between the substrate region and the plasma 135, where the substrate region is at a more negative potential than the plasma during the pulse. With such a negative DC bias, positively charged species in the plasma will accelerate toward the surface of the substrate region, enabling processing of the substrate region. Coupling a positive DC pulse to a substrate region will increase the potential difference between the substrate region and the plasma 135, where the substrate region is at a more positive potential than the plasma during the pulse. With such a positive DC bias, negatively charged species in the plasma will accelerate toward the surface of the substrate region, enabling processing of the substrate region. The ability to adjust the frequency, duty cycle, and / or duration of the cycling DC voltage for positive and negative DC bias conditions provided to different substrate regions allows tuning of the uniformity across the substrate processing and improvements across the substrate processing. Among other useful attributes, the ability to apply positive and negative DC bias pulses provides charge neutralization of the substrate region, where the surface of the substrate region can be periodically brought into a neutral charge state.

[0027] Figure 3 is a flow diagram illustrating a method 300 of biasing a region of a substrate during a plasma assisted process, according to embodiments described herein. At 310, the method 300 includes flowing a process gas into a process chamber, and at 320, the method includes forming a plasma from the process gas.

[0028] At 330, the method includes electrically chucking a substrate to a substrate support disposed in the process chamber using a chucking electrode disposed in the substrate support, the substrate support including a first dielectric layer and a second dielectric layer.

[0029] At 340, the method 300 includes providing a plurality of cycling DC voltages to a plurality of bias electrodes disposed in the substrate support, where each respective cycling DC voltage provides an individual pulsed DC bias to a region of the substrate through capacitive coupling with the region of the substrate. In some embodiments, the plurality of cycling DC voltages includes more than one polarity, more than one frequency, more than one duty cycle, and / or more than one duration. The pulsed DC bias causes ions in the plasma formed at 330 to accelerate toward the substrate to perform a material process, such as deposition or removal, on the substrate. It should be noted that the plasma can also be formed after 320, after 330, after 340, or after 350.

[0030] The substrate support assemblies and methods described herein enable a capacitively coupled pulsed DC bias substrate during plasma assisted processing compatible with the use of electrostatic clamping forces. The pulsed DC bias allows for increased control of ion energy and angular distribution at and into features formed on the substrate surface and / or in feature openings in the substrate surface. This increased control is desirable at least when forming high aspect ratio features and / or features requiring a square etch profile, such as in silicon etching for shallow trench isolation (STI) applications, or silicon fins used in FinFET technology. The ability to apply DC pulses of different frequencies, duty cycles, polarity, and / or durations to different areas of the substrate enables tuning of process uniformity across the substrate and improvements in processing across the substrate.

[0031] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure can be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the following claims.

Claims

1. A substrate processing system, the substrate processing system comprising a substrate support assembly, the substrate support assembly comprising: A metal base having a substrate support disposed thereon, the substrate support including a plurality of electrodes, wherein Each of the plurality of electrodes is spaced apart from the substrate support surface of the substrate support member by a first dielectric material layer. The plurality of electrodes are spaced apart from the metal base by a second dielectric material layer. Each of the plurality of electrodes is isolated from each of the other plurality of electrodes by a portion of the second dielectric material layer. The first bias electrode among the plurality of electrodes is electrically coupled to a first pulsed DC voltage source. The second bias electrode among the plurality of electrodes is coupled to a second pulsed DC voltage source. The second bias electrode of the plurality of electrodes is disposed radially outward relative to the first bias electrode, and at least partially surrounds the first bias electrode. A third clamping electrode of the plurality of electrodes is coupled to a clamping power supply for electrically clamping the substrate to the substrate support surface of the substrate support, wherein each of the first bias electrode and the second bias electrode is electrically isolated from the third clamping electrode by a plurality of openings formed in the third clamping electrode and by the second dielectric material layer.

2. The substrate processing system of claim 1, wherein the first dielectric material layer has a thickness between 5 μm and 300 μm.

3. The substrate processing system of claim 1, wherein the third clamping electrode comprises a metal mesh.

4. The substrate processing system of claim 1, wherein the first bias electrode and the second bias electrode are concentrically disposed around the center of the substrate support surface of the substrate support member.

5. The substrate processing system of claim 4, wherein the first bias electrode has a circular shape in a plane parallel to the substrate support surface.

6. The substrate processing system of claim 4, wherein the second bias electrode is disposed adjacent to the circumferential edge of the substrate support.

7. The substrate processing system of claim 4, wherein... The substrate support surface includes multiple protrusions, and One or more gas conduits formed through the substrate support are in fluid communication with the space formed between multiple protrusions on the substrate support surface.

8. The substrate processing system of claim 7, wherein the one or more gas conduits are fluidly coupled to an inert gas source.

9. The substrate processing system of claim 8, wherein one or more fluid conduits formed in the metal substrate are fluidly coupled to a coolant source.

10. The substrate processing system of claim 9, wherein the substrate support and the metal base are thermally coupled through an adhesive layer sandwiched between them.

11. The substrate processing system of claim 1, wherein the first pulse DC voltage source includes a first high-voltage DC power supply and one or more first switches for converting a first static DC voltage from the first high-voltage DC power supply to a first pulse DC voltage.

12. The substrate processing system of claim 11, wherein the second pulse DC voltage source includes a second high-voltage DC power supply and one or more second switches for converting the second static DC voltage from the second high-voltage DC power supply to the second pulse DC voltage.

13. The substrate processing system of claim 1, wherein The first pulsed DC voltage source includes a first high-voltage DC power supply, which is configured to provide a negative DC voltage to the first bias electrode of the plurality of electrodes. The second pulsed DC voltage source includes a second high-voltage DC power supply configured to provide a negative DC voltage to the second bias electrode of the plurality of electrodes.

14. The substrate processing system of claim 13, further comprising an RF power supply for forming capacitively coupled plasma in the processing volume of the processing system.

15. A method for processing a substrate, the method comprising: The substrate is positioned on a substrate support disposed within the processing volume, the substrate support comprising a plurality of electrodes, wherein The substrate support is mounted on a metal base. Each of the plurality of electrodes is spaced apart from the substrate support surface of the substrate support member by a first dielectric material layer. The plurality of electrodes are spaced apart from the metal base by a second dielectric material layer. The first bias electrode among the plurality of electrodes is electrically coupled to a first pulsed DC voltage source. The second bias electrode among the plurality of electrodes is coupled to a second pulsed DC voltage source, and The second bias electrode of the plurality of electrodes at least partially surrounds a portion of the first bias electrode; Plasma is formed within the processing volume; A clamping voltage is applied to a third clamping electrode among the plurality of electrodes to electrically clamp the substrate to the substrate support, wherein each of the first bias electrode and the second bias electrode is electrically isolated from the third clamping electrode by a plurality of openings formed in the third clamping electrode and through the second dielectric material layer. The first pulse DC voltage is applied to the first bias electrode using the first pulse DC voltage source; as well as The second pulse DC voltage is applied to the second bias electrode using the second pulse DC voltage source.

16. The method of claim 15, wherein Applying the first pulsed DC voltage to the first bias electrode includes: Sequentially disconnecting and closing the switch coupled between the first DC voltage source of the first pulse DC voltage source and the first bias electrode among the plurality of electrodes, and Applying the second pulsed DC voltage to the second bias electrode includes: sequentially opening and closing a switch coupled between a second DC voltage source of the second pulsed DC voltage source and the second bias electrode among the plurality of electrodes.

17. The method of claim 16, wherein the first DC voltage source is configured to provide a negative voltage to the first bias electrode, and the second DC voltage source is configured to provide a negative voltage to the second bias electrode.

18. The method of claim 15, wherein the plasma is formed by coupling an RF power capacitor to a process gas disposed in the process volume.

19. The method of claim 15, wherein the first bias electrode and the second bias electrode are concentrically disposed about the center of the substrate clamping surface of the substrate support.

20. The method of claim 19, wherein the second bias electrode is disposed adjacent to the circumferential edge of the substrate support.

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