Three-dimensional semiconductor structure and preparation method thereof

Abstract

The present application provides a three-dimensional semiconductor structure and a preparation method thereof, which relates to the field of semiconductor technology and is used to solve the technical problems of difficulty and low precision in characterizing the uniformity of the film thickness of the capacitor structure in the existing three-dimensional semiconductor structure. The three-dimensional semiconductor structure includes a substrate, a stacking structure, a contact pad and a test structure. The stacking structure is provided with a plurality of capacitor structures spaced along a second direction, and an isolation wall is provided between adjacent capacitor structures. The capacitor structure includes a first electrode array and a second electrode, and the first electrode array is connected to the substrate, which is further connected to the contact pad in the isolation wall, the contact pad is electrically connected to the first test pad in the test structure, and the second electrode is electrically connected to the second test pad in the test structure. The test structure is used to test the voltage of the capacitor structure. The structure of the present application and the method for characterizing the uniformity of the capacitor film are simple, easy to implement, and can improve the test accuracy of the test structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a three-dimensional semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device, which includes many repeated memory cells. Each memory cell usually includes a transistor and a capacitor, and the gate of the transistor is connected to the word line (WL), the drain is connected to the bit line (BL), and the source is connected to the capacitor.

[0003] With the continuous development of semiconductor chips, their critical dimensions are constantly decreasing, and the thickness of the capacitor film material in the capacitor is getting thinner and thinner. The leakage of the capacitor is exponentially related to the thickness of the capacitor film. A small thickness difference of the capacitor film will lead to a large leakage difference. Therefore, the characterization of the thickness uniformity of the capacitor film is particularly important.

[0004] However, in the related art, there are technical problems such as difficulty in characterizing the uniformity of capacitor film thickness and low test accuracy. Summary of the invention

[0005] In view of the above problems, the embodiments of the present application provide a three-dimensional semiconductor structure and a method for preparing the same, which can reduce the difficulty of characterizing the uniformity of the thickness of the capacitor film and improve the characterization accuracy.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] A first aspect of an embodiment of the present application provides a three-dimensional semiconductor structure, including:

[0008] substrate;

[0009] A stacking structure, the stacking structure is located on the substrate, the stacking structure comprises a plurality of capacitor structures arranged at intervals along a first direction, and an isolation wall is arranged between any two adjacent capacitor structures; the capacitor structure comprises a first electrode array and a plurality of second electrodes, the bottom of the first electrode array is connected to the substrate; the plurality of second electrodes are stacked at intervals along a second direction, and a supporting layer is arranged between any two adjacent second electrodes; wherein the second direction is the thickness direction of the substrate, and the first direction is perpendicular to the second direction;

[0010] A contact pad is disposed in the isolation wall and penetrates the isolation wall along the first direction, and the bottom of the contact pad is connected to the substrate, and the projection of the contact pad along the first direction covers the projection of the capacitor structure in the first direction;

[0011] A test structure is located on the stacked structure, the test structure includes a first test pad and a second test pad, the first test pad is electrically connected to the top of the contact pad, the second test pad is electrically connected to the second electrode, and the test structure is configured to test the voltage of the capacitor structure.

[0012] In some optional embodiments, a first slit is provided on the isolation wall and passes through the isolation wall along the second direction, a width of the first slit along the first direction is smaller than a width of the isolation wall along the first direction, and the contact pad is located in the first slit.

[0013] In some optional embodiments, the contact pad includes a metal conductive layer and a first barrier layer disposed between a sidewall of the first slit and the metal conductive layer.

[0014] In some optional embodiments, the metal conductive layer is a metal tungsten layer; and / or the first barrier layer is a titanium nitride layer.

[0015] In some optional embodiments, the first electrode array includes a plurality of first electrodes arranged in an array, and each of the first electrodes is connected to the substrate.

[0016] In some optional embodiments, a plurality of the first electrodes are arranged in a rectangular array.

[0017] In some optional embodiments, a plurality of contact structures are further included, the contact structures comprising a first contact plug and a plurality of second contact plugs, the first contact plug being electrically connected between the contact pad and the first test pad; and each second contact plug being electrically connected between the second electrode corresponding thereto and the second test pad.

[0018] In some optional embodiments, the stack structure is provided with a plurality of first channels penetrating the stack structure along the second direction, and each of the first electrodes is respectively provided in the first channel corresponding thereto;

[0019] The capacitor structure further includes a dielectric layer, wherein the dielectric layer is located between the first electrode and the inner wall of the first channel;

[0020] The plurality of second electrodes are sequentially stacked and spaced apart in a step-like manner from a direction close to the substrate to a direction far away from the substrate, and each of the second electrodes is connected to the dielectric layer.

[0021] In some optional embodiments, a second blocking layer is further disposed between the dielectric layer and the first electrode; and / or a third blocking layer is further disposed between the second electrode and the support layer.

[0022] In some optional implementations, a plurality of the capacitor structures are arranged in parallel.

[0023] A second aspect of an embodiment of the present application provides a method for preparing a three-dimensional semiconductor structure, comprising:

[0024] providing a substrate;

[0025] A stacking structure is formed on the substrate; the stacking structure comprises a plurality of capacitor structures spaced apart along a first direction, and an isolation wall is provided between any two adjacent capacitor structures; the capacitor structure comprises a first electrode array and a plurality of second electrodes, and the bottom of the first electrode array is connected to the substrate; the plurality of second electrodes are spaced apart and stacked along a second direction, and a supporting layer is provided between any two adjacent second electrodes; wherein the second direction is a thickness direction of the substrate, and the first direction is perpendicular to the second direction;

[0026] forming a contact pad extending along the second direction and penetrating the isolation wall on each isolation wall, so that the contact pad is connected to the substrate; wherein the projection of the contact pad along the first direction covers the projection of the capacitor structure in the first direction;

[0027] A test structure is formed on a surface of the stacked structure facing away from the substrate; the test structure includes a first test pad and a second test pad, the first test pad is electrically connected to the top of the contact pad, the second test pad is electrically connected to the second electrode, and the test structure is configured to test the voltage of the capacitor structure.

[0028] In some optional embodiments, the step of forming a contact pad on the isolation wall extending along the second direction and penetrating the stacked structure specifically includes:

[0029] forming a first slit on the isolation wall extending along a second direction and penetrating the isolation wall;

[0030] A first barrier layer and a metal conductive layer are sequentially formed in the first slit, and the first barrier layer and the metal conductive layer together form a contact pad.

[0031] In some optional embodiments, before the step of forming the stacked structure on the substrate and after the step of providing the substrate, the method further comprises:

[0032] forming a plurality of preset layers stacked on the substrate;

[0033] The plurality of preset layers include supporting layers and sacrificial layers which are alternately stacked in sequence.

[0034] In some optional embodiments, the step of forming a stacked structure on the substrate includes:

[0035] A plurality of first channels arranged in an array are formed in the preset layer; the first channels extend along the second direction and penetrate the preset layer;

[0036] A dielectric layer, a second barrier layer and a first electrode are sequentially formed in the first channel; wherein the second barrier layer is arranged around the outer side wall of the first electrode; and the dielectric layer is located between the second barrier layer and the inner side wall of the first channel;

[0037] Removing the sacrificial layer in the preset layer and forming a second slit;

[0038] A second electrode is formed in the second slit.

[0039] In some optional implementations, before removing the sacrificial layer in the preset layer, the method further includes:

[0040] Removing part of the supporting layer and part of the sacrificial layer on two opposite sides of the preset layer along the third direction to expose the surface of each supporting layer facing away from the substrate, so that the remaining adjacent supporting layers and sacrificial layers are arranged in a step-like manner from close to away from the substrate; the third direction, the second direction and the first direction are perpendicular to each other;

[0041] forming a first oxide layer on the remaining support layer and the sacrificial layer;

[0042] A plurality of third slits spaced apart along the first direction are formed on the first oxide layer, the third slits extend along the second direction and penetrate the preset layer, and the first electrode array and the third slits are sequentially spaced apart along the first direction.

[0043] In some optional implementations, the step of forming the second electrode in the second slit specifically includes:

[0044] sequentially forming a third blocking layer and a second electrode in the second slit through the third slit;

[0045] removing the third barrier layer and the second electrode in the third slit;

[0046] An isolation material is filled in the third slit to form an isolation wall.

[0047] In some optional implementations, the step of forming a test structure on a surface of the stacked structure facing away from the substrate specifically includes:

[0048] forming a second oxide layer on the stacked structure;

[0049] forming a second channel and a plurality of third channels on the second oxide layer, wherein the second channel exposes the contact pad, and the third channel exposes the surface of the second electrode; wherein one third channel corresponds to one second electrode;

[0050] Depositing a conductive material on the second oxide layer, the conductive material filling the second trench and the third trench while covering the surface of the second oxide layer; the conductive material filled in the second trench forms a first contact plug, and the conductive material filled in the third trench forms a second contact plug;

[0051] The conductive material partially covering the surface of the second oxide layer is removed, and the conductive material covering the first contact plug and the second contact plug is retained; wherein the conductive material covering the first contact plug is formed into a first test pad; the conductive material covering the second contact plug is formed into a second test pad; the first test pad and the second test pad form the test structure.

[0052] In the three-dimensional semiconductor structure and its preparation method provided in the embodiment of the present application, the first electrode array in the capacitor structure is connected to the substrate, and the substrate is further connected to the outside of the stacked structure through the contact pad, so that the contact pad is electrically connected to the first test pad in the test structure, and the multiple second electrodes in the capacitor structure are respectively electrically connected to the corresponding second test pads in the test structure. In this way, the test structure can test the voltage at different positions of the capacitor structure, and determine the leakage current at different positions of the capacitor structure according to the acquired voltage, so that the uniformity of the film thickness in the capacitor can be characterized by the size of the leakage current at different positions of the capacitor structure. The structure and characterization method are simple and easy to implement. In addition, by connecting the first electrode array to the substrate, and the substrate is further connected to the first test pad through the contact pad, the signal of the leakage current can be amplified, thereby providing the test accuracy of the test structure.

[0053] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the three-dimensional semiconductor structure and the preparation method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0055] Figure 1 A schematic diagram of a half-section structure of a three-dimensional semiconductor structure provided in one embodiment of the present application;

[0056] Figure 2 for Figure 1 A local enlarged schematic diagram of the middle A;

[0057] Figure 3 A schematic diagram of a process for preparing a three-dimensional semiconductor structure provided in one embodiment of the present application;

[0058] Figure 4 A schematic flow chart of step S103 in the method for preparing a three-dimensional semiconductor structure provided in one embodiment of the present application;

[0059] Figures 5 to 18 A schematic diagram of a preparation process of a three-dimensional semiconductor structure provided in one embodiment of the present application.

[0060] Reference numerals:

[0061] 100-three-dimensional semiconductor structure; 10-substrate; 20-stacked structure; 21-capacitor structure;

[0062] 211-first electrode array; 2111-first electrode; 212-second electrode;

[0063] 22-preset layer; 221-support layer; 222-sacrificial layer; 223-first slit; 224-third slit;

[0064] 23 - first channel; 24 - metal conductive layer; 241 - contact pad;

[0065] 25-contact structure; 251-first contact plug;

[0066] 252 - second contact plug; 26 - first oxide layer; 27 - second oxide layer;

[0067] 28 - second channel; 29 - third channel; 30 - test structure; 301 - first test pad;

[0068] 302 - second test pad; 31 - isolation wall; 40 - first mask layer; 41 - second mask layer;

[0069] 42 - a third mask layer; 43 - a fourth mask layer; 50 - an insulating layer. DETAILED DESCRIPTION

[0070] As described in the background technology, in the related art, the uniformity of the film thickness at the top and bottom of the capacitor structure is usually analyzed by means of a transmission electron microscope, however, as the critical dimensions of semiconductor structures continue to decrease, the thickness of DRAM capacitor film materials is very thin, resulting in great difficulty in characterizing the uniformity of the thickness of the films at the top and bottom of the capacitor structure by means of a transmission electron microscope, resulting in a technical problem of low characterization accuracy.

[0071] In view of this, an embodiment of the present application provides a three-dimensional semiconductor structure and a preparation method thereof, by connecting the first electrode array in the capacitor structure to the substrate, and the substrate is further connected to the outside of the stacked structure through the contact pad, so that the contact pad is electrically connected to the first test pad in the test structure, and the multiple second electrodes in the capacitor structure are respectively electrically connected to the corresponding second test pads in the test structure. In this way, the test structure can test the voltage at different positions of the capacitor structure, and determine the leakage current at different positions of the capacitor structure according to the acquired voltage, so that the uniformity of the film thickness in the capacitor can be characterized by the size of the leakage current at different positions of the capacitor structure. The structure and characterization method are simple and easy to implement. In addition, by connecting the first electrode array to the substrate, and the substrate is further connected to the first test pad through the contact pad, the signal of the leakage current can be amplified, thereby providing the test accuracy of the test structure.

[0072] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of this application.

[0073] Embodiment 1

[0074] The embodiment of the present application provides a three-dimensional semiconductor structure, which can be a memory device or a non-memory device. The memory device may include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), or a magnetoresistive random access memory (MRAM). The non-memory device may be a logic device (such as a microprocessor, a digital signal processor, or a microcontroller) or a device similar thereto. The embodiment of the present application is described by taking a DRAM memory device as an example.

[0075] Figure 1 A schematic diagram of a half-section structure of a three-dimensional semiconductor structure provided in an embodiment of the present application; Figure 2 for Figure 1 A local enlarged schematic diagram of point A in the middle. Figure 1 A schematic diagram of the structure of a three-dimensional semiconductor structure provided in an embodiment of the present application; Figure 2 This is a partial cross-sectional diagram of a three-dimensional semiconductor structure provided in an embodiment of the present application. Figure 1 and Figure 2 As shown, the three-dimensional semiconductor structure 100 includes a substrate 10 .

[0076] The substrate 10 may provide a support foundation for the structure on the substrate 10. The substrate 10 may be made of a doped crystalline semiconductor material and have conductive properties, such as a doped silicon (Si) substrate. The substrate 10 may also be a doped silicon germanium (SiGe) substrate or a doped silicon carbide (SiC) substrate. The substrate 10 may be a single-layer structure or a multi-layer composite structure. The substrate 10 may be adaptively designed according to actual needs, and no specific limitation is made here. In the embodiment of the present application, the substrate 10 includes a doped silicon substrate as an example for introduction.

[0077] In some embodiments, a stacked structure 20 is disposed on the substrate 10, and the stacked structure 20 includes a plurality of capacitor structures 21 spaced apart along a first direction, and an isolation wall 31 is disposed between any two adjacent capacitor structures 21, and the isolation wall 31 is used to electrically isolate the two adjacent capacitor structures 21 to avoid signal interference between adjacent capacitor structures 21. The first direction may be, for example, perpendicular to the thickness direction of the substrate 10, for example, in a three-dimensional coordinate system, if the thickness direction of the substrate 10 is along the Z direction, then the first direction may be the X direction or the Y direction.

[0078] In an embodiment of the present application, the capacitor structure 21 includes a first electrode array 211 and a plurality of second electrodes 212, wherein the first electrode array 211 includes a plurality of first electrodes 2111 arranged in an array, for example, the plurality of first electrodes 2111 are arranged in a rectangular array; alternatively, the plurality of first electrodes 2111 may also be arranged in any shape such as a circle or an ellipse, and the embodiment of the present application does not impose any specific limitation on this.

[0079] Among them, the first electrode array 211 is connected to the substrate 10, that is, each first electrode 2111 in the first electrode array 211 is connected to the substrate 10; and a plurality of second electrodes 212 are stacked and arranged at intervals along the second direction, and a support layer 221 is arranged between any two adjacent second electrodes 212; by arranging the support layer 221 between two adjacent second electrodes 212, electrical isolation between adjacent second electrodes 212 is achieved through the support layer 221, so as to avoid mutual interference of signals between two adjacent second electrodes 212; wherein, the second direction can be the thickness direction of the substrate 10, and the second direction is perpendicular to the first direction. Exemplarily, the second direction can be the Z direction.

[0080] It can be understood that the multiple first electrodes 2111 in the first electrode array 211 extend along the second direction. Exemplarily, each first electrode 2111 is arranged in a columnar shape on the substrate 10, and the multiple second electrodes 212 are arranged at different heights of the first electrode 2111 at intervals along the second direction, and a dielectric layer (not shown in the figure) is arranged between the first electrode 2111 and the second electrode 212. The dielectric layer can be understood as a thin film structure in the capacitor structure 21, wherein the material of the dielectric layer may include but is not limited to aluminum oxide, zirconium oxide, etc.

[0081] Since the first electrode array 211 includes a plurality of first electrodes 2111 arranged in an array, and a plurality of second electrodes 212 are stacked and spaced at different heights of the first electrodes 2111 along the extension direction of each first electrode 2111, that is, each first electrode 2111 can be understood as a common electrode. In this way, each first electrode 2111, a plurality of second electrodes 212 and a dielectric layer between the first electrode 2111 and the second electrode 212 together form a capacitor structure 21, so as to simulate and test the performance of the parallel capacitor, and the leakage signal of the capacitor structure 21 can be amplified.

[0082] Please continue to refer to Figure 1 and Figure 2 The three-dimensional semiconductor structure 100 provided in the embodiment of the present application also includes a contact pad 241 and a test structure 30, the contact pad 241 is arranged in the isolation wall 31, and the contact pad 241 passes through the isolation wall 31 along the first direction and is connected to the substrate 10, for example, the contact pad 241 is connected to the substrate 10 at the bottom along the second direction, wherein the projection of the contact pad 241 along the first direction can cover the projection of the capacitor structure 21 in the first direction to increase the coverage area of ​​the contact pad 241, thereby being able to further amplify the signal of the leakage current of the capacitor structure 21 during charging and discharging, so as to improve the test accuracy of the test structure 30.

[0083] In addition, by providing the contact pad 241, each first electrode 2111 in the first electrode array 211 is connected to the substrate 10, and the substrate 10 is led out through the contact pad 241 to achieve electrical connection with the test structure 30. In this way, there is no need to prepare a contact plug, for example, for each first electrode 2111 to be electrically connected to the test structure 30, thereby simplifying the preparation process, making the critical dimension of the contact pad 241 wider, and being able to reduce the preparation cost.

[0084] Among them, the test structure 30 can be located on the stacked structure 20, and the test structure 30 includes a first test pad 301 and a second test pad 302. The first test pad 301 is electrically connected to the contact pad 241. For example, the first test pad 301 is located on the stacked structure 20, and the top of the contact pad 241 is electrically connected to the first test pad 301; the second test pad 302 is electrically connected to the second electrode 212, so as to test the voltage of the capacitor structure 21 through the test structure 30, so as to determine the leakage current conditions at different positions of the capacitor structure 21 according to the tested voltage conditions, and then characterize the thickness uniformity of the thin film structure in the capacitor structure 21 according to the leakage current conditions of the capacitor structure 21. The structure and characterization method are simple and easy to implement.

[0085] In a specific implementation, a ground voltage can be applied to the first test pad 301 electrically connected to the first electrode 2111, and a test voltage can be applied to each second test pad 302 electrically connected to each second electrode 212, so that each capacitor structure 21 is charged; then the actual voltage value between the first electrode 2111 and each second electrode 212 is obtained through the first test pad 301 and each second test pad 302, and the actual voltage value obtained is compared with the preset voltage value previously preset. If there is a voltage difference between the detected actual voltage value and the preset voltage value, it means that the capacitor structure 21 has a leakage condition, and the magnitude of the voltage difference can characterize the magnitude of the leakage at different height positions of the capacitor structure 21. Since the magnitude of the leakage of the capacitor structure 21 is exponentially related to the film thickness of the capacitor structure 21, the thickness uniformity of the capacitor structure 21 at different height positions can be characterized by the leakage magnitude at different height positions of the capacitor structure 21. The structure is simple and easy to implement, thereby reducing the difficulty of characterizing the uniformity of the film thickness of the capacitor structure 21.

[0086] It can be seen that in the above scheme, by connecting the first electrode array 211 in the capacitor structure 21 to the substrate 10, and the substrate 10 is further connected to the outside of the stacked structure 20 through the contact pad 241, so that the contact pad 241 is electrically connected to the first test pad 301 in the test structure 30, and the plurality of second electrodes 212 in the capacitor structure 21 are respectively electrically connected to the corresponding second test pads 302 in the test structure 30. In this way, the test structure 30 can test the voltages at different positions of the capacitor structure 21, and determine the different positions of the capacitor structure 21 according to the obtained voltages. The leakage current of the capacitor structure 21 is measured so that the uniformity of the film thickness in the capacitor can be characterized by the size of the leakage current at different positions of the capacitor structure 21. The structure and characterization method are simple and easy to implement. In addition, by connecting each first electrode 2111 in the first electrode array 211 to the substrate 10, the substrate 10 is connected to the contact pad 241, and the contact pad 241 is further connected to the first test pad 301, the capacitor structure 21 can be charged and discharged. In this way, the leakage current signal in the capacitor structure 21 can be amplified, thereby improving the test accuracy of the test structure 30.

[0087] In some embodiments, a first slit is disposed on the isolation wall 31 and penetrates the isolation wall 31 along the second direction. The width of the first slit along the first direction is smaller than the width of the isolation wall 31 along the first direction. The contact pad 241 is located in the first slit.

[0088] It can be understood that an opening is provided at the top of the isolation wall 31 , and the opening passes through the isolation wall 31 to expose the surface of the substrate 10 . The opening passing through the isolation wall 31 is formed as a first slit, and the contact pad 241 is located in the first slit to achieve connection with the substrate 10 .

[0089] In some embodiments, the contact pad 241 includes a metal conductive layer and a first barrier layer arranged between the side wall of the first slit and the metal conductive layer. That is, the metal conductive layer is located in the first slit. In order to avoid ion diffusion between the metal conductive layer and the isolation wall 31, the first barrier layer is arranged between the metal conductive layer and the side wall of the first slit to prevent ion diffusion between the metal conductive layer and the isolation wall 31 through the first barrier layer.

[0090] Exemplarily, the metal conductive layer can be a material with low resistance such as W, TiN, TaN, Al, Ru or Cu, for example, the metal conductive layer is a metal tungsten (W) layer; and the first barrier layer can include but is not limited to a titanium nitride layer or a titanium layer.

[0091] Please continue to refer to Figure 1 and Figure 2 The three-dimensional semiconductor structure 100 provided in the embodiment of the present application also includes a contact structure 25, the contact structure 25 includes a first contact plug 251 and a plurality of second contact plugs 252, the first contact plug 251 is electrically connected between the contact pad 241 and the first test pad 301, and each second contact plug 252 is electrically connected between the corresponding second electrode 212 and the second test pad 302, wherein an isolation structure is arranged between any two adjacent second contact plugs 252 to achieve electrical isolation between the two adjacent second contact plugs 252 through the isolation structure.

[0092] In the above scheme, the first test pad 301 is connected to the contact pad 241 through the first contact plug 251, the contact pad 241 is connected to the substrate 10, and the substrate 10 is further connected to each first electrode 2111 in the first electrode array 211. It is not necessary to set a first contact plug 251 for each first electrode 2111, thereby simplifying the preparation process and reducing the preparation cost; at the same time, the second test pad 302 is electrically connected to the corresponding second electrode 212 through multiple second contact plugs 252, so as to realize the characterization of the thickness uniformity of the thin film structure in the capacitor structure 21 through the test structure 30. The structure and characterization method are simple and easy to implement.

[0093] Please continue to refer to Figure 1 and Figure 2 , each second contact plug 252 and the second contact plug 252 can extend along the first direction, so that each second contact plug 252 is vertically connected to the corresponding second electrode 212; the first contact plug 251 is connected to the top of the contact pad 241. In this way, by respectively extending the first contact plug 251 and the second contact plug 252 along the first direction, the space occupied by the contact structure 25 in the stacked structure can be reduced, the space utilization rate is improved, the volume is reduced, and it is beneficial to increase the number of arrangements of the capacitor structure 21, thereby simulating the test performance of the simulated parallel capacitor.

[0094] In some embodiments, a plurality of first channels 23 penetrating the stacked structure 20 along the second direction may be provided on the stacked structure 20, and each first electrode 2111 is respectively provided in the first channel 23 corresponding thereto to form at least one first electrode array 211, and the dielectric layer may be located between the first electrode 2111 and the inner wall of the first channel 23.

[0095] It can be understood that the dielectric layer is a thin film structure formed on the inner wall of the first channel 23, and then the first electrode 2111 is filled in the first channel 23 having the dielectric layer, so that the dielectric layer is wrapped around the outer wall of the first electrode 2111. In this way, the arrangement between the first electrode 2111 and the dielectric layer can be better, and the volume of the capacitor structure 21 can be smaller, which is conducive to improving space utilization.

[0096] In some embodiments, a second barrier layer may be further disposed between the dielectric layer and the first electrode 2111 , wherein the material of the second barrier layer may include but is not limited to titanium or titanium nitride, and the second barrier layer may prevent ion diffusion from occurring in the first electrode 2111 .

[0097] In some embodiments, a second barrier layer may be disposed between the second electrode 212 and the support layer 221 to prevent ion diffusion between the second electrode 212 and the support layer 221. The material of the second barrier layer may include but is not limited to titanium or titanium nitride.

[0098] In some embodiments, the edges of the plurality of second electrodes 212 are arranged in a stepped manner from close to the substrate 10 to far away from the substrate 10 (eg, Figure 1 and Figure 2 ), and each second electrode 212 is connected to its corresponding dielectric layer.

[0099] For example, the edges of the plurality of second electrodes 212 are sequentially stepped from bottom to top along the second direction. Therefore, the distance between the connection point of each second electrode 212 and its corresponding second contact plug 252 and the first electrode 2111 decreases sequentially.

[0100] It can be understood that by arranging the edges of the plurality of second electrodes 212 in a stepped manner, on the one hand, each second electrode 212 can be exposed while preventing each second contact plug 252 from being electrically connected to the corresponding second electrode 212 and from being electrically connected to other second electrodes 212, thereby improving the connection reliability of the electrical connection between the second contact plug 252 and the corresponding second electrode 212; on the other hand, the space occupied by the plurality of second electrodes 212 can be reduced, which is beneficial to reducing the characteristic size of the three-dimensional semiconductor structure 100.

[0101] In some embodiments, there may be multiple capacitor structures 21, and the multiple capacitor structures 21 are arranged at intervals in the stacked structure 20 along, for example, a first direction, and isolation walls 31 are arranged between adjacent capacitor structures 21, and the adjacent capacitor structures 21 are electrically isolated by the isolation walls 31.

[0102] The second direction is perpendicular to the first direction. For example, in a three-dimensional coordinate system, the first direction may be the Y direction, and the second direction may be the Z direction. Figure 1 and Figure 2 In the embodiment, a plurality of capacitor structures 21 are arranged at intervals along the Y direction. Of course, the first direction may also be a direction having an inclined angle with the X direction or the Y direction, and the adaptive design is performed according to actual needs.

[0103] It can be understood that multiple capacitor structures 21 are arranged at intervals along the first direction in the stacked structure 20. This arrangement can make the arrangement of the capacitor structures 21 more compact, so that the arrangement form of the multiple capacitor structures 21 in the stacked structure 20 is better, and the volume they occupy is smaller, which is conducive to increasing the number of arranged capacitor structures 21, thereby improving the storage density of the three-dimensional semiconductor structure 100.

[0104] In some embodiments, Figure 1 and Figure 2 As shown, multiple capacitor structures 21 are arranged in parallel along the Y direction. It can be understood that since the leakage difference between the two ends of a single capacitor structure 21 in the first direction is small, if the signal collected by a single capacitor structure 21 is represented by i, by arranging multiple capacitor structures 21 in parallel, for example, N capacitor structures 21 are arranged in parallel, then the total collected signal (represented by I) is: I=Nxi, thereby maximizing the resolution.

[0105] Embodiment 2

[0106] An embodiment of the present application provides a method for preparing a three-dimensional semiconductor structure. The method for preparing a three-dimensional semiconductor structure can be used to prepare the three-dimensional semiconductor structure 100 in the above embodiment.

[0107] Figure 3 This is a schematic diagram of a process for preparing a three-dimensional semiconductor structure provided in an embodiment of the present application. Figure 3 As shown, the method for preparing the three-dimensional semiconductor structure includes:

[0108] Step S101: providing a substrate.

[0109] Combination Figure 5 As shown, in the embodiment of the present application, the substrate 10 includes a silicon substrate and an oxide layer formed on the silicon substrate, and the silicon substrate is insulated and protected by the oxide layer.

[0110] Step S102: forming a plurality of preset layers stacked on a substrate.

[0111] Specifically, a plurality of stacked preset layers 22 may be sequentially formed on the substrate 10 by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process, wherein the plurality of preset layers 22 include a support layer 221 and a sacrificial layer 222 alternately stacked in sequence along a first direction, and the preset layer 22 close to the substrate 10 may be, for example, a sacrificial layer 222, such as Figure 5 As shown in FIG. 1 , a plurality of preset layers 22 are arranged on the substrate 10 , so that a stacked structure 20 is formed on the preset layers 22 in a subsequent process.

[0112] In some embodiments, the material of the sacrificial layer 222 can be silicon nitride (SIN) and the material of the supporting layer 221 can be an insulating material such as oxide, so as to achieve electrical isolation between adjacent second electrodes 212 in the stacked structure 20 formed by subsequent processes through the supporting layer 221 to avoid mutual interference of signals between adjacent second electrodes 212.

[0113] Step S103: forming a stacking structure on the substrate.

[0114] Among them, the stacked structure 20 includes a plurality of capacitor structures 21 arranged at intervals along a first direction, and an isolation wall 31 is arranged between any two adjacent capacitor structures 21; the capacitor structure 21 includes a first electrode array 211 and a plurality of second electrodes 212, the bottom of the first electrode array 211 is connected to the substrate 10, the plurality of second electrodes 212 are stacked and arranged at intervals along a second direction, and a support layer 221 is arranged between any two adjacent second electrodes 212; wherein the second direction is the thickness direction of the substrate 10, and the first direction and the second direction are perpendicular to each other.

[0115] It can be understood that the first electrode array 211 includes a plurality of first electrodes 2111 arranged in an array, and each first electrode 2111 in the first electrode array 211 is connected to the substrate 10 .

[0116] Figure 4 This is a flow chart of step S103 in the method for preparing a three-dimensional semiconductor structure provided in one embodiment of the present application. Figure 4 As shown, the step of forming the stacked structure 20 on the substrate 10 specifically includes:

[0117] Step S1031: forming a plurality of first channels arranged in an array in a preset layer; the first channels extend along the second direction and penetrate the preset layer.

[0118] For details, please refer to Figure 6 As shown, a first mask layer 40 is first formed on the preset layer 22, and the first mask layer 40 is patterned by exposure, development, etc., and a portion of the preset layer 22 is etched using the patterned first mask layer 40 as a mask, so that a plurality of first channels 23 penetrating the preset layer 22 and arranged in an array are formed on the preset layer 22, so that the first channels 23 expose the substrate 10 (for example, penetrating the oxide layer to expose the silicon substrate located under the oxide layer); a first electrode 2111 can be formed in each first channel 23 in a subsequent process, so that each first electrode 2111 is connected to the substrate 10, thereby realizing that the first electrode array 211 formed by the plurality of first electrodes 2111 is connected to the substrate 10.

[0119] The cross-sectional shape of the first channel 23 may be circular, elliptical, rectangular or square.

[0120] like Figure 7 As shown, after the first trench 23 is formed, the first mask layer 40 is removed to expose the surface of the top preset layer 22 .

[0121] Step S1032: forming a dielectric layer, a second barrier layer and a first electrode in sequence in the first channel; wherein the second barrier layer is arranged around the outer side wall of the first electrode, and the dielectric layer is located between the second barrier layer and the inner side wall of the first channel.

[0122] For details, please continue to refer to Figure 7 After removing the first mask layer 40 on the surface of the preset layer 22 , a thin film structure can be formed on the preset layer 22 by a chemical deposition process or a physical deposition process, and the thin film structure covers the inner wall of the first channel 23 .

[0123] After the thin film structure is formed on the inner wall of the first trench 23, the thin film structure on the surface of the preset layer 22 can be removed by chemical mechanical polishing (CMP) or etching, and the surface of the preset layer 22 is exposed, and the thin film structure covering the inner wall of the first trench 23 is retained to form a dielectric layer of the capacitor structure 21.

[0124] The material of the dielectric layer may be a high-K gate dielectric material, which may include nitrides, metal oxides, etc., such as SI3N4, SION, etc. By setting the dielectric layer to be made of a high-K gate dielectric material, the electron tunneling effect can be effectively suppressed, thereby reducing the leakage of the capacitor structure 21. It can be understood that K is a dielectric constant.

[0125] In some embodiments, after a dielectric layer is formed on the inner wall of each first channel 23, a second barrier layer is formed on the preset layer 22 by a chemical vapor deposition process or a physical vapor deposition process, and the second barrier layer is attached to the surface of the dielectric layer, wherein the second barrier layer can be a titanium layer or a titanium nitride layer.

[0126] After forming a dielectric layer on the inner wall of each first trench 23, a conductive material may be deposited on the preset layer 22 by a chemical deposition process or a physical deposition process so that the conductive material fills the first trench 23, so that the conductive material filled in the first trench 23 forms a first electrode layer.

[0127] The first electrode layer may be formed of a material such as a metal having conductive properties. For example, the material of the first electrode layer may be a material with low resistance such as W, TiN, TaN, Al, Ru or Cu.

[0128] After the first electrode layer fills the first trench 23, the first electrode layer on the surface of the preset layer 22 can be removed by chemical mechanical polishing (CMP) or etching, and the surface of the preset layer 22 is exposed, and the first electrode layer in the first trench 23 is retained. The first electrode layer retained in the first trench 23 is formed into a first electrode 2111 of the capacitor structure 21, such as Figure 1 and Figure 2 As shown in , the second barrier layer is wrapped on the outer side wall of the first electrode 2111 , and the dielectric layer is wrapped on the outer side wall of the second barrier layer, so that the dielectric layer is located between the outer side wall of the second barrier layer and the inner wall of the first channel 23 .

[0129] In some embodiments, after the dielectric layer, the second barrier layer and the first electrode 2111 are sequentially formed in the first channel 23, a mask block is formed on the preset layer 22, and the mask block is used as a mask to remove part of the support layer 221 and the sacrificial layer 222 on two opposite sides of the preset layer 22 along the third direction to expose the surface of each support layer 221 facing away from the substrate 10, and the above process is repeated to make the retained adjacent support layers 221 and sacrificial layers arranged in a step-like manner from close to away from the substrate 10 (such as along the second direction), such as Figure 8 As shown in ; wherein the third direction, the second direction and the first direction are perpendicular to each other. For example, in an embodiment of the present application, the first direction may be the Y direction, the second direction may be the Z direction, and the third direction may be the X direction.

[0130] Afterwards, a first oxide layer 26 is formed on the retained support layer 221 and the sacrificial layer 222, the side walls of the first oxide layer 26 are flush with the side walls of the substrate 10, and the upper surface of the first oxide layer 26 covers the upper surface of the preset layer 22; wherein the material of the first oxide layer 26 may include but is not limited to silicon oxide, silicon dioxide, etc.

[0131] Step S1033: removing the sacrificial layer in the preset layer and forming a second slit.

[0132] Among them, before forming the second slits, after forming the first oxide layer 26 on the retained support layer 221 and the sacrificial layer 222, it also includes forming a plurality of third slits 224 spaced apart along the first direction on the first oxide layer 26, the third slits 224 extending along the second direction and penetrating the preset layer 22, and the first electrode array 211 and the third slits 224 are arranged in sequence along the first direction.

[0133] Specifically, a portion of the preset layer 22 is removed to form Figure 8 After the structure in FIG. 1 is formed, a first oxide layer 26 is formed on the reserved preset layer 22, and a second mask layer 41 is formed on the first oxide layer 26, and the second mask layer 41 is patterned by exposure, development, etc., such as Fig. 9 As shown in FIG, the patterned second mask layer 41 is used as a mask, and a portion of the preset layer 22 is removed by a wet etching process or a dry etching process, and the area where the preset layer 22 is removed is formed into a third slit 224 (as shown in FIG. Fig.10 ), wherein the third slit 224 extends along the second direction and exposes the substrate 10.

[0134] After a portion of the preset layer 22 is removed to form the third slit 224, each sacrificial layer 222 in the preset layer 22 is removed through the third slit 224 to form a second slit, and then the second mask layer 41 is removed to expose the surface of the preset layer 22. Fig.10 as shown in .

[0135] Specifically, each sacrificial layer 222 in the preset layer 22 may be removed through the third slit 224 by wet etching or other processes, and the supporting layer 221 in the preset layer 22 may be retained, so that a second slit is formed between adjacent supporting layers 221 .

[0136] Step S1034: forming a second electrode in the second slit.

[0137] Combination Fig.11As shown, after the second slit is formed between adjacent supporting layers 221, the third blocking layer and the second electrode 212 are sequentially formed through the third slit 224 into the second slit by chemical vapor deposition process, physical vapor deposition process, etc., so that the third blocking layer and the second electrode 212 fill the second slit in sequence, and the third blocking layer is wrapped around the outer wall of the second electrode 212.

[0138] After the third barrier layer and the second electrode 212 are filled in the second slit in sequence, the third barrier layer and the second electrode 212 in the third slit 224 can be removed by an etching process, that is, the third slit 224 is etched back so that the third slit 224 exposes the substrate 10. Fig.12 As shown in , thereafter, an isolation material is filled into the third slit 224 to form an isolation wall 31 . It can be understood that the isolation wall 31 is used to achieve electrical isolation between adjacent capacitor structures 21 .

[0139] Please refer to Fig.13 As shown, after the isolation material is filled in the third slit 224 to form the isolation wall 31, a portion of the first oxide layer 26 is removed to expose the surface of the first electrode array 211 facing away from the substrate 10; wherein, after removing a portion of the first oxide layer 26, the surface of the retained first oxide layer 26 facing away from the substrate 10 is a flat surface.

[0140] Step S104: forming contact pads on each isolation wall, the contact pads extending along the second direction and penetrating the isolation wall, so that the contact pads are connected to the substrate.

[0141] The projection of the contact pad 241 along the first direction covers the projection of the capacitor structure 21 in the first direction to increase the area of ​​the contact pad 241 , thereby further amplifying the leakage current signal of the capacitor structure 21 during charging and discharging, so as to improve the test accuracy of the test structure 30 .

[0142] After forming the isolation wall 31 in the third slit 224 and removing a portion of the first oxide layer 26, an insulating layer 50 may be formed on the surface of the remaining first oxide layer 26, such as Fig.14 As shown in , the projection of the insulating layer 50 on the substrate 10 covers the projection of each capacitor structure 21 on the substrate 10 to achieve electrical isolation between the first electrode array 211 in the capacitor structure 21 and external devices.

[0143] The insulating layer 50 may include but is not limited to insulating materials such as silicon nitride, and no specific limitation is made here.

[0144] After forming the insulating layer 50 on the first oxide layer 26, a patterned third mask layer 42 is formed on the insulating layer 50, and the patterned third mask layer 42 is used as a mask to form a first slit 223 extending along the second direction and penetrating the isolation wall 31 on the isolation wall 31, such as Fig.14 as shown in .

[0145] It can be understood that the first slit 223 is disposed in the isolation wall 31, and the projection of the first slit 223 on the substrate 10 is smaller than the projection of the isolation wall 31 on the substrate 10. Exemplarily, the symmetric center plane of the first slit 223 in the first direction coincides with the symmetric center plane of the isolation wall 31 in the first direction. In this way, the isolation wall 31 is retained on opposite sides of the first slit 223 in the first direction. Figure 2 As shown in FIG. 1 , the electrical isolation between adjacent capacitor structures 21 is achieved by the reserved isolation wall 31 .

[0146] There may be a plurality of first slits 223 , and the plurality of first slits 223 are arranged at intervals along the first direction. Exemplarily, one first slit 223 corresponds to one capacitor structure 21 .

[0147] After forming the first slit 223 using the third mask layer 42 as a mask, the third mask layer 42 is removed to expose the surface of the insulating layer 50, and a first barrier layer and a metal conductive layer 24 are sequentially deposited in the first slit 223. Fig.15 as shown in .

[0148] Afterwards, the first barrier layer and the metal conductive layer 24 deposited on the surface of the insulating layer 50 are removed to expose the surface of the insulating layer 50, such as Fig.16 As shown in FIG. 2 , the first barrier layer and the metal conductive layer 24 remaining in the first slit 223 are jointly formed into a contact pad 241 , wherein the first barrier layer is wrapped around the outer wall of the metal conductive layer 24 .

[0149] It should be noted that the contact pad 241 is connected to the substrate 10 . Exemplarily, the substrate 10 includes a silicon substrate and an oxide layer located on the silicon substrate, and the contact pad 241 is connected to the silicon substrate.

[0150] Step S105: forming a test structure on a surface of the stack structure facing away from the substrate.

[0151] The test structure 30 includes a first test pad 301 and a second test pad 302 . The first test pad 301 is electrically connected to the top of the contact pad 241 , and the second test pad 302 is electrically connected to its corresponding second electrode 212 . The test structure 30 is used to test the voltage of the capacitor structure 21 .

[0152] In some embodiments, forming the test structure 30 on the stack structure 20 specifically includes:

[0153] Please refer to Fig.17 As shown, after the contact pad 241 is formed in the first slit 223, a second oxide layer 27 covering the insulating layer 50 and the contact pad 241 is formed on the insulating layer 50, and the surface of the second oxide layer 27 facing away from the substrate 10 is a flat surface, and a fourth mask layer 43 is formed on the second oxide layer 27, the fourth mask layer 43 is patterned, and a portion of the second oxide layer 27 is removed using the patterned fourth mask layer 43 as a mask to form a second channel 28 exposing the top of the contact pad 241 and a third channel 29 exposing the second electrode 212. It can be understood that the second channel 28 and the third channel 29 both extend along the second direction. In this way, the space can be reasonably utilized, which is beneficial to reducing the characteristic size of the three-dimensional semiconductor structure 100 while improving the storage density of the three-dimensional semiconductor structure 100.

[0154] It can be understood that the second oxide layer 27 retained between two adjacent third channels 29 forms an isolation structure, and the isolation structure can be used to electrically isolate two adjacent second contact plugs 252 formed in a subsequent process.

[0155] The cross-sectional shapes of the second channel 28 and the third channel 29 may be any shapes such as circular, elliptical, rectangular, square, etc.

[0156] Combination Fig.18 As shown, after the second channel 28 and the third channel 29 are formed on the second oxide layer 27, the fourth mask layer 43 is removed to expose the surface of the second oxide layer 27, and a conductive material is deposited on the second oxide layer 27. The conductive material fills the second channel 28 and the third channel 29 and covers the surface of the second oxide layer 27. In this way, the conductive material filled in the second channel 28 is formed as a first contact plug 251, and the conductive material filled in the third channel 29 is formed as a second contact plug 252.

[0157] The conductive material formed on the surface of the second oxide layer 27 covers the entire surface of the second oxide layer 27. Afterwards, a patterned fifth mask layer is formed on the conductive material on the surface of the second oxide layer 27, and the fifth mask layer is used as a mask to remove part of the conductive material, and retain the conductive material covering the first contact plug 251 and the second contact plug 252, wherein the conductive material covering the first contact plug 251 is formed as a first test pad 301; the conductive material covering the second contact plug 252 is formed as a second test pad 302. It can be understood that the first test pad 301 and the second test pad 302 are independent structures, and the second test pad 302 formed is multiple, and the multiple second test pads 302 are also independent structures. In this way, the first test pad 301 and the second test pad 302 form a test structure 30, such as Figure 1 and Figure 2 as shown in .

[0158] Exemplarily, the first test pad 301 can be a strip structure extending along the first direction, the second test pad 302 can also be a strip structure extending along the first direction, and the second test pad 302 can be multiple, and the multiple second test pads 302 can be arranged at intervals along a third direction, wherein the third direction is perpendicular to the first direction and the second direction respectively.

[0159] In the above solution, the test structure 30 and the first contact plug 251 and the second contact plug 252 can be formed by an integrated molding process, so that the manufacturing process can be reduced, thereby reducing the manufacturing cost.

[0160] It can be understood that the material of the test structure 30 and the first contact plug 251 and the second contact plug 252 can be a material with low resistance such as W, TiN, TaN, Al, Ru or Cu; of course, the materials of the test structure 30, the first contact plug 251 and the second contact plug 252 can be the same or different. In the embodiment of the present application, the material of the test structure 30, the first contact plug 251 and the second contact plug 252 is the same and is formed by an integrated molding process, thereby reducing the preparation process.

[0161] That is to say, the first contact plug 251 electrically connected to the contact pad 241 in each capacitor structure 21 is an integral structure with the first test pad 301, and the second contact plugs 252 electrically connected to the second electrodes 212 corresponding to the same height position in each capacitor structure 21 are an integral structure with the corresponding second test pad 302. In this way, the preparation process can be reduced, thereby reducing the preparation cost.

[0162] When characterizing the uniformity of the film thickness in each capacitor structure 21, first, a ground voltage is applied to the first test pad 301, and a test voltage is applied to each second test pad 302 to charge each capacitor structure 21, and then the actual voltage value of the first electrode 2111 and each second electrode 212 is obtained through the first test pad 301 and each second test pad 302, and the actual voltage value obtained is compared with the preset voltage value. If there is a voltage difference between the actual voltage value and the preset voltage value, it means that the capacitor structure 21 has a leakage condition, and the magnitude of the voltage difference can characterize the magnitude of the leakage at different height positions of the capacitor structure 21. Since the magnitude of the leakage of the capacitor structure 21 is exponentially related to the thickness of the film of the capacitor structure 21, the uniformity of the thickness of the film of the capacitor structure 21 at different height positions can be characterized by the magnitude of the leakage at different height positions of the capacitor structure 21. The structure is simple and easy to implement, thereby reducing the difficulty of characterizing the uniformity of the film thickness of the capacitor structure 21.

[0163] In the three-dimensional semiconductor structure and its preparation method provided in the embodiment of the present application, the first electrode array in the capacitor structure is connected to the substrate, and the substrate is further connected to the outside of the stacked structure through the contact pad, so that the contact pad is electrically connected to the first test pad in the test structure, and the multiple second electrodes in the capacitor structure are respectively electrically connected to the corresponding second test pads in the test structure. In this way, the test structure can test the voltage at different positions of the capacitor structure, and determine the leakage current at different positions of the capacitor structure according to the acquired voltage, so that the uniformity of the film thickness in the capacitor can be characterized by the size of the leakage current at different positions of the capacitor structure. The structure and characterization method are simple and easy to implement. In addition, by connecting the first electrode array to the substrate, and the substrate is further connected to the first test pad through the contact pad, the signal of the leakage current can be amplified, thereby providing the test accuracy of the test structure.

[0164] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0165] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0166] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A three-dimensional semiconductor structure, characterized in that: include: substrate; A stacking structure, the stacking structure is located on the substrate, the stacking structure comprises a plurality of capacitor structures arranged at intervals along a first direction, and an isolation wall is arranged between any two adjacent capacitor structures; the capacitor structure comprises a first electrode array and a plurality of second electrodes, the bottom of the first electrode array is connected to the substrate; the plurality of second electrodes are stacked at intervals along a second direction, and a supporting layer is arranged between any two adjacent second electrodes; wherein the second direction is the thickness direction of the substrate, and the first direction is perpendicular to the second direction; A contact pad is disposed in the isolation wall and penetrates the isolation wall along the first direction, and the bottom of the contact pad is connected to the substrate, and the projection of the contact pad along the first direction covers the projection of the capacitor structure in the first direction; A test structure is located on the stacked structure, the test structure includes a first test pad and a second test pad, the first test pad is electrically connected to the top of the contact pad, the second test pad is electrically connected to the second electrode, and the test structure is configured to test the voltage of the capacitor structure.

2. The three-dimensional semiconductor structure according to claim 1, characterized in that: The isolation wall is provided with a first slit penetrating the isolation wall along the second direction, the width of the first slit along the first direction is smaller than the width of the isolation wall along the first direction, and the contact pad is located in the first slit.

3. The three-dimensional semiconductor structure according to claim 2, characterized in that: The contact pad includes a metal conductive layer and a first barrier layer disposed between a sidewall of the first slit and the metal conductive layer.

4. The three-dimensional semiconductor structure according to claim 3, characterized in that: The metal conductive layer is a metal tungsten layer; and / or the first barrier layer is a titanium nitride layer.

5. The three-dimensional semiconductor structure according to any one of claims 1 to 4, characterized in that: The first electrode array includes a plurality of first electrodes arranged in an array, and each of the first electrodes is connected to the substrate.

6. The three-dimensional semiconductor structure according to claim 5, characterized in that: The plurality of first electrodes are arranged in a rectangular array.

7. The three-dimensional semiconductor structure according to any one of claims 1 to 4, characterized in that: It also includes multiple contact structures, which include a first contact plug and multiple second contact plugs. The first contact plug is electrically connected between the contact pad and the first test pad; each second contact plug is electrically connected between the corresponding second electrode and the second test pad.

8. The three-dimensional semiconductor structure according to any one of claims 1 to 4, characterized in that: The stack structure is provided with a plurality of first channels penetrating the stack structure along the second direction, and each of the first electrodes is respectively provided in the first channel corresponding thereto; The capacitor structure further includes a dielectric layer, wherein the dielectric layer is located between the first electrode and the inner wall of the first channel; The plurality of second electrodes are sequentially stacked and spaced apart in a step-like manner from a direction close to the substrate to a direction far away from the substrate, and each of the second electrodes is connected to the dielectric layer.

9. The three-dimensional semiconductor structure according to claim 8, characterized in that: A second blocking layer is further arranged between the dielectric layer and the first electrode; and / or a third blocking layer is further arranged between the second electrode and the support layer.

10. The semiconductor structure according to any one of claims 1 to 4, characterized in that: A plurality of the capacitor structures are arranged in parallel.

11. A method for preparing a three-dimensional semiconductor structure, characterized in that: include: providing a substrate; A stacking structure is formed on the substrate; the stacking structure comprises a plurality of capacitor structures spaced apart along a first direction, and an isolation wall is provided between any two adjacent capacitor structures; the capacitor structure comprises a first electrode array and a plurality of second electrodes, and the bottom of the first electrode array is connected to the substrate; the plurality of second electrodes are spaced apart and stacked along a second direction, and a supporting layer is provided between any two adjacent second electrodes; wherein the second direction is a thickness direction of the substrate, and the first direction is perpendicular to the second direction; forming a contact pad extending along the second direction and penetrating the isolation wall on each isolation wall, so that the contact pad is connected to the substrate; wherein the projection of the contact pad along the first direction covers the projection of the capacitor structure in the first direction; A test structure is formed on a surface of the stacked structure facing away from the substrate; the test structure includes a first test pad and a second test pad, the first test pad is electrically connected to the top of the contact pad, the second test pad is electrically connected to the second electrode, and the test structure is configured to test the voltage of the capacitor structure.

12. The method for preparing a three-dimensional semiconductor structure according to claim 11, characterized in that: The step of forming a contact pad on the isolation wall extending along the second direction and penetrating the stacked structure specifically includes: forming a first slit on the isolation wall extending along a second direction and penetrating the isolation wall; A first barrier layer and a metal conductive layer are sequentially formed in the first slit, and the first barrier layer and the metal conductive layer together form a contact pad.

13. The method for preparing a three-dimensional semiconductor structure according to claim 11, characterized in that: Before the step of forming a stacked structure on the substrate and after the step of providing the substrate, the method comprises: forming a plurality of preset layers stacked on the substrate; The plurality of preset layers include supporting layers and sacrificial layers which are alternately stacked in sequence.

14. The method for preparing a three-dimensional semiconductor structure according to claim 13, characterized in that: The step of forming a stacked structure on the substrate includes: A plurality of first channels arranged in an array are formed in the preset layer; the first channels extend along the second direction and penetrate the preset layer; A dielectric layer, a second barrier layer and a first electrode are sequentially formed in the first channel; wherein the second barrier layer is arranged around the outer side wall of the first electrode; and the dielectric layer is located between the second barrier layer and the inner side wall of the first channel; Removing the sacrificial layer in the preset layer and forming a second slit; A second electrode is formed in the second slit.

15. The method for preparing a three-dimensional semiconductor structure according to claim 14, characterized in that: Before removing the sacrificial layer in the preset layer, the method further comprises: Removing part of the supporting layer and part of the sacrificial layer on two opposite sides of the preset layer along the third direction to expose the surface of each supporting layer facing away from the substrate, so that the remaining adjacent supporting layers and sacrificial layers are arranged in a step-like manner from close to away from the substrate; the third direction, the second direction and the first direction are perpendicular to each other; forming a first oxide layer on the remaining support layer and the sacrificial layer; A plurality of third slits spaced apart along the first direction are formed on the first oxide layer, the third slits extend along the second direction and penetrate the preset layer, and the first electrode array and the third slits are sequentially spaced apart along the first direction.

16. The method for preparing a three-dimensional semiconductor structure according to claim 15, characterized in that: The step of forming a second electrode in the second slit specifically includes: sequentially forming a third blocking layer and a second electrode in the second slit through the third slit; removing the third barrier layer and the second electrode in the third slit; An isolation material is filled in the third slit to form an isolation wall.

17. The method for preparing a three-dimensional semiconductor structure according to claim 12, characterized in that: The step of forming a test structure on a surface of the stacked structure facing away from the substrate specifically includes: forming a second oxide layer on the stacked structure; forming a second channel and a plurality of third channels on the second oxide layer, wherein the second channel exposes the contact pad, and the third channel exposes the surface of the second electrode; wherein one third channel corresponds to one second electrode; Depositing a conductive material on the second oxide layer, the conductive material filling the second trench and the third trench while covering the surface of the second oxide layer; the conductive material filled in the second trench forms a first contact plug, and the conductive material filled in the third trench forms a second contact plug; The conductive material partially covering the surface of the second oxide layer is removed, and the conductive material covering the first contact plug and the second contact plug is retained; wherein the conductive material covering the first contact plug is formed into a first test pad; the conductive material covering the second contact plug is formed into a second test pad; the first test pad and the second test pad form the test structure.

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