Image sensor and method of forming the same
By employing a multi-step ion doping technique with phosphorus and arsenic in CMOS image sensors, the isolation region structure was optimized, solving the problems of insufficient full-well capacity and increased white spots in small-sized image sensors, and enabling the production of high-performance image sensors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GALAXYCORE SHANGHAI
- Filing Date
- 2021-09-13
- Publication Date
- 2026-04-10
AI Technical Summary
Existing small-sized CMOS image sensors have insufficient full-well capacity and small dynamic range. Furthermore, interface defects and damage are easily introduced during the deep trench isolation process on the back side of the back-illuminated CIS, leading to an increase in white spots.
N-type ion implantation is performed using phosphorus and arsenic. Through multi-step ion doping, first, second, and third ion-doped regions are formed. The second ion-doped region is located below the first ion-doped region, and the third ion-doped region partially or completely surrounds the first ion-doped region. Combined with rapid heat treatment and high-temperature annealing, ion implantation damage is repaired and the isolation region structure is optimized.
It improves full-well capacity, reduces white spot occurrence, maintains the FWC and low WP of high-performance small-pixel image sensors, and does not increase cost or mask layers.
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Figure CN115810639B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor manufacturing, and particularly relates to an image sensor and a method for forming the same. Background Technology
[0002] A CMOS image sensor (Complementary Metal Oxide Semiconductor image sensor, CIS) is a semiconductor device that converts optical images into electrical signals. A CIS consists of a photodiode (PD) for sensing light and logic circuitry for processing the sensed light into electrical signals.
[0003] As CIS pixel cells become smaller, the full well capacity (FWC) also decreases. To address the insufficient FWC and small dynamic range of small pixels, improvements are typically made in the depth direction of the substrate, for example, by increasing the depth of the silicon substrate. However, simply increasing the thickness of the silicon substrate does not significantly improve the FWC; an additional step of N-type ion implantation is usually required.
[0004] For back-illuminated CIS, deep trench isolation (BDTI) is typically formed on the back side of the substrate for isolation, addressing optical / electrical crosstalk between adjacent pixels. The etching process to form the BDTI structure introduces varying degrees of interface defects and damage. Subsequently, high-dielectric-constant materials such as hafnium oxide (HfO2) are deposited on the BDTI surface to passivate these defects, followed by filling with aluminum oxide (Al2O3). However, the isolation at the bottom and sides is generally weaker, making the passivation effect of the high-dielectric-constant materials easily susceptible to other factors.
[0005] like Figure 1 As shown, to ensure the field of view (FWC) of small-sized pixels, two N-type ion implantation masks are typically used on the semiconductor substrate 10 to form ion-doped regions 11 and 12. The upper half has a larger critical dimension (CD) (mainly contributing to the FWC), while the lower half has a smaller CD to account for lag and white pixels (WP). Phosphorus is used for implantation in both half. The disadvantage of this method is that phosphorus easily diffuses to the sides, resulting in insufficient P-type isolation 13. At the same time, it diffuses to the bottom of the semiconductor substrate 10, causing insufficient pinning of the high dielectric constant material 14 on the BDTI 15 surface, resulting in a significant increase in WP. Summary of the Invention
[0006] Based on the problems in the prior art, the application provides a forming method of an image sensor. The method comprises the following steps: providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface; performing ion implantation on the semiconductor substrate from the front surface of the semiconductor substrate to form a first ion doped region, a second ion doped region and a third ion doped region together to form a photosensitive unit of the image sensor; the second ion doped region is located below the first ion doped region; and the third ion doped region at least partially surrounds the first ion doped region.
[0007] In some embodiments, the first ion doped region is phosphorus; the second ion doped region and the third ion doped region are arsenic; and the ion implantation doped region for isolating the photosensitive units is boron or indium.
[0008] In some embodiments, the method further comprises the following step: performing ion implantation on the photosensitive units from the front surface of the semiconductor substrate to form a front surface isolation region.
[0009] In some embodiments, the method further comprises the following steps: forming a back surface deep trench isolation region on the back surface of the semiconductor substrate; and the bottom of the back surface deep trench isolation region is wrapped by the front surface isolation region.
[0010] In some embodiments, the second ion doped region is formed before the first ion doped region.
[0011] In some embodiments, the second ion doped region is formed before the first ion doped region; and after the second ion doped region is formed, ion activation is performed by rapid thermal treatment.
[0012] In some embodiments, the second ion doped region is formed before the first ion doped region; after the second ion doped region is formed, ion activation is performed by rapid thermal treatment, and then ion implantation loss repair is performed by high-temperature annealing.
[0013] In some embodiments, the temperature range of the rapid thermal treatment is 750-1100 DEG C, and the processing time is 10s-1min.
[0014] In some embodiments, the temperature range of the high-temperature annealing is 750-1100 DEG C, and the processing time is 10min-120min.
[0015] In some embodiments, after the second ion implantation doped region and the rapid thermal treatment are formed, the first ion implantation doped region and the front surface isolation region between the photosensitive units are formed.
[0016] In some embodiments, the second ion doped region is arsenic, and is formed by multi-step ion implantation through the same mask layer.
[0017] In some embodiments, the third ion doped region is arsenic, and is formed by multi-step ion implantation through the same mask layer.
[0018] In some embodiments, the first ion-doped region and the second ion-doped region are formed using the same mask layer.
[0019] In some embodiments, the third ion-doped region is formed using a mask layer that exposes the first ion-doped region.
[0020] In some embodiments, the third ion-doped region is formed using a mask layer that partially or completely covers the first ion-doped region, exposing a ring-shaped portion of the semiconductor substrate.
[0021] In some embodiments, the depth of the third ion-doped region is adjusted according to the depth of the backside deep trench isolation of the semiconductor substrate.
[0022] In some embodiments, the depth of the first ion-doped region exceeds the bottom of the backside deep trench isolation of the semiconductor substrate.
[0023] In some embodiments, the third ion-doped region and the second ion-doped region completely surround the first ion-doped region.
[0024] The present application also provides an image sensor, comprising: a semiconductor substrate having a front surface and a back surface; a first ion-doped region, a second ion-doped region, and a third ion-doped region located within the semiconductor substrate, collectively forming a photosensitive unit of the image sensor; the second ion-doped region is located below the first ion-doped region; the third ion-doped region at least partially surrounds the first ion-doped region.
[0025] The present application also provides an image sensor formed by the above method.
[0026] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:
[0027] The technical scheme of the present application reduces the WP increase caused by insufficient pinning of the bottom surface due to the diffusion of phosphorus to the bottom by performing N-type ion implantation on the semiconductor substrate using phosphorus and arsenic together, specifically, first performing ion implantation of phosphorus using a first mask layer, performing multiple steps of ion implantation of phosphorus from top to bottom on the front surface of the semiconductor substrate, and finally doping arsenic near the bottom region of the semiconductor substrate. Then, implant arsenic using a second mask layer, so that the implanted arsenic at least partially surrounds the phosphorus, thereby effectively utilizing the small diffusion coefficient of arsenic to avoid compensation by the P-type ions in the side isolation region, which not only ensures that the FWC will not decrease, but also avoids the increase of WP caused by insufficient pinning of the side isolation region. At the same time, arsenic is not completely used to replace phosphorus, the thermal budget is less, the implanted ions are easy to activate, and the damage in the implantation process is easy to repair.
[0028] The technical scheme of the present application has obvious advantages, without adding any new mask layer and increasing cost, a high-performance small-size high-pixel image sensor with a larger FWC and a smaller WP can be obtained. BRIEF DESCRIPTION OF DRAWINGS
[0029] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present application and, together with the description, further serve to explain the principles of the application and to enable a person skilled in the art to make and use the application.
[0030] Figure 1 A sectional view of a structure of an image sensor of the prior art is shown in the following figure:
[0031] Figure 2 A flow chart of a forming method of an image sensor of an embodiment of the present application is shown in the following figure:
[0032] Figure 3 A sectional view of a structure of an image sensor of an embodiment of the present application is shown in the following figure:
[0033] Figure 4 A sectional view of a structure of another image sensor of an embodiment of the present application is shown in the following figure. DETAILED DESCRIPTION
[0034] The following detailed description is exemplary in nature and is intended to provide further description of the present application. All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs unless otherwise specifically defined herein.
[0035] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.
[0036] Figure 2 A flow chart of a forming method of an image sensor of an embodiment of the present application is shown in the following figure, which comprises the following steps:
[0037] Step S1: providing a semiconductor substrate, which has a front surface and a back surface.
[0038] Step S2: performing ion implantation on the semiconductor substrate from the front surface of the semiconductor, to form a first ion doped region, a second ion doped region and a third ion doped region together forming a photosensitive unit of the image sensor; the second ion doped region is located below the first ion doped region; the third ion doped region at least partially surrounds the first ion doped region.
[0039] Specifically, in combination with Figure 3 and Figure 4 The forming method is described in detail. As shown in Figure 3 and Figure 4 A semiconductor substrate 20 is provided, which has a front surface and a back surface. Optionally, the semiconductor substrate 20 can be a doped or undoped semiconductor material, such as silicon, germanium, silicon germanium, silicon on insulator, or a combination thereof. Optionally, the semiconductor substrate 10 can include a substrate of multiple epitaxial layers.
[0040] As shown in Figure 3 and Figure 4 Ion implantation is performed on the semiconductor substrate 20 from the front surface of the semiconductor substrate 20 to form a first ion-doped region 21, a second ion-doped region 22, and a third ion-doped region 23, which together form a light sensing unit of an image sensor.
[0041] Optionally, the second ion-doped region 22 is located below the first ion-doped region 21; and the third ion-doped region 23 at least partially surrounds the first ion-doped region 21. As shown in Figure 4 The third ion-doped region 23 can completely surround the first ion-doped region 21.
[0042] Optionally, the first ion-doped region 21 is phosphorus; and the second ion-doped region 22 and the third ion-doped region 22 are arsenic.
[0043] The forming method of the image sensor of the embodiment further includes: performing ion implantation between the light sensing units from the front surface of the semiconductor substrate 20 to form a front surface isolation region 24. The ion implantation for isolating the light sensing units is boron or indium.
[0044] The forming method of the image sensor of the embodiment further includes: forming a backside deep trench isolation (BDTI) 26 on the back surface of the semiconductor substrate 20, and the bottom of the BDTI is wrapped by the front surface isolation region 24. The BDTI includes a layer of high dielectric constant side layer 25, such as hafnium oxide or the like.
[0045] Optionally, the second ion-doped region 22 is formed before the first ion-doped region 21.
[0046] Optionally, the second ion-doped region 22 is formed before the first ion-doped region 21; and after the formation of the second ion-doped region, rapid thermal treatment is performed for ion activation.
[0047] Optionally, the second ion-doped region 22 is formed before the first ion-doped region 21; and after the formation of the second ion-doped region, rapid thermal treatment is performed for ion activation, and then high-temperature annealing is performed for ion implantation loss repair.
[0048] Optionally, the rapid thermal treatment temperature ranges from 750 to 1100 °C, and the treatment time ranges from 10 s to 1 min.
[0049] Optionally, the high-temperature annealing temperature ranges from 750 to 1100 °C, and the treatment time ranges from 10 min to 120 min.
[0050] Optionally, after the formation of the second ion implantation doped region and the rapid thermal treatment, a front surface isolation region between the first ion implantation doped region and the light sensing unit is formed.
[0051] Optionally, the second ion doped region 22 is arsenic, and is formed by multi-step ion implantation through the same mask layer.
[0052] Optionally, the third ion doped region 23 is arsenic, and is formed by multi-step ion implantation through the same mask layer.
[0053] Optionally, the first ion doped region 21 and the second ion doped region 22 are formed by using the same mask layer.
[0054] Optionally, the mask layer used for forming the third ion doped region 23 exposes the first ion doped region 21.
[0055] Optionally, the mask layer used for forming the third ion doped region 23 partially or completely shields the first ion doped region 21, and exposes a ring-shaped part of the semiconductor substrate 20.
[0056] Optionally, the depth of the third ion doped region 23 is adjusted according to the depth of the BDTI of the semiconductor substrate 20.
[0057] Optionally, the depth of the first ion doped region 21 exceeds the bottom of the BDTI of the semiconductor substrate 20.
[0058] Optionally, as shown in FIG. 2, the third ion doped region 23 and the second ion doped region 22 completely surround the first ion doped region 21. Figure 4
[0059] Figure 3 Figure 4 As shown in FIG. 1 and FIG. 2, the present application also provides an image sensor, comprising: a semiconductor substrate 20, the semiconductor substrate 20 having a front surface and a back surface; a first ion doped region 21, a second ion doped region 22 and a third ion doped region 23 located in the semiconductor substrate 20, and collectively forming a light sensing unit of the image sensor; the second ion doped region 22 is located below the first ion doped region 21; and the third ion doped region 23 at least partially surrounds the first ion doped region 21.
[0060] It should be noted that the image sensor in the embodiments of the present application only shows part of the structure, and other devices of the image sensor, for example, transfer transistor, reset transistor, etc. are not shown.
[0061] It will be obvious to a person skilled in the art that, without departing from the spirit or essential characteristics of the application, the present application can be implemented otherwise than as described previously, for example, on the basis of the appended claims. The disclosures and the descriptions of the embodiments are only intended to be illustrative, and not restrictive. Thus, it should be appreciated that changes can be made to the form and details of the application without material affecting the overall object of the application. It is therefore clear that all the embodiments actually described are only illustrative in nature and that they should not be considered limiting the scope of the application. Moreover, it should be understood that in a command claiming a combination of features, the combination of features is not necessarily to be considered essential for the practice of the application. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" preceding the name of a element does not exclude other such elements also. The use of relative terms like "first", "second", and the like can be used solely to distinguish one independent claim from another claim without necessarily implying an order of priority.
Claims
1. A method for forming an image sensor, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having a front side and a back side; Ion implantation is performed on the semiconductor substrate from the front side to form a first ion-doped region, a second ion-doped region, and a third ion-doped region, which together form the photosensitive unit of the image sensor. The second ion-doped region is located below the first ion-doped region; The third ion-doped region at least partially surrounds the first ion-doped region; The depth of the third ion-doped region is adjusted according to the depth of the back trench isolation of the semiconductor substrate, and / or the depth of the first ion-doped region exceeds the bottom of the back trench isolation of the semiconductor substrate.
2. The method for forming an image sensor as described in claim 1, characterized in that, The first ion-doped region is phosphorus; the second and third ion-doped regions are arsenic; and the ion implantation doping between the photosensitive units is boron or indium.
3. The method for forming an image sensor as described in claim 2, characterized in that, Also includes: Ion implantation is performed between the photosensitive cells from the front side of the semiconductor substrate to form a front isolation region.
4. The method for forming an image sensor as described in claim 3, characterized in that, Also includes: A back-side deep trench isolation region is formed on the back side of the semiconductor substrate; The bottom of the deep groove isolation area on the back is covered by the front isolation area.
5. The method as described in claim 2, characterized in that, The second ion-doped region is formed before the first ion-doped region.
6. The method as described in claim 2, characterized in that, The second ion-doped region is formed before the first ion-doped region; after the second ion-doped region is formed, rapid thermal processing is used for ion activation.
7. The method as described in claim 2, characterized in that, The second ion-doped region is formed before the first ion-doped region; after the second ion-doped region is formed, rapid thermal treatment is used for ion activation, and then high-temperature annealing is used for ion implantation loss repair.
8. The method as described in claim 6 or 7, wherein the rapid heat treatment temperature range is 750~1100℃ and the treatment time is 10s-1min.
9. The method as described in claim 7, wherein the high-temperature annealing temperature range is 750~1100℃, and the processing time is 10min-120min.
10. The method as described in claim 6, characterized in that, After forming the second ion-doped region and undergoing rapid thermal processing, a front isolation region is then formed between the first ion-doped region and the photosensitive unit.
11. The method as described in claim 1, characterized in that, The second ion-doped region is arsenic, which is achieved through multi-step ion implantation using the same mask layer.
12. The method as described in claim 11, characterized in that, The third ion-doped region is arsenic, and is completed through multi-step ion implantation using the same mask layer.
13. The method as described in claim 2, characterized in that, The first ion-doped region and the second ion-doped region share the same mask layer.
14. The method as described in claim 2, characterized in that, The mask layer used to form the third ion-doped region exposes the first ion-doped region.
15. The method as described in claim 2, characterized in that, The mask layer used to form the third ion-doped region partially or completely blocks the first ion-doped region, exposing a ring-shaped portion of the semiconductor substrate.
16. The method as described in claim 3, characterized in that, The third ion-doped region and the second ion-doped region completely surround the first ion-doped region.
17. An image sensor, characterized in that, include: Semiconductor substrate, which has a front side and a back side; The first ion-doped region, the second ion-doped region, and the third ion-doped region located within the semiconductor substrate together form the photosensitive unit of the image sensor; The second ion-doped region is located below the first ion-doped region; The third ion-doped region at least partially surrounds the first ion-doped region; The depth of the third ion-doped region is adjusted according to the depth of the back trench isolation of the semiconductor substrate, and / or the depth of the first ion-doped region exceeds the bottom of the back trench isolation of the semiconductor substrate.
18. An image sensor, characterized in that, Formed by the method described in any one of claims 1 to 16.
Citation Information
Patent Citations
CMOS Image Sensors and Methods for Forming the Same
US20130320420A1
Photodiode and manufacturing method, sensor and sensing array
WO2020037455A1