Array substrate and display panel

Abstract

The present application discloses an array substrate, which includes a plurality of pixel driving circuits and a plurality of lead voltage lines. The plurality of pixel driving circuits are arranged in an array along a first direction and a second direction. In the first direction, at least two adjacent pixel driving circuits are arranged in a mirror-symmetrical manner, and a light-transmitting area is formed between the two mirror-symmetrically arranged pixel driving circuits. In the second direction, a plurality of pixel driving circuits located in the same column form a pixel column. At least a portion of the lead voltage lines extend between the two pixel columns where the two mirror-symmetrically arranged pixel driving circuits are located, and a partition area is provided on the lead voltage lines at a position corresponding to the light-transmitting area. The light-transmitting area is arranged corresponding to a photosensitive element, so that the optical sensor in the photosensitive element can accurately sense ambient light, so that the photosensitive element can control the display panel to adjust the screen brightness according to the ambient light, thereby improving the user's visual experience and saving power.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Display panels are becoming increasingly widely used, and their functionality is increasing, driving them towards intelligentization. Array substrates can be equipped with photosensitive elements on the backlight side to detect ambient brightness. This allows the array substrate to adjust the brightness of the light according to the ambient light, facilitating user experience.

[0003] Therefore, it is necessary to improve the structure of the array substrate so that the array substrate has a light-transmitting area so that the photosensitive element can sense the brightness in the external environment, thereby providing a basis for brightness control of the array substrate. Summary of the Invention

[0004] The present application mainly provides a method of opening a light-transmitting area on an array substrate so that light can pass through the array substrate to reach the optical sensor area of ​​the photosensitive element.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: providing an array substrate, which includes multiple pixel driving circuits and multiple lead-out voltage lines; wherein, the multiple pixel driving circuits are arranged in an array along a first direction and a second direction; wherein, in the first direction, at least partially adjacent two pixel driving circuits are arranged in a mirror-symmetrical manner, and a light-transmitting area is formed between the two pixel driving circuits arranged in a mirror-symmetrical manner.

[0006] In the second direction, multiple pixel driving circuits located in the same column form a pixel column; at least a portion of the extraction voltage line extends between two pixel columns containing two pixel driving circuits arranged in mirror symmetry, and a blocking region is provided at the position of the extraction voltage line corresponding to the light-transmitting region. By providing the blocking region at the position of the extraction voltage line corresponding to the light-transmitting region, the light-transmitting area of ​​the light-transmitting region is not affected by the extraction voltage line, thereby ensuring the light transmittance of the array substrate.

[0007] A lead voltage line is provided between the pixel columns where two pixel drive circuits are located in a mirror-symmetrical arrangement. By providing a lead voltage line between the pixel columns where two pixel drive circuits are located in a mirror-symmetrical arrangement, the space on the array substrate is fully utilized for routing the lead voltage line, thereby increasing the routing density within the array substrate and improving the integration of the array substrate.

[0008] The array substrate further includes: a plurality of reference voltage lines extending along a first direction and electrically connected to the pixel driving circuit; wherein one lead-out voltage line is electrically connected to one of the reference voltage lines. The lead-out voltage line is electrically connected to the reference voltage line, and the lead-out voltage line leads the signal of the reference voltage line, thereby facilitating voltage uniformity across the array substrate.

[0009] Preferably, the reference voltage line includes a first reference voltage line, a second reference voltage line, and a third reference voltage line, and the lead voltage line is electrically connected to one of the first reference voltage line, the second reference voltage line, and the third reference voltage line. The design of three reference voltage lines is conducive to maintaining the stability of the pixel circuit.

[0010] Wherein, in the first direction, the array substrate includes a plurality of lead-out voltage lines, and the plurality of lead-out voltage lines are electrically connected to the plurality of reference voltage lines alternately in sequence.

[0011] Between adjacent pixel columns containing mirror-symmetrically arranged pixel driver circuits, lead-out voltage lines connected to different reference voltage lines can be sequentially arranged, with the lead-out voltage lines and reference voltage lines forming a grid. By sequentially connecting the lead-out voltage lines and reference voltage lines, the signal from each reference voltage line is extracted, achieving uniform voltage and current across the pixel circuits in the array substrate.

[0012] The array substrate further includes a plurality of data lines extending along the second direction, with the data lines adjacent to the light-transmitting area being bent along the periphery of the light-transmitting area. By having the data lines adjacent to the light-transmitting area bend along the periphery of the light-transmitting area, the area of ​​the light-transmitting area can be controlled, so that the design of the light-transmitting area meets the requirements.

[0013] Among them, the lead-out voltage line and the first reference voltage line are located in different metal layers; and / or, the lead-out voltage line and the second reference voltage line are located in different metal layers; and / or, the lead-out voltage line and the third reference voltage line are located in different metal layers; by setting the reference voltage line and the lead-out voltage line in different metal layers, the routing design in the array substrate is optimized.

[0014] Preferably, the lead-out voltage line, the first reference voltage line, the second reference voltage line and the third reference voltage line are respectively located in different metal layers; by setting the reference voltage line and the lead-out voltage line in different metal layers, the voltage signal is transmitted in different layers of the array substrate, which is conducive to achieving voltage stability of the pixel circuit.

[0015] Preferably, the metal layer containing the first reference voltage line is located between the metal layer containing the third reference voltage line and the metal layer containing the lead-out voltage line, and the metal layer containing the second reference voltage line is located on the side of the metal layer containing the third reference voltage line facing away from the first reference voltage line. By arranging different reference voltage lines and lead-out voltage lines in different metal layers, the routing design in the array substrate is optimized, improving routing design efficiency and density, and increasing the integration of the array substrate.

[0016] The shape of the light-transmitting area is the same as the shape of the photosensitive element located below the light-transmitting area, so that the diffraction pattern of the light-transmitting area is the same as the shape of the photosensitive element, thereby improving the sensitivity of the photosensitive element.

[0017] Preferably, the photosensitive element and the light-transmitting area are circular in shape, which is a shape that is easy to design for the photosensitive element and the light-transmitting area.

[0018] The pixel drive circuit includes a charging circuit, a light-emitting circuit, and a reset circuit. The charging circuit is used to charge the drive transistor and write data; the light-emitting circuit responds to the light-emitting control signal to achieve light emission of the light-emitting element; and the reset circuit resets the transistor in the pixel drive circuit and includes multiple reference voltage lines.

[0019] The reset circuit includes a first reference voltage line, a second reference voltage line, and a third reference voltage line, wherein the first reference voltage line is connected to the gate of the driving transistor for resetting the gate of the driving transistor; the second reference voltage line is connected to the anode of the light-emitting element for resetting the anode of the light-emitting element; and the third reference voltage line is connected to the drain of the driving transistor for resetting the source of the driving transistor.

[0020] Preferably, the charging circuit includes a data line, a second transistor, a driving transistor and a third transistor, the drain of the second transistor is connected to the data line, the source of the second transistor is connected to the drain of the driving transistor, the source of the driving transistor is connected to the source of the third transistor, and the drain of the third transistor is connected to the gate of the driving transistor; the charging circuit is used to realize data writing and charging of the driving transistor.

[0021] Preferably, the light-emitting circuit includes a high power supply voltage line, a light-emitting control signal, a fifth transistor, a driving transistor, a sixth transistor, and a light-emitting element; the source of the fifth transistor is connected to the high power supply voltage line, the gate of the fifth transistor is connected to the light-emitting control signal, the drain of the fifth transistor is connected to the drain of the driving transistor, the source of the driving transistor is connected to the source of the sixth transistor, the gate of the sixth transistor is connected to the light-emitting control signal, and the drain of the sixth transistor is connected to the anode of the light-emitting element. The light-emitting circuit controls the light emission of the light-emitting element.

[0022] In order to solve the above technical problems, another technical solution adopted in the present application is: providing a display panel including the array substrate in the above embodiment.

[0023] The beneficial effects of the present application are as follows: at least two adjacent pixel driving circuits in the array substrate are arranged in mirror-symmetrical fashion, and a light-transmitting area is formed between the two mirror-symmetrically arranged pixel driving circuits. In addition, at least a portion of the lead-out voltage line extends between two pixel columns where the two mirror-symmetrically arranged pixel driving circuits are located, and a partition area is provided at the position of the lead-out voltage line corresponding to the light-transmitting area. The light-transmitting area is arranged corresponding to the photosensitive element, and the optical sensor in the photosensitive element can accurately sense the ambient light, so that the photosensitive element can control the display panel to adjust the screen brightness according to the ambient light, thereby improving the user's visual experience and saving the power of the display panel using the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0025] Figure 1 This is a structural diagram of an embodiment of an array substrate of a display panel of the present application;

[0026] Figure 2 This is a structural diagram of another embodiment of an array substrate of a display panel of the present application;

[0027] Figure 3 FIG. 1 is a circuit diagram of an embodiment of a pixel driving circuit in the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] See also Figure 1 , Figure 1This is a structural schematic diagram of an embodiment of an array substrate for a display panel of the present application. The present application provides an array substrate, which includes multiple pixel driving circuits and multiple lead-out voltage lines Vref', wherein the multiple pixel driving circuits are arranged in an array along a first direction X and a second direction Y. Wherein, in the first direction X, at least two adjacent pixel driving circuits are arranged in a mirror-symmetrical manner, and a light-transmitting area 1 is formed between the two mirror-symmetrically arranged pixel driving circuits; in the second direction Y, multiple pixel driving circuits located in the same column form a pixel column; at least part of the lead-out voltage line Vref' extends between two pixel columns where the two mirror-symmetrically arranged pixel driving circuits are located, and a partition area is provided on the lead-out voltage line Vref' at a position corresponding to the light-transmitting area 1.

[0030] The present application provides a method for providing a display panel using the array substrate with a plurality of pixel drive circuits disposed at least partially in a mirror-symmetrical manner, with a light-transmitting region 1 formed between the two mirror-symmetrically disposed pixel drive circuits. The light-transmitting region 1 is primarily composed of portions of the adjacent, mirror-symmetrically disposed pixel drive circuits. This eliminates the need to reduce the number of pixel drive circuits on the array substrate, thereby ensuring the resolution of the display panel using the array substrate and preventing the display effect of the display panel from being affected. Furthermore, the array substrate design of the present application includes an extraction voltage line Vref', at least a portion of which extends between two pixel columns containing the two mirror-symmetrically disposed pixel drive circuits. This extraction voltage line Vref' extends in the second direction Y, making the voltage in the display panel more uniform and further ensuring current uniformity and pixel circuit stability in the display panel. In the present application, by providing a light-transmitting region 1 between the mirror-symmetrically disposed pixel drive circuits, the light-transmitting region 1 is disposed correspondingly to a photosensitive element. The optical sensor in the photosensitive element can accurately sense ambient light, allowing the photosensitive element to control the display panel to adjust screen brightness according to the ambient light, thereby improving the user's visual experience and saving power for the display panel using the array substrate.

[0031] A lead voltage line Vref' is provided between a set of pixel columns containing two pixel drive circuits arranged in a mirror-symmetrical manner. The lead voltage line Vref' is provided between the pixel columns containing the two pixel drive circuits arranged in a mirror-symmetrical manner. Because the pixel columns provided with the lead voltage line Vref' are adjacent to each other and the pixel drive circuits in adjacent pixel columns are arranged in a mirror-symmetrical manner, there is sufficient space between the adjacent pixel columns to provide the lead voltage line Vref'. Furthermore, providing the lead voltage line Vref' between adjacent pixel columns does not affect other wiring designs in the array substrate and does not cause resistance interference.

[0032] In addition, the array substrate also includes a plurality of reference voltage lines Vref, which extend along a first direction X and are electrically connected to the pixel driving circuit; wherein, a lead voltage line Vref' is electrically connected to a reference voltage line Vref; the English equivalent of the reference voltage line Vref is voltage reference (abbreviated as Vref), and the reference voltage line Vref in this application refers to a voltage in the circuit that can remain constant regardless of the load, power supply, temperature drift, time, etc. When measuring voltage values, the voltage value is used as a reference point. Vref can be used in voltage regulators, analog-to-digital converters, and digital-to-analog converters in power supply systems.

[0033] Preferably, the reference voltage line Vref includes a first reference voltage line Vref 1, a second reference voltage line Vref 2, and a third reference voltage line Vref 3. An extraction voltage line Vref′, provided between a set of pixel columns containing two mirror-symmetrically arranged pixel driving circuits, is electrically connected to one of the first reference voltage line Vref 1, the second reference voltage line Vref 2, and the third reference voltage line Vref 3. In the pixel driving circuit of the present application, a total of three reference voltage lines Vref are included: a first reference voltage line Vref 1, a second reference voltage line Vref 2, and a third reference voltage line Vref 3. Each reference voltage line Vref is connected to a different transistor. Specifically, the first reference voltage line Vref 1 is connected to the source electrode Source of the fourth transistor T4, the second reference voltage line Vref 2 is connected to the drain electrode Drain of the seventh transistor T7, and the third reference voltage line Vref 3 is connected to the source electrode Source of the eighth transistor T8.

[0034] See also Figure 2 , Figure 2This is a schematic structural diagram of another embodiment of an array substrate for a display panel of the present application; in a first direction X, the array substrate includes a plurality of lead voltage lines Vref', and the plurality of lead voltage lines Vref' are electrically connected to a plurality of reference voltage lines Vref in alternating order. Since the lead voltage line Vref' is electrically connected to one of the first reference voltage line Vref 1, the second reference voltage line Vref 2, and the third reference voltage line Vref 3, and the lead voltage line Vref' is disposed between a group of pixel columns containing two mirror-symmetrically arranged pixel driving circuits, between adjacent pixel columns containing two mirror-symmetrically arranged pixel driving circuits arranged in sequence in the first direction X, the lead voltage line Vref' can be electrically connected to one of the first reference voltage line Vref 1, the second reference voltage line Vref 2, and the third reference voltage line Vref 3 in sequence according to the arrangement order of the adjacent pixel columns. That is, between adjacent pixel columns containing two mirror-symmetrically arranged pixel driver circuits, lead voltage lines Vref' connected to different reference voltage lines Vref can be sequentially arranged, so that the lead voltage lines Vref' and the reference voltage lines Vref form a grid design. In the first direction X, between a first group of adjacent pixel columns containing two mirror-symmetrically arranged pixel driver circuits, the lead voltage line Vref' is connected to the first reference voltage line Vref 1; between a second group of adjacent pixel columns, the lead voltage line Vref' is connected to the second reference voltage line Vref 2; and between a third group of adjacent pixel columns, the lead voltage line Vref' is connected to the third reference voltage line Vref 3, and the lead voltage lines Vref' are alternately arranged in this order.

[0035] It can be understood that in other embodiments, between the first group of adjacent pixel columns, the lead-out voltage line Vref' is connected to the second reference voltage line Vref 2 or the third reference voltage line Vref 3; between the second group of adjacent pixel columns, the lead-out voltage line Vref' is connected to the third reference voltage line Vref3 or the first reference voltage line Vref 1; between the third group of adjacent pixel columns, the lead-out voltage line Vref' is connected to the first reference voltage line Vref 1 or the second reference voltage line Vref 2, and then the arrangements are alternately performed in this order.

[0036] In the above embodiments, the lead-out voltage line Vref′ and the reference voltage line Vref can all be designed in a grid pattern, wherein the reference voltage line Vref extends along the first direction X, and the lead-out voltage line Vref′ extends along the second direction Y. In addition, since the lead-out voltage line Vref′ is sequentially connected to different reference voltage lines Vref, for the first reference voltage line Vref 1, the first reference voltage line Vref 1 extends along the first direction X, and the lead-out voltage line Vref′ connected to the first reference voltage line Vref 1 extends along the second direction Y. The first reference voltage line Vref 1 and the lead-out voltage lines Vref′ in the corresponding circuit structure have a grid structure in the array substrate. Similarly, the second reference voltage line Vref 2 and the lead-out voltage lines Vref′ in the corresponding circuit structure also have a grid structure in the array substrate, and the third reference voltage line Vref 3 and the lead-out voltage lines Vref′ in the corresponding circuit structure also have a grid structure in the array substrate. When the reference voltage line Vref and the lead-out voltage line Vref′ have a mesh structure in the array substrate, the reference voltage is more balanced and uniform, and the pixel circuit is stabilized.

[0037] In one embodiment, the lead-out voltage line Vref' and the first reference voltage line Vref 1 are located in different metal layers; in one embodiment, the lead-out voltage line Vref' and the second reference voltage line Vref 2 are located in different metal layers; in one embodiment, the lead-out voltage line Vref' and the third reference voltage line Vref 3 are located in different metal layers; when the reference voltage line Vref and the lead-out voltage line Vref' are set in different layers, the lead-out voltage line Vref' can effectively realize the lead-out of the signal in the reference voltage line Vref.

[0038] Preferably, the lead-out voltage line Vref', the first reference voltage line Vref 1, the second reference voltage line Vref 2 and the third reference voltage line Vref 3 are respectively located in different metal layers; when the lead-out voltage line Vref', the first reference voltage line Vref1, the second reference voltage line Vref 2 and the third reference voltage line Vref 3 are respectively located in different metal layers, the best routing design method can be obtained in the array substrate, the integration of the routing design in the array substrate is improved, and the routing setting space in the array substrate is reasonably arranged.

[0039] Preferably, the metal layer where the first reference voltage line Vref 1 is located is located between the metal layer where the third reference voltage line Vref 3 and the lead-out voltage line Vref' are located, and the metal layer where the second reference voltage line Vref 2 is located is located on the side of the metal layer where the third reference voltage line Vref 3 is located away from the first reference voltage line Vref 1. An optimal setting method for the reference voltage lines Vref is obtained by combining the connection relationships between different reference voltage lines Vref in the circuit.

[0040] In one embodiment, the array substrate includes a first metal layer M1 , a second metal layer M2 , a third metal layer M3 and a fourth metal layer M4 .

[0041] In one embodiment, the extraction voltage line Vref' is electrically connected to one of the first reference voltage line Vref1, the second reference voltage line Vref2, and the third reference voltage line Vref3. The extraction voltage line Vref' is located in the fourth metal layer M4; the first reference voltage line Vref1 is located in the third metal layer M3. The electrical connection between the first reference voltage line Vref1 and the extraction voltage line Vref' is achieved by opening a hole in the planar layer and filling the hole with a conductive material.

[0042] In one embodiment, the second reference voltage line Vref 2 is located in the first metal layer M1, and the electrical connection between the second reference voltage line Vref 2 and the lead-out voltage line Vref' is achieved through a conductive via connecting the second reference voltage line Vref 2 and the lead-out voltage line Vref';

[0043] In one embodiment, a conductive via is used to connect the second reference voltage line Vref 2 located in the first metal layer M1 and the third metal layer M3, and then the second reference voltage line signal Vref 2 is transmitted to the fourth metal layer M4 through a conductive via located between the third metal layer M3 and the fourth metal layer M4, thereby achieving electrical connection between the second reference voltage line Vref 2 and the extraction voltage line Vref′.

[0044] In one embodiment, the third reference voltage line Vref 3 is located in the second metal layer M2, and the electrical connection between the third reference voltage line Vref 3 and the lead-out voltage line Vref' is achieved through a conductive via connecting the third reference voltage line Vref 3 and the lead-out voltage line Vref'. The conductive via first connects the third reference voltage line Vref 3 located in the second metal layer M2 and the third metal layer M3, and then transmits the signal of the third reference voltage line Vref 3 to the fourth metal layer M4 through a conductive via between the third metal layer M3 and the fourth metal layer M4, thereby achieving the electrical connection between the third reference voltage line Vref 3 and the lead-out voltage line Vref'.

[0045] The array substrate also includes a plurality of data lines (Data) extending along a second direction (Y), with the data lines (Data) adjacent to the light-transmitting region 1 being curved along the periphery of the light-transmitting region. In the prior art, the data lines (Data) in the array substrate are designed as straight lines. When the data lines (Data) are designed as straight lines, the data lines (Data) in each of two adjacent pixel driving circuits with mirror-symmetrical designs are also arranged adjacent to each other. Furthermore, since the pixel driving circuits in the array substrate are arranged in an array along the first direction (X), it is impossible to design a light-transmitting region 1 between adjacent data lines (Data). In the present application, light-transmitting regions 1 are designed in adjacent mirror-symmetrical pixel driving circuits, and the data lines (Data) adjacent to the light-transmitting region 1 are curved along the periphery of the light-transmitting region 1. This allows for an increased area of ​​the light-transmitting region 1. Furthermore, by controlling the degree of curvature of the data lines (Data) around the periphery of the light-transmitting region 1, the size of the light-transmitting region 1 can be controlled, thereby ensuring that the area and transmittance of the light-transmitting region 1 of the array substrate meet customer requirements.

[0046] Preferably, the data line Data is connected to the second transistor T2. Specifically, the semiconductor layer (i.e., the P-Si layer) where the second transistor T2 is located is first connected to the third metal layer M3 through a first via, and then the data line Data is electrically connected to the second transistor T2 through the planarization layer through a second via in the third metal layer M3. The first via and the second via are connected through the third metal layer M3; the light-transmitting area 1 is arranged adjacent to the first and second vias. The first and second vias avoid the area of ​​the light-transmitting area 1. In the routing of the array substrate, the first and second vias are close to the drain Drain of the second transistor T2. Furthermore, the first and second vias are away from the edge of the light-transmitting area 1. In one embodiment, the data line Data is connected to the drain Drain of the second transistor T2, so that the second transistor T2 has the function of writing data.

[0047] In one embodiment, a zigzag design is adopted for the source electrode Source of the second transistor T2 in the array substrate, so that in the first direction X, the light-transmitting region 1 is located between the drain electrodes Drain of the second transistors T2 in adjacent pixel driving circuits, while simultaneously reducing the height of the gate Gate of the second transistor T2 in the second direction Y. This increases the height of the light-transmitting region 1 in the second direction Y, thereby increasing the area of ​​the light-transmitting region 1. In the prior art, the source electrode Source and the drain electrode Drain of the second transistor T2 are designed parallel to the second direction Y. In the present application, a zigzag design is adopted for the source electrode Source of the second transistor T2, so that the source electrode Source and the drain electrode Drain of the second transistor T2 are no longer parallel to the second direction Y. When adjacent pixel driving circuits adopt a mirror-symmetrical design, the distance between the drain electrodes Drain of the second transistors T2 in adjacent pixel driving circuits is increased. Conditions are created for providing a light-transmitting area 1 in the first direction X in adjacent pixel driving circuits with a mirror-symmetrical design. In addition, the height of the gate Gate of the second transistor T2 is reduced in the second direction Y. However, although the height of the gate Gate of the second transistor T2 is reduced, the width-to-length ratio of the gate Gate is still guaranteed so that the function of the gate Gate is not impaired. This design creates conditions for providing a light-transmitting area 1 in the second direction Y in adjacent pixel driving circuits with a mirror-symmetrical design.

[0048] In one embodiment, the array substrate further includes a first scan line S1 and a second scan line S2, which are spaced apart and extend along a first direction X. In a second direction Y, the light-transmitting region 1 is located between the first scan line S1 and the second scan line S2. In the second direction Y, the first scan line S1 and the second scan line S2 surround the light-transmitting region 1.

[0049] In one embodiment, the shape of the light-transmitting region 1 is identical to the shape of the photosensitive element located below the light-transmitting region 1. The shape of the light-transmitting region 1 can be not only a quadrilateral, such as a square, rectangle, parallelogram, isosceles trapezoid, right-angled trapezoid, or ordinary trapezoid, but also a circle, ellipse, or the like. In another embodiment, the light-transmitting region 1 can have a different shape. When the shape of the light-transmitting region 1 is identical to the shape of the photosensitive element located below the light-transmitting region 1, the diffraction pattern of the shape of the light-transmitting region 1 matches the pattern of the photosensitive element, thereby improving the sensitivity of the optical sensor in the photosensitive element.

[0050] Preferably, the shape of the photosensitive element and the light-transmitting area 1 is circular. When the shape of the photosensitive element is circular and the shape of the light-transmitting area 1 is also circular, the external light passing through the circular light-transmitting area will have a circular diffraction pattern. When the shape of the diffraction pattern is consistent with the shape of the photosensitive element, the sensitivity of the optical sensor in the photosensitive element can be improved. In one embodiment, the first scanning line S1 and the second scanning line S2 located on both sides of the light-transmitting area 1 in the second direction Y are in an arc shape (not shown in the figure), so that the light-transmitting area 1 has a circular shape. In one embodiment, the initial scanning line S0 is located in the first gate layer G1, the first scanning line S1 is located in the second gate layer G2, and the second scanning line S2 is located in the first metal layer M1. By designing different layers of scanning lines, the routing design of the array substrate is optimized.

[0051] Preferably, the pixel driving circuit includes a pixel driving circuit for a blue sub-pixel, a pixel driving circuit for a red sub-pixel, and a pixel driving circuit for a green sub-pixel. By changing the pixel driving circuit for the blue sub-pixel, the pixel driving circuit for the blue sub-pixel and the pixel driving circuit for its adjacent sub-pixel are arranged in a mirror-symmetrical manner. This approach is easier to implement in terms of production technology and has less impact on the display effect of the subsequent display panel. This is not limited here and can be adjusted according to actual circumstances.

[0052] See also Figure 3 , Figure 3 This is a schematic structural diagram of another embodiment of an array substrate for a display panel of the present application. The array substrate of the present application includes multiple pixel driving circuits and multiple lead-out voltage lines Vref'. The pixel driving circuit includes a charging circuit, a light-emitting circuit, and a reset circuit. The charging circuit is used to charge the driving transistor T1 and write data; the light-emitting circuit responds to a light-emitting control signal EM to enable the light-emitting element to emit light; and the reset circuit resets the transistors in the pixel driving circuit. The reset circuit includes multiple reference voltage lines Vref.

[0053] Furthermore, the reset circuit includes a first reference voltage line Vref 1, a second reference voltage line Vref 2, and a third reference voltage line Vref 3, wherein the first reference voltage line Vref 1 is connected to the gate Gate of the driving transistor T1 for resetting the gate Gate of the driving transistor T1; the second reference voltage line Vref 2 is connected to the anode of the light-emitting element for resetting the anode of the light-emitting element; the third reference voltage line Vref 3 is connected to the drain Drain of the driving transistor T1 for resetting the source Source of the driving transistor T1; wherein the first reference voltage line Vref1 and the third reference voltage line Vref3 perform a dual reset on the driving transistor T1, which has a good reset effect and is easy to control, thereby improving the stability and accuracy of the operation of the driving transistor T1 and achieving a uniform display effect of the display panel.

[0054] Preferably, the charging circuit includes a data line Data, a second transistor T2, a driving transistor T1 and a third transistor T3, the drain Drain of the second transistor T2 is connected to the data line Data, the source Source of the second transistor T2 is connected to the drain Drain of the driving transistor, the source Source of the driving transistor T1 is connected to the source Source of the third transistor T3, and the drain Drain of the third transistor T3 is connected to the gate Gate of the driving transistor T1; in the charging circuit, the signal of the data line Data passes through the drain Drain of the second transistor T2, then reaches the drain Drain of the driving transistor T1 through the source Source of the second transistor T2, then flows out through the source Source of the driving transistor T1 to reach the source Source of the third transistor T3, and then reaches the gate Gate of the driving transistor T1 through the drain Drain of the third transistor T3, thereby charging the driving transistor T1 and writing data.

[0055] Preferably, the light-emitting circuit includes a high power supply voltage line ELVDD, a light-emitting control signal EM, a fifth transistor T5, a driving transistor T1, a sixth transistor T6, and a light-emitting element; the source of the fifth transistor T5 is connected to the high power supply voltage line ELVDD, the gate of the fifth transistor T5 is connected to the light-emitting control signal EM, the drain of the fifth transistor T5 is connected to the drain of the driving transistor T1, the source of the driving transistor T1 is connected to the source of the sixth transistor T6, the gate of the sixth transistor T6 is connected to the light-emitting control signal EM, and the drain of the sixth transistor T6 is connected to the anode of the light-emitting element. In the light-emitting circuit, the gates of the fifth transistor T5 and the sixth transistor T6 are both connected to the light-emitting control signal EM, and the fifth transistor T5 and the sixth transistor T6 are turned on in response to a signal emitted by the light-emitting control signal EM.

[0056] Furthermore, the pixel driving circuit in the present application is an 8T1C structure, that is, the pixel driving circuit in the present application includes 8 transistors and 1 storage capacitor.

[0057] The first transistor T1 (or driving transistor T1) may be electrically connected between the high power voltage ELVDD supply and the light emitting element (or between the first node N1 and the second node N2), and may be turned on in response to a third node voltage at the third node N3.

[0058] The second transistor T2 is used for data writing, and the second transistor T2 (or switching transistor) may be electrically connected between the data line Data and the first node N1 and may be turned on in response to a signal of the second scan signal S2.

[0059] The third transistor T3 is used for threshold compensation. The third transistor T3 may be electrically connected between the second node N2 and the fourth node N4 and may be turned on by the second scan signal S2'. That is, the second transistor T2 and the third transistor T3 may transmit the data signal to the third node N3 in response to the second scan signal S2'. The storage capacitor Cst may be electrically connected between the high power supply voltage ELVDD and the third node N3 and may store the data signal provided to the third node N3.

[0060] The fourth transistor T4 is used to reset the gate Gate of the driving transistor T1. The fourth transistor T4 can be electrically connected between the fourth node N4 and the first reference voltage line Vref1, and can be turned on in response to the signal of the first scan line S1. Here, the storage capacitor Cst can be initialized to charge (or have) a voltage. In one embodiment, the third transistor T3 and the fourth transistor T4 are made of indium gallium zinc oxide (IGZO), which has a small leakage current during operation and improves the stability of the pixel circuit. The other transistors can be made of low temperature polysilicon (LTPS).

[0061] The fifth transistor T5 is used to control the light emitting element to emit light in the light emitting phase. The fifth transistor T5 may be electrically connected between the high power voltage ELVDD and the first node N1 and may be turned on in response to the light emitting control signal EM.

[0062] The sixth transistor T6 is used to control the light-emitting element to emit light during the light-emitting phase. The sixth transistor T6 may be electrically connected between the second node N2 and the fifth node N5 and may be turned on in response to the light-emitting control signal EM. In other words, the fifth transistor T5 and the sixth transistor T6 may form a current path from the high power supply voltage line ELVDD to the light-emitting element in response to the light-emitting control signal EM.

[0063] The seventh transistor T7 is used to reset the light-emitting element. The seventh transistor T7 can be electrically connected between the second reference voltage line Vref2 and the fifth node N5, and can be turned on in response to the signal of the initial scan line S0. In other words, the seventh transistor T7 can form a bypass path (or bypass route) between the fifth node N5 and the second voltage line Vref2 in response to the initial scan signal S0. The light-emitting element EL can be an organic light-emitting diode EL.

[0064] The eighth transistor T8 is used to reset the source of the driving transistor T1 and shares a gate line with the seventh transistor T7. The eighth transistor T8 can be electrically connected between the first node N1 and the third reference voltage line Vref3 and can be turned on in response to the initial scan signal S0. It resets the source of the driving transistor T1.

[0065] The organic light emitting diode EL may be electrically connected between the fifth node N5 and the low power supply voltage ELVSS. Similarly, the anode of the organic light emitting diode EL may be electrically connected to the fifth node N5, and the cathode of the organic light emitting diode EL may be electrically connected to the low power supply voltage ELVSS. The organic light emitting diode EL may emit light based on the current (i.e., the driving current) transmitted by the driving transistor T1. The organic light emitting diode EL works in conjunction with the storage capacitor Cst, as shown in FIG. Figure 3 As shown, the storage capacitor Cst may be represented as a parasitic capacitor electrically connected in parallel with the organic light emitting diode EL.

[0066] The present application also provides a display panel, which includes the array substrate in the above embodiment. This embodiment provides an array substrate, which can be applied to the following display panels, such as electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, smart bracelets, smart watches, super personal computers, navigators and other mobile or fixed terminals. The array substrate can be an organic light-emitting diode (OLED) array substrate, a micro light-emitting diode (Micro LED or μLED) array substrate, or a liquid crystal display (LCD) array substrate.

[0067] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An array substrate, characterized in that: include: A plurality of pixel driving circuits, the plurality of pixel driving circuits being arranged in an array along a first direction and a second direction; wherein, in the first direction, at least two adjacent pixel driving circuits are arranged in a mirror-symmetrical manner, and a light-transmitting area is formed between the two mirror-symmetrically arranged pixel driving circuits; Multiple lead-out voltage lines, in the second direction, multiple pixel driving circuits located in the same column form a pixel column; at least part of the lead-out voltage lines extend between two pixel columns where two pixel driving circuits are located in a mirror-symmetrical arrangement, and the lead-out voltage lines are provided with a partition area at a position corresponding to the light-transmitting area.

2. The array substrate according to claim 1, wherein: One of the lead-out voltage lines is arranged between two pixel columns where the pixel driving circuits are located in a mirror-symmetrical arrangement.

3. The array substrate according to claim 2, wherein: Also includes: A plurality of reference voltage lines are provided, wherein the reference voltage lines extend along the first direction and are electrically connected to the pixel driving circuit; wherein one of the lead-out voltage lines is electrically connected to one of the reference voltage lines.

4. The array substrate according to claim 3, wherein: The reference voltage lines include a first reference voltage line, a second reference voltage line, and a third reference voltage line, and the lead-out voltage line is electrically connected to one of the first reference voltage line, the second reference voltage line, and the third reference voltage line.

5. The array substrate according to claim 4, wherein: In the first direction, the array substrate includes a plurality of lead-out voltage lines, and the plurality of lead-out voltage lines are electrically connected to the plurality of reference voltage lines in sequence and in alternating order; Between two adjacent pixel columns where the pixel driving circuits are located and which are arranged in a mirror-symmetrical manner, lead-out voltage lines connected to different reference voltage lines are sequentially arranged, and the lead-out voltage lines and the reference voltage lines are designed in a grid.

6. The array substrate according to claim 1, wherein: Also includes: A plurality of data lines extend along the second direction, and the data lines adjacent to the light-transmitting area are bent along the periphery of the light-transmitting area.

7. The array substrate according to claim 5, wherein: The lead voltage line and the first reference voltage line are located in different metal layers; and / or, the lead voltage line and the second reference voltage line are located in different metal layers; and / or, the lead voltage line and the third reference voltage line are located in different metal layers.

8. The array substrate according to claim 7, wherein: The extraction voltage line, the first reference voltage line, the second reference voltage line, and the third reference voltage line are respectively located in different metal layers.

9. The array substrate according to claim 7, wherein: The metal layer where the first reference voltage line is located is located between the metal layer where the third reference voltage line and the lead-out voltage line are located, and the metal layer where the second reference voltage line is located is located on the side of the metal layer where the third reference voltage line is located away from the first reference voltage line.

10. The array substrate according to claim 1, wherein: The shape of the light-transmitting area is the same as the shape of the photosensitive element located below the light-transmitting area.

11. The array substrate according to claim 10, wherein: The photosensitive element and the light-transmitting area are circular in shape.

12. The array substrate according to claim 2, wherein: The pixel driving circuit includes: Charging circuit; used for charging the driving transistor and writing data; A light emitting circuit; in response to a light emitting control signal, the light emitting element is caused to emit light; A reset circuit is used to reset the transistors in the pixel driving circuit, and the reset circuit includes a plurality of reference voltage lines.

13. The array substrate according to claim 12, wherein: The reset circuit includes a first reference voltage line, a second reference voltage line and a third reference voltage line, wherein the first reference voltage line is connected to the gate of the driving transistor and is used to reset the gate of the driving transistor; The second reference voltage line is connected to the anode of the light emitting element and is used to reset the anode of the light emitting element; The third reference voltage line is connected to the drain of the driving transistor and is used to reset the source of the driving transistor.

14. The array substrate according to claim 12, wherein: The charging circuit includes a data line, a second transistor, the driving transistor and a third transistor, the drain of the second transistor is connected to the data line, the source of the second transistor is connected to the drain of the driving transistor, the source of the driving transistor is connected to the source of the third transistor, and the drain of the third transistor is connected to the gate of the driving transistor.

15. The array substrate according to claim 12, wherein: The light-emitting circuit includes a high power supply voltage line, a light-emitting control signal, a fifth transistor, the driving transistor, a sixth transistor and the light-emitting element; the source of the fifth transistor is connected to the high power supply voltage line, the gate of the fifth transistor is connected to the light-emitting control signal, the drain of the fifth transistor is connected to the drain of the driving transistor, the source of the driving transistor is connected to the source of the sixth transistor, the gate of the sixth transistor is connected to the light-emitting control signal, and the drain of the sixth transistor is connected to the anode of the light-emitting element.

16. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 15.

Images