A method for fabricating a GaN HEMT device using a selective epitaxy process

Abstract

The application belongs to the technical field of power semiconductors, and relates to a manufacturing method of a GaN HEMT device by using a selective epitaxy process. ++ In the manufacturing method, a medium is epitaxied on a Uid-GaN layer, and a medium hard mask is formed by combining a photoetching process and an etching process; a P-GaN layer and a P ++ -GaN layer are selectively epitaxied on the structure, not only a P-GaN gate structure is realized, but also a condition for forming an ohmic contact of a B electrode is provided, and finally, an enhancement device with a polarization junction is realized. Compared with a technology of realizing a polarization junction and an enhancement by etching a P-GaN layer partially or wholly, the application adopts a selective epitaxy process, avoids lattice damage introduced by an etching process, reduces an interface state density, and reduces an influence on 2DEG mobility.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, and more specifically, relates to a method for manufacturing a GaNHEMT device using selective epitaxy. Background Technology

[0002] GaN HEMT (High Electron Mobility Transistor) devices have broad application prospects in high-current, low-power, and medium-to-low-voltage switching applications. However, interface damage caused by etching processes leads to current leakage paths, causing the device's breakdown voltage to fall far short of its theoretical limit. Polarized superjunction technology is one method to improve the device's breakdown voltage. When the device is turned off, the 2DHG and 2DEG at the heterojunction are depleted, leaving positive and negative fixed charges to form a polarized junction. This alleviates the electric field concentration at the gate edge, making the electric field distribution in the drift region more uniform and improving the device's breakdown voltage. Using a P-GaN gate is one of the main methods to achieve enhancement mode. Partial or complete etching of the P-GaN layer can achieve polarized junctions and enhancement mode, but it causes lattice damage, reduces the quality of the gate interface, and decreases electron mobility at the channel, degrading output characteristics and affecting the device's reliability and stability. Summary of the Invention

[0003] This invention, based on the application requirements of GaN HEMT devices, proposes a method for manufacturing GaN HEMT devices using selective epitaxy. First, a dielectric material is epitaxially grown on the Uid-GaN layer, and a dielectric hard mask is formed using photolithography and etching processes. Then, a P-GaN layer and a P-GaN layer are selectively epitaxially grown on this structure. ++ The P-GaN layer not only realizes the P-GaN gate structure but also provides conditions for the formation of the B-electrode ohmic contact, ultimately realizing an enhancement-mode device with a polarized junction. Compared to techniques that utilize partial or complete etching of the P-GaN layer to achieve polarized junctions and enhancement-mode characteristics, this invention employs a selective epitaxial process, avoiding lattice damage introduced by the etching process, reducing interface state density, and minimizing its impact on 2DEG mobility.

[0004] To achieve the above-mentioned objectives, the technical solution of the present invention is as follows:

[0005] A method for manufacturing a GaN HEMT device using selective epitaxy, characterized by comprising the following steps:

[0006] Step 1: Prepare substrate 1, epitaxially grow GaN buffer layer 2 on substrate, epitaxially grow GaN channel layer 3 on GaN buffer layer 2, epitaxially grow AlGaN barrier layer 4 on GaN channel layer 3, and epitaxially grow Uid-GaN layer 5 on AlGaN barrier layer 4.

[0007] Step 2: Using chemical vapor deposition, a dielectric material is deposited on the Uid-GaN layer 5 and photolithography is performed to etch away the middle part of the dielectric material, thereby forming hard masks 61 at both ends of the upper surface of the Uid-GaN layer 5, defining the position of the next epitaxial growth of the P-GaN layer 7.

[0008] Step 3: Using metal-organic chemical vapor deposition, an epitaxial P-GaN layer 7 is formed, with the upper surface of the P-GaN layer 7 being lower than the upper surface of the hard mask 61 in the longitudinal direction of the device.

[0009] Step 4: Remove the hard mask 61, and the P-GaN on it is also removed, so as to selectively epitaxially grow the P-GaN layer 7 on the Uid-GaN layer 5;

[0010] Step 5: Using chemical vapor deposition, a dielectric material is deposited on the Uid-GaN layer 5 and the P-GaN layer 7, followed by photolithography. The two spaces between the dielectric materials are etched away, forming a hard mask 62 in three parts: the left end of the upper surface of the Uid-GaN layer 5, the middle part of the upper surface of the Uid-GaN layer 5 (contacting the left end of the P-GaN layer 7), and the right end of the upper surface of the Uid-GaN layer 5 (extending to the upper surface of the P-GaN layer 7). This defines the next step of epitaxial growth of P... ++ -The location of GaN layer 8;

[0011] Step 6: Using a metal-organic chemical vapor deposition process, first epitaxially grow P ++ -GaN layer 8, followed by in-situ growth of passivation layer 9. In the longitudinal direction of the device, the upper surface of passivation layer 9 is lower than the upper surface of hard mask 62.

[0012] Step 7: Remove the hard mask 62, and the P on it ++ -GaN and the passivation layer were removed together to achieve selective epitaxy of P on the Uid-GaN layer 5 and the P-GaN layer 7. ++ -GaN layer 8;

[0013] Step 8: Deposit the material to form the ohmic contact between the source 10 and the drain 11, and perform a stripping process and annealing to form the source 10 and drain 11 at both ends of the device;

[0014] Step 9: Using an etching process, the P near the drain electrode 11 is... ++ The passivation layer 9 on GaN layer 8 is completely etched away, and the middle part of the passivation layer 9 near the source electrode 10 is also etched away to expose P. ++ -GaN layer 8;

[0015] Step 10: At P near the drain 11 ++ - A B electrode 12 is formed on the GaN layer 8, near the P electrode 10. ++ Gate 13 is formed on GaN layer 8.

[0016] As a preferred method, by changing the process in step 10, the gate 13 formed can be an ohmic gate or a Schottky gate, which are incompatible.

[0017] As a preferred embodiment, the specific steps for making the gate 13 an ohmic gate are as follows: In step 10, material is deposited to form the ohmic contact between the B electrode 12 and the gate 13, followed by a stripping process and annealing, and then the P electrode near the drain 11 is deposited. ++ - A B electrode 12 is formed on the GaN layer 8, near the P electrode 10. ++ Gate 13 is formed on GaN layer 8.

[0018] As a preferred embodiment, the specific steps for the gate 13 to be a Schottky gate are as follows: In step 10, material is deposited to form the ohmic contact of the B electrode 12, a stripping process is performed, and annealing is carried out on the P electrode. ++ - A B electrode 12 is formed on the GaN layer 8, and then the material for forming the Schottky contact of the gate 13 is deposited. A lift-off process is then used to form the P electrode 12. ++ Gate 13 is formed on GaN layer 8.

[0019] As a preferred embodiment, electrode 12 and gate 13 can be shorted together.

[0020] As a preferred embodiment, the source electrode 10 and the B electrode 12 can be short-circuited together.

[0021] As a preferred method, the passivation layer 9 is made of SiN. x One of SiO2, Al2O3, and AlN.

[0022] As a preferred embodiment, both electrode B 12 and gate 13 are made of a combination of Ni, Au, Ti, and TiN.

[0023] The beneficial effect of this invention is that, compared with the technology of using partial or complete etching of P-GaN layer to realize polarization junction and enhancement mode, this invention adopts selective epitaxy process, which avoids lattice damage introduced by etching process, reduces interface state density, and reduces its impact on 2DEG mobility. Attached Figure Description

[0024] Figure 1 This is a two-dimensional structural schematic diagram of Example 1.

[0025] Figure 2 This is the process flow diagram of Example 1.

[0026] Figure 3 These are the specific process steps of Example 1, wherein:

[0027] (a) is a schematic diagram of the device structure after material preparation in step 1 of the process flow of Example 1;

[0028] (b) is a schematic diagram of the device structure after the hard mask is formed in step 2 of the process flow of Example 1;

[0029] (c) is a schematic diagram of the device structure after epitaxial P-GaN layer in step 3 of the process flow of Example 1;

[0030] (d) is a schematic diagram of the device structure after removing the hard mask in step 4 of the process flow of Example 1;

[0031] (e) is a schematic diagram of the device structure after the hard mask is formed in step 5 of the process flow of Example 1;

[0032] (f) is the extension of step 6 P in the process flow of Example 1. ++ - Schematic diagram of the device structure after GaN layer and in-situ growth of passivation layer;

[0033] (g) is a schematic diagram of the device structure after removing the hard mask in step 7 of the process flow of Example 1;

[0034] (h) is a schematic diagram of the device structure after the source and drain electrodes are formed in step 8 of the process flow of Example 1;

[0035] (i) is a schematic diagram of the device structure after etching the passivation layer in step 9 of the process flow of Example 1;

[0036] (j) is a schematic diagram of the device structure after the gate and B electrode are formed in step 10 of the process flow of Example 1. Detailed Implementation

[0037] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0038] Example 1:

[0039] Step 1: Prepare substrate 1, epitaxially grow GaN buffer layer 2 on substrate, epitaxially grow GaN channel layer 3 on GaN buffer layer 2, epitaxially grow AlGaN barrier layer 4 on GaN channel layer 3, and epitaxially grow Uid-GaN layer 5 on AlGaN barrier layer 4.

[0040] Step 2: Using chemical vapor deposition, a dielectric material is deposited on the Uid-GaN layer 5 and photolithography is performed to etch away the middle part of the dielectric material, thereby forming hard masks 61 at both ends of the upper surface of the Uid-GaN layer 5, defining the position of the next epitaxial growth of the P-GaN layer 7.

[0041] Step 3: Using metal-organic chemical vapor deposition, an epitaxial P-GaN layer 7 is formed, with the upper surface of the P-GaN layer 7 being lower than the upper surface of the hard mask 61 in the longitudinal direction of the device.

[0042] Step 4: Remove the hard mask 61, and the P-GaN on it is also removed, so as to selectively epitaxially grow the P-GaN layer 7 on the Uid-GaN layer 5;

[0043] Step 5: Using chemical vapor deposition, a dielectric material is deposited on the Uid-GaN layer 5 and the P-GaN layer 7, followed by photolithography. The two spaces between the dielectric materials are etched away, forming a hard mask 62 in three parts: the left end of the upper surface of the Uid-GaN layer 5, the middle part of the upper surface of the Uid-GaN layer 5 (contacting the left end of the P-GaN layer 7), and the right end of the upper surface of the Uid-GaN layer 5 (extending to the upper surface of the P-GaN layer 7). This defines the next step of epitaxial growth of P... ++ -The location of GaN layer 8;

[0044] Step 6: Using a metal-organic chemical vapor deposition process, first epitaxially grow P ++ -GaN layer 8, followed by in-situ growth of passivation layer 9. In the longitudinal direction of the device, the upper surface of passivation layer 9 is lower than the upper surface of hard mask 62.

[0045] Step 7: Remove the hard mask 62, and the P on it ++ -GaN and the passivation layer were removed together to achieve selective epitaxy of P on the Uid-GaN layer 5 and the P-GaN layer 7. ++ -GaN layer 8;

[0046] Step 8: Deposit the material to form the ohmic contact between the source 10 and the drain 11, and perform a stripping process and annealing to form the source 10 and drain 11 at both ends of the device;

[0047] Step 9: Using an etching process, the P near the drain electrode 11 is... ++ The passivation layer 9 on GaN layer 8 is completely etched away, and the middle part of the passivation layer 9 near the source electrode 10 is also etched away to expose P. ++ -GaN layer 8;

[0048] Step 10: Deposit the material to form the ohmic contact between the B electrode 12 and the gate 13, perform a lift-off process and annealing, and deposit the material near the drain 11 on the P electrode. ++ - A B electrode 12 is formed on the GaN layer 8, near the P electrode 10. ++ Gate 13 is formed on GaN layer 8.

[0049] The GaN HEMT device fabricated using the above method first involves epitaxially growing a dielectric on the Uid-GaN layer and forming a dielectric hard mask using photolithography and etching processes. Then, P-GaN and P-GaN layers are selectively epitaxially grown on this structure. ++ The -GaN layer not only realizes the P-GaN gate structure, but also provides the conditions for the formation of the B electrode ohmic contact, and finally realizes the enhancement device with polarized junction.

[0050] Example 2:

[0051] The difference between this example and Example 1 is that the gate 13 is a Schottky gate. Specifically, in step 10, the material forming the ohmic contact of the B electrode 12 is deposited, a stripping process is used, and annealing is performed on the P electrode. ++ - A B electrode 12 is formed on the GaN layer 8, and then the material for forming the Schottky contact of the gate 13 is deposited. A lift-off process is then used to form the P electrode 12. ++ Gate 13 is formed on GaN layer 8.

[0052] The GaN HEMT device fabricated using the above method first involves epitaxially growing a dielectric on the Uid-GaN layer and forming a dielectric hard mask using photolithography and etching processes. Then, P-GaN and P-GaN layers are selectively epitaxially grown on this structure. ++ The -GaN layer not only realizes the P-GaN gate structure, but also provides the conditions for the formation of the B electrode ohmic contact, ultimately realizing an enhancement-mode device with a polarized junction.

Claims

1. A method for manufacturing a GaN HEMT device using selective epitaxy, characterized in that, Includes the following steps: Step 1: Prepare a substrate (1), epitaxially grow a GaN buffer layer (2) on the substrate, epitaxially grow a GaN channel layer (3) on the GaN buffer layer (2), epitaxially grow an AlGaN barrier layer (4) on the GaN channel layer (3), and epitaxially grow a Uid-GaN layer (5) on the AlGaN barrier layer (4). Step 2: Using chemical vapor deposition, a dielectric material is deposited on the Uid-GaN layer (5) and photolithography is performed to etch away the middle part of the dielectric material, thereby forming hard masks (61) at both ends of the upper surface of the Uid-GaN layer (5) to define the position of the next epitaxial growth of the P-GaN layer (7); Step 3: Using metal-organic chemical vapor deposition, an epitaxial P-GaN layer (7) is formed. In the longitudinal direction of the device, the upper surface of the P-GaN layer (7) is lower than the upper surface of the hard mask (61). Step 4: Remove the hard mask (61), and the P-GaN on it is also removed to achieve selective epitaxy of P-GaN layer (7) on Uid-GaN layer (5); Step 5: Using chemical vapor deposition, a dielectric material is deposited on the Uid-GaN layer (5) and the P-GaN layer (7) and photolithography is performed to etch away the two portions of the dielectric material that are separated in the middle. This forms a hard mask (62) in three parts: the left end of the upper surface of the Uid-GaN layer (5), the middle part of the upper surface of the Uid-GaN layer (5) that contacts the left end of the P-GaN layer (7), and the right end of the upper surface of the Uid-GaN layer (5) that extends to the upper surface of the P-GaN layer (7). This defines the next step of epitaxial growth of P-GaN. ++ -The location of the GaN layer (8); Step 6: Using a metal-organic chemical vapor deposition process, first epitaxially grow P ++ -GaN layer (8), then passivation layer (9) is grown in situ. In the longitudinal direction of the device, the upper surface of the passivation layer (9) is lower than the upper surface of the hard mask (62). Step 7: Remove the hard mask (62), on which P ++ -GaN and the passivation layer are removed together to achieve selective epitaxy of P on the Uid-GaN layer (5) and the P-GaN layer (7). ++ -GaN layer(8); Step 8: Deposit the material to form the ohmic contact between the source (10) and drain (11), and perform a stripping process and annealing to form the source (10) and drain (11) at both ends of the device; Step 9: Using an etching process, the P near the drain (11) is... ++ The passivation layer (9) on the GaN layer (8) is completely etched away, and the middle part of the passivation layer (9) near the source (10) is also etched away to expose the P. ++ -GaN layer(8); Step 10: At P near the drain (11) ++ - A B electrode (12) is formed on the GaN layer (8), and a P electrode is formed near the source electrode (10). ++ - A gate (13) is formed on the GaN layer (8).

2. The method for manufacturing a GaN HEMT device using selective epitaxy as described in claim 1, characterized in that, By changing the process in step 10, the gate (13) formed can be an ohmic gate or a Schottky gate, which are incompatible.

3. The method for manufacturing a GaN HEMT device using selective epitaxy as described in claim 2, characterized in that, The specific steps for the gate (13) to be an ohmic gate are as follows: In step 10, material is deposited to form the ohmic contact between the B electrode (12) and the gate (13), a stripping process is used and annealing is performed, and P near the drain (11) is deposited. ++ - A B electrode (12) is formed on the GaN layer (8), and a P electrode is formed near the source electrode (10). ++ - A gate (13) is formed on the GaN layer (8).

4. A method for manufacturing a GaN HEMT device using selective epitaxy as described in claim 2, characterized in that, The specific steps for the gate (13) to be a Schottky gate are as follows: In step 10, material is deposited to form the ohmic contact of the B electrode (12), a stripping process is used and annealing is performed, and P near the drain (11) is deposited. ++ A B electrode (12) is formed on the GaN layer (8), and then the material forming the gate (13) Schottky contact is deposited. A stripping process is used to form the P electrode near the source (10). ++ - A gate (13) is formed on the GaN layer (8).

5. A method for manufacturing a GaN HEMT device using selective epitaxy as described in claim 1, characterized in that, The B electrode (12) is shorted to the gate electrode (13).

6. A method for manufacturing a GaN HEMT device using selective epitaxy as described in claim 1, characterized in that, The source electrode (10) and the B electrode (12) are short-circuited together.

7. A method for manufacturing a GaN HEMT device using selective epitaxy as described in claim 1, characterized in that, The passivation layer (9) is made of SiN. x One of SiO2, Al2O3, and AlN.

8. A method for manufacturing a GaN HEMT device using selective epitaxy according to claim 1, characterized in that, The materials used for the B electrode (12) and the gate (13) are one of Ni, Au, Ti, TiN or a combination thereof.

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