Test structure and test method

Abstract

The present invention provides a test structure and a test method, the test structure comprising: a substrate; a device structure formed on the substrate; a first metal interconnection line, a second metal interconnection line and a first pad, the first metal interconnection line is electrically connected to the device structure, the second metal interconnection line is electrically connected to the first pad, and the first metal interconnection line is disconnected from the second metal interconnection line; an electromigration metal line, the electromigration metal line is located between the first metal interconnection line and the second metal interconnection line, so that when the electromigration metal line undergoes electromigration, the electromigration metal line is electrically connected to the first metal interconnection line and the second metal interconnection line respectively. The technical solution of the present invention can effectively prevent the free positive charge and negative charge from causing damage to the device structure, while also allowing the test to proceed normally.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a test structure and a test method. Background Art

[0002] During processes such as deposition and etching, plasma bombardment is performed on the wafer surface, resulting in free positive and negative charges on the wafer surface. These free charges are conducted through conductors on the wafer surface to the device structure in the test structure used for reliability and WAT testing. For example, when the device structure is a MOS transistor, the free charges are conducted to the gate layer and gate oxide layer in the MOS transistor, causing damage to the gate oxide layer, thereby affecting the performance of the semiconductor device.

[0003] Among them, in order to avoid damage to the device structure, a protection diode connected in parallel with the device structure is currently added to the test structure to conduct away the free charges. However, the protection diode has limited conduction capability for free charges. If the area of ​​the protection diode is small, it will not be able to conduct away all the free charges; and when a protection diode connected in parallel with the device structure is added to the test structure, in order to be able to test the semiconductor device normally later, it is necessary to specially select the polarity of the protection diode (for example, when the device structure is a MOS transistor, in order to perform a reverse test normally, NMOS must select an N / P diode instead of a P / N diode, and PMOS must select a P / N diode instead of an N / P diode). However, since the protection diode of a specific polarity has a good conduction capability only for a certain specific charge, but a poor conduction capability for another charge (for example, the P / N diode has a good conduction capability for positive charges, but a poor conduction capability for negative charges), the protection diode has a poor protection effect on the device structure.

[0004] Therefore, the test structure needs to be improved to solve the above problems. Summary of the invention

[0005] The object of the present invention is to provide a test structure and a test method, which can effectively prevent free positive charges and negative charges from damaging the device structure while allowing the test to proceed normally.

[0006] To achieve the above object, the present invention provides a test structure, comprising:

[0007] substrate;

[0008] a device structure formed on the substrate;

[0009] a first metal interconnection line, a second metal interconnection line and a first pad, wherein the first metal interconnection line is electrically connected to the device structure, the second metal interconnection line is electrically connected to the first pad, and the first metal interconnection line is disconnected from the second metal interconnection line;

[0010] The electromigration metal line is located between the first metal interconnection line and the second metal interconnection line, so that when the electromigration metal line undergoes electromigration, the electromigration metal line is electrically connected to the first metal interconnection line and the second metal interconnection line respectively.

[0011] Optionally, the test structure further includes:

[0012] A third metal interconnection line, a second pad and a third pad, wherein two ends of the electromigration metal line are electrically connected to the second pad and the third pad respectively through the third metal interconnection line.

[0013] Optionally, the first metal interconnection line and the device structure, the second metal interconnection line and the first pad, the two ends of the electromigration metal line and the third metal interconnection line, and the third metal interconnection line and the second pad and the third pad are all electrically connected via conductive plugs.

[0014] Optionally, the electromigration metal line is more susceptible to electromigration than the third metal interconnection line.

[0015] Optionally, a longitudinal cross-sectional area of ​​the electromigration metal line is smaller than a longitudinal cross-sectional area of ​​the third metal interconnect line; or, a material of the electromigration metal line is more susceptible to electromigration than a material of the third metal interconnect line.

[0016] Optionally, a metal diffusion barrier layer is formed between two ends of the electromigration metal line and the conductive plug.

[0017] Optionally, the first metal interconnection line and the second metal interconnection line extend from one end close to the electromigration metal line toward both ends of the electromigration metal line.

[0018] Optionally, the device structure is a MOS transistor, the MOS transistor includes a gate oxide layer and a gate layer formed in sequence on the substrate, and the MOS transistor is an NMOS transistor or a PMOS transistor; the device structure is a capacitor structure, the capacitor structure is composed of the substrate, the gate oxide layer and the control gate layer, or the capacitor structure includes an oxide layer, a floating gate layer, an inter-gate dielectric layer and a control gate layer formed in sequence on the substrate.

[0019] The present invention also provides a testing method, comprising:

[0020] A wafer is provided, wherein the wafer comprises a test structure, wherein the test structure comprises a substrate, a device structure, a first metal interconnection line, a second metal interconnection line and an electromigration metal line, wherein the device structure is formed on the substrate, the first metal interconnection line is electrically connected to the device structure, the electromigration metal line is located between the first metal interconnection line and the second metal interconnection line, and the first metal interconnection line, the second metal interconnection line and the electromigration metal line are disconnected from each other;

[0021] performing a production process, wherein the production process generates free positive charges and negative charges on the surface of the wafer, and the free positive charges and negative charges are not introduced into the first metal interconnection line through the second metal interconnection line, and are not guided into the device structure;

[0022] A current is applied to the electromigration metal line to cause electromigration of the electromigration metal line, thereby causing the electromigration metal line to be electrically connected to the first metal interconnection line and the second metal interconnection line, respectively.

[0023] Optionally, before applying current to the electromigration metal line, the testing method further includes:

[0024] forming a third metal interconnection line electrically connected to both ends of the electromigration metal line;

[0025] A first pad, a second pad and a third pad are formed, the second metal interconnection line is electrically connected to the first pad, and the two ends of the electromigration metal line are electrically connected to the second pad and the third pad respectively through the third metal interconnection line, so that current is applied to the electromigration metal line through the second pad and the third pad.

[0026] Optionally, a current is applied to the electromigration metal line so that the current density in the electromigration metal line is in the range of 0.3 MA / cm 2 ~10MA / cm 2 .

[0027] Optionally, the testing method further comprises:

[0028] Testing is performed on the device structure.

[0029] Optionally, the production process includes a deposition process or an etching process.

[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0031] 1. The test structure of the present invention is in a disconnected state before the production process is executed, so that the free positive and negative charges generated in the production process cannot be introduced into the first metal interconnection through the second metal interconnection, and then cannot be introduced into the device structure, thereby effectively avoiding the free positive and negative charges from damaging the device structure; and, since the test structure includes an electromigration metal line, and the electromigration metal line is located between the first metal interconnection and the second metal interconnection, before the test is executed, the electromigration metal line can be electrically connected to the first metal interconnection and the second metal interconnection respectively under the action of electromigration, that is, the first metal interconnection is electrically connected to the second metal interconnection, so that subsequent tests can be carried out normally.

[0032] 2. The test method of the present invention is that before executing the production process, the first metal interconnection line and the second metal interconnection line electrically connected to the device structure in the test structure are in a disconnected state, so that the free positive and negative charges generated during the production process cannot be introduced into the first metal interconnection line through the second metal interconnection line, and then cannot be introduced into the device structure, thereby effectively avoiding the free positive and negative charges from causing damage to the device structure; and, since the test structure includes the electromigration metal line, and the electromigration metal line is located between the first metal interconnection line and the second metal interconnection line, before executing the test, when current is applied to the electromigration metal line, the electromigration metal line can be electromigrated, and then the electromigration metal line is electrically connected to the first metal interconnection line and the second metal interconnection line respectively under the action of electromigration, that is, the first metal interconnection line is electrically connected to the second metal interconnection line, so that voltage can be applied to the device structure normally subsequently, that is, subsequent tests can be carried out normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic top view of a test structure according to an embodiment of the present invention;

[0034] Figure 2 is a schematic top view of a test structure after current is applied according to an embodiment of the present invention;

[0035] Figure 3a yes Figure 1 A schematic cross-sectional view of the test structure shown along the AA' direction;

[0036] Figure 3b yes Figure 2A schematic cross-sectional view of the test structure along the BB' direction after current is applied as shown;

[0037] Figure 4 is a flow chart of a testing method according to an embodiment of the present invention.

[0038] Among them, Figure 1 to Figure 4 The reference numerals are described as follows:

[0039] 11-active area; 12-gate layer; 131-first metal interconnection line; 132-second metal interconnection line; 133-first pad; 141-electromigration metal line; 142-third metal interconnection line; 143-second pad; 144-third pad; 15-conductive plug; 16-dielectric layer. DETAILED DESCRIPTION

[0040] In order to make the purpose, advantages and features of the present invention clearer, the test structure and test method proposed in the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0041] An embodiment of the present invention provides a test structure, comprising: a substrate; a device structure formed on the substrate; a first metal interconnection line, a second metal interconnection line and a first pad, wherein the first metal interconnection line is electrically connected to the device structure, the second metal interconnection line is electrically connected to the first pad, and the first metal interconnection line is disconnected from the second metal interconnection line; an electromigration metal line, wherein the electromigration metal line is located between the first metal interconnection line and the second metal interconnection line, so that when electromigration occurs, the electromigration metal line is electrically connected to the first metal interconnection line and the second metal interconnection line, respectively.

[0042] See below Figure 1 to Figure 3b The test structure provided by this embodiment is described in detail.

[0043] The device structure is formed on the substrate and can be a MOS transistor or a capacitor structure.

[0044] Take the device structure as a MOS transistor as an example, Figure 1 and Figure 2As shown, a shallow trench isolation structure (not shown) is formed in the substrate, and the area surrounded by the shallow trench isolation structure is an active area 11. The MOS transistor includes a gate oxide layer (not shown) and a gate layer 12 formed in sequence on the active area 11, and the gate layer 12 extends from the active area 11 to the shallow trench isolation structure; and the MOS transistor also includes a source region (not shown) and a drain region (not shown) formed in the active area 11 on both sides of the gate layer 12.

[0045] The MOS transistor may be an NMOS transistor or a PMOS transistor, and the test structure may include only an NMOS transistor or a PMOS transistor, or include both an NMOS transistor and a PMOS transistor.

[0046] The capacitor structure (not shown) is composed of a substrate, a gate oxide layer and a control gate layer. In some embodiments, the capacitor structure may also be a PIP (Poly-insulator-poly) capacitor, etc., including an oxide layer, a floating gate layer, an inter-gate dielectric layer and a control gate layer sequentially formed on the substrate.

[0047] like Figure 1 As shown, the first metal interconnection line 131 is electrically connected to the device structure, the second metal interconnection line 132 is electrically connected to the first pad 133 , and the first metal interconnection line 131 and the second metal interconnection line 132 are disconnected.

[0048] When the device structure is a MOS transistor, the first metal interconnection line 131 is electrically connected to the gate layer 12; when the device structure is a capacitor structure, the first metal interconnection line 131 is electrically connected to the control gate layer.

[0049] The two ends of the electromigration metal line 141 are electrically connected to the second pad 143 and the third pad 144 respectively through the third metal interconnection line 142; the electromigration metal line 141 is located between the first metal interconnection line 131 and the second metal interconnection line 132, that is, the electromigration metal line 141, the first metal interconnection line 131 and the second metal interconnection line 132 are located in the same layer. Figure 1 and Figure 3a As shown, before the electromigration metal line 141 undergoes electromigration, the electromigration metal line 141 is not connected to the first metal interconnection line 131 or the second metal interconnection line 132 .

[0050] When current is applied to the electromigration metal line 141 through the second pad 143 and the third pad 144, the current flows from the anode to the cathode. If the current density in the electromigration metal line 141 is large enough, the electrons move from the cathode to the anode at a high speed under the drive of the electrostatic field, forming an electron wind. The metal ions diffuse directionally from the cathode to the anode under the drive of the electron wind, thereby electromigration occurs, and the metal ions accumulate at the end of the electromigration metal line 141 close to the anode, so that the accumulated metal ions diffuse to both sides of the electromigration metal line 141 close to the anode end, so that the width gradually increases. In addition, since the distance between the electromigration metal line 141 and the first metal interconnection line 131 and the second metal interconnection line 132 on both sides are very close, the increased width of the electromigration metal line 141 close to the anode end can be easily increased to contact the first metal interconnection line 131 and the second metal interconnection line 132 on both sides, thereby achieving electrical connection between the first metal interconnection line 131 and the second metal interconnection line 132.

[0051] like Figure 2 and Figure 3b As shown, when a positive voltage is applied to the second pad 143 and a negative voltage is applied to the third pad 144 or the third pad 144 is grounded, the second pad 143 acts as an anode and the third pad 144 acts as a cathode, and electromigration occurs at the top of the electromigration metal line 141, so that the metal ions accumulated at the top of the electromigration metal line 141 near one end of the second pad 143 migrate toward the first metal interconnect line 131 and the second metal interconnect line 132 respectively, and the width increases to form an A1 region, so that the electromigration metal line 141 is electrically connected to the first metal interconnect line 131 and the second metal interconnect line 132 through the A1 region, thereby realizing electrical connection between the first metal interconnect line 131 and the second metal interconnect line 132.

[0052] It should be noted that, in other embodiments, a positive voltage may be applied to the third pad 144, and a negative voltage may be applied to the second pad 143 or the second pad 143 may be grounded. In this case, the third pad 144 serves as an anode and the second pad 143 serves as a cathode. Electromigration occurs at the top of the electromigration metal line 141 so that the A1 region is formed at the top of the electromigration metal line 141 near one end of the third pad 144.

[0053] Preferably, the ends of the first metal interconnection line 131 and the second metal interconnection line 132 close to the electromigration metal line 141 extend toward both ends of the electromigration metal line 141, so that the length of the electromigration metal line 141 between the end of the first metal interconnection line 131 close to the electromigration metal line 141 and the end of the second metal interconnection line 132 close to the electromigration metal line 141 increases, thereby ensuring that the increased width portion of the electromigration metal line 141 close to the anode end can contact the first metal interconnection line 131 and the second metal interconnection line 132 on both sides. Figure 1 and Figure 2 Taking the illustrated embodiment as an example, the first metal interconnection line 131 and the second metal interconnection line 132 may both be T-shaped, with the “—” portion of the T-shape close to the electromigration metal line 141 and the “|” portion of the T-shape away from the electromigration metal line 141 .

[0054] Furthermore, due to electromigration, the width of the electromigration metal line 141 near the anode end increases. Therefore, when the length of the electromigration metal line 141 is greatly different from the lengths of the first metal interconnection line 131 and the second metal interconnection line 132 on both sides, in order to ensure that the increased width of the electromigration metal line 141 near the anode end can be connected to the first metal interconnection line 131 and the second metal interconnection line 132 on both sides, the first metal interconnection line 131 and the second metal interconnection line 132 are preferably formed closer to the anode end. Figure 1 and Figure 2 Taking the illustrated embodiment as an example, the first metal interconnection line 131 and the second metal interconnection line 132 are preferably formed closer to the second pad 143 and the third metal interconnection line 142 connected to the second pad 143 .

[0055] It should be noted that, in other embodiments, the lengths of the first metal interconnect line 131 and the second metal interconnect line 132 may be increased to be close to the length of the electromigration metal line 141. In this case, the first metal interconnect line 131 and the second metal interconnect line 132 may be located in the middle of the area between the anode and the cathode, or may be closer to the anode or closer to the cathode.

[0056] Furthermore, the first metal interconnection line 131 and the device structure, the second metal interconnection line 132 and the first pad 133, the two ends of the electromigration metal line 141 and the third metal interconnection line 142, and the third metal interconnection line 142 and the second pad 143 and the third pad 144 are all electrically connected via at least one layer of conductive plugs 15 and / or at least one layer of metal interconnection lines (not shown), and the conductive plugs 15 of each layer are alternately connected to the metal interconnection lines of each layer.

[0057] Furthermore, the electromigration metal line 141 is more susceptible to electromigration than the third metal interconnection line 142, so as to avoid electromigration in the third metal interconnection line 142. The longitudinal cross-sectional area of ​​the electromigration metal line 141 can be smaller than the longitudinal cross-sectional area of ​​the third metal interconnection line 142, or the material of the electromigration metal line 141 is more susceptible to electromigration than the material of the third metal interconnection line 142.

[0058] When the longitudinal cross-sectional area of ​​the electromigration metal line 141 is smaller than the longitudinal cross-sectional area of ​​the third metal interconnection line 142, the width of the electromigration metal line 141 in a direction parallel to the substrate surface is smaller than the width of the third metal interconnection line 142 in a direction parallel to the substrate surface, and / or the thickness of the electromigration metal line 141 in a direction perpendicular to the substrate surface is smaller than the thickness of the third metal interconnection line 142 in a direction perpendicular to the substrate surface.

[0059] When the material of the electromigration metal line 141 is more susceptible to electromigration than the material of the third metal interconnection line 142, the material of the electromigration metal line 141 may be aluminum or copper, and the material of the third metal interconnection line 142 may be copper or tungsten, and the ability of aluminum, copper and tungsten to undergo electromigration decreases in turn.

[0060] Furthermore, a metal diffusion barrier layer (not shown) is formed between the conductive plugs 15 on both ends of the electromigration metal line 141 (i.e., the conductive plugs 15 between both ends of the electromigration metal line 141 and the third metal interconnection line 142) and the electromigration metal line 141 to prevent the conductive plugs 15 from electromigration; and, a plurality of conductive plugs 15 may be formed on both ends of the electromigration metal line 141 to reduce the current density in each conductive plug 15 by increasing the number of the conductive plugs 15, thereby further preventing the conductive plugs 15 from electromigration.

[0061] As can be seen from the above content, in the test structure of the present invention, since the first metal interconnection line 131 electrically connected to the device structure and the second metal interconnection line 132 electrically connected to the first pad 133 are in a disconnected state before the production process is executed, the free positive and negative charges generated during the production process cannot be introduced into the first metal interconnection line 131 through the second metal interconnection line 132, and then cannot be introduced into the device structure, thereby effectively avoiding the free positive and negative charges from causing damage to the device structure; and since the test structure includes the electromigration metal line 141, the third metal interconnection line 142, the second pad 143 and the third pad 144, and the two ends of the electromigration metal line 141 are electrically connected to the second pad 143 and the third pad 144 respectively through the third metal interconnection line 142. The electromigration metal line 141 is located between the first metal interconnection line 131 and the second metal interconnection line 132, so that before performing the test, when a current of a predetermined value is applied to the electromigration metal line 141 through the second pad 143 and the third pad 144, the electromigration metal line 141 can be electromigrated, and then the electromigration metal line 141 is electrically connected to the first metal interconnection line 131 and the second metal interconnection line 132 respectively under the action of electromigration, that is, the first metal interconnection line 131 and the second metal interconnection line 132 are electrically connected, and the first pad 133 is electrically connected to the device structure through the first metal interconnection line 131 and the second metal interconnection line 132, so that the voltage can be normally applied to the device structure through the first pad 133 subsequently, that is, the subsequent test can be carried out normally.

[0062] Furthermore, the test structure of the present invention can achieve good protection for the device structure without forming a protection diode, thereby simplifying the test structure and saving costs; and since the test structure does not include a protection diode, there will be no problem of the protection diode affecting tests such as inversion tests.

[0063] In summary, the present invention provides a test structure, comprising: a substrate; a device structure formed on the substrate; a first metal interconnection line, a second metal interconnection line and a first pad, wherein the first metal interconnection line is electrically connected to the device structure, the second metal interconnection line is electrically connected to the first pad, and the first metal interconnection line and the second metal interconnection line are disconnected; an electromigration metal line, wherein the electromigration metal line is located between the first metal interconnection line and the second metal interconnection line, so that when electromigration occurs, the electromigration metal line is electrically connected to the first metal interconnection line and the second metal interconnection line, respectively. The test structure provided by the present invention can effectively prevent free positive and negative charges from causing damage to the device structure, while also allowing the test to proceed normally.

[0064] Based on the same inventive concept, an embodiment of the present invention provides a testing method, referring to Figure 4 ,from Figure 4 As can be seen from the figure, the test method includes:

[0065] Step S1, providing a wafer, wherein the wafer comprises a test structure, wherein the test structure comprises a substrate, a device structure, a first metal interconnection line, a second metal interconnection line, and an electromigration metal line, wherein the device structure is formed on the substrate, the first metal interconnection line is electrically connected to the device structure, the electromigration metal line is located between the first metal interconnection line and the second metal interconnection line, and the first metal interconnection line, the second metal interconnection line, and the electromigration metal line are disconnected from each other;

[0066] Step S2, executing a production process, wherein the production process generates free positive charges and negative charges on the surface of the wafer, and the free positive charges and negative charges are not introduced into the first metal interconnection line through the second metal interconnection line, and further are not introduced into the device structure;

[0067] Step S3, applying current to the electromigration metal line to cause electromigration of the electromigration metal line, thereby causing the electromigration metal line to be electrically connected to the first metal interconnection line and the second metal interconnection line, respectively.

[0068] See below Figure 1 to Figure 3b The testing method provided in this embodiment is described in detail.

[0069] According to step S1, a wafer is provided, wherein the wafer includes a test structure, wherein the test structure includes a substrate, a device structure, a first metal interconnection line 131, a second metal interconnection line 132 and an electromigration metal line 141, wherein the device structure is formed on the substrate, the first metal interconnection line 131 is electrically connected to the device structure, and the electromigration metal line 141 is located between the first metal interconnection line 131 and the second metal interconnection line 132.

[0070] like Figure 1 and Figure 3a As shown, the first metal interconnection line 131 is disconnected from the second metal interconnection line 132 , the electromigration metal line 141 is located between the first metal interconnection line 131 and the second metal interconnection line 132 , and the electromigration metal line 141 is not connected to the first metal interconnection line 131 and the second metal interconnection line 132 .

[0071] The test structure is described in detail in the above description of the test structure of the present invention, which will not be described again. It should be noted that at this time, the third metal interconnection line 142, the first pad 133, the second pad 143 and the third pad 144 have not been formed.

[0072] The test structure can be located in the cutting path of the wafer, and the cutting path is located at the periphery of the chip area. After cutting along the cutting path, the chip can be obtained. The test structure does not occupy the area of ​​the chip area to avoid affecting the wiring design of the chip area, thereby avoiding affecting the performance of the chip and increasing the production cost.

[0073] The wafer includes the substrate and a dielectric layer 16 formed on the substrate, the gate oxide layer and the gate layer 12 in the MOS transistor or the gate oxide layer and the gate layer in the capacitor structure or the oxide layer, floating gate layer, inter-gate dielectric layer and control gate layer in the capacitor structure are all formed in the dielectric layer 16, and the first metal interconnection line 131, the second metal interconnection line 132, the electromigration metal line 141 and the subsequently formed third metal interconnection line 142 and the conductive plug 15 are also formed in the dielectric layer 16. The dielectric layer 16 can expose the metal interconnection line (not shown) connected to the second metal interconnection line 132 and the metal interconnection line (not shown) connected to the third metal interconnection line 142, so that the first pad 133, the second pad 143 and the third pad 144 formed subsequently are respectively electrically connected to the second metal interconnection line 132 and the third metal interconnection line 142 through the exposed metal interconnections. It should be noted that only Figure 3a to Figure 3b The dielectric layer 16 is shown schematically in FIG. Figure 1-2 The dielectric layer 16 is not shown.

[0074] According to step S2, a production process is performed, wherein the production process generates free positive and negative charges on the surface of the wafer.

[0075] Among them, the production process may include a deposition process or an etching process. Further, the deposition process may be a high-density plasma enhanced chemical vapor deposition process, and the etching process may be a plasma etching process, so that plasma bombardment is performed on the surface of the wafer during the production process, resulting in free positive and negative charges on the surface of the wafer.

[0076] When the device structure is a MOS transistor, if the free positive and negative charges are introduced into the device structure, the gate oxide layer will be damaged, thereby causing problems such as increased gate oxide leakage and increased turn-on voltage; when the device structure is a capacitor structure, if the free positive and negative charges are introduced into the device structure, the gate oxide layer or the inter-gate dielectric layer will be damaged, thereby causing problems such as increased leakage, weakened anti-breakdown capability and reduced life.

[0077] After the free positive and negative charges are introduced into the second metal interconnection line 132, since the first metal interconnection line 131 and the second metal interconnection line 132 are disconnected, the free positive and negative charges cannot be introduced into the first metal interconnection line 131 through the second metal interconnection line 132, and thus cannot be introduced into the device structure, thereby effectively avoiding the above-mentioned problems in the device structure, so that the device structure can be well protected.

[0078] Before subsequently applying current to the electromigration metal line 141, the testing method further includes:

[0079] Forming a third metal interconnection line 142 electrically connected to both ends of the electromigration metal line 141; wherein the third metal interconnection line 142 can be formed before or after performing the production process;

[0080] After the production process is performed, the first pad 133 , the second pad 143 and the third pad 144 are formed. The first pad 133 , the second pad 143 and the third pad 144 are formed on the surface of the dielectric layer 16 .

[0081] The second metal interconnection line 132 is electrically connected to the first pad 133 , and two ends of the electromigration metal line 141 are electrically connected to the second pad 143 and the third pad 144 through the third metal interconnection line 142 , respectively.

[0082] Step S3, applying current to the electromigration metal line 141 through the second pad 143 and the third pad 144, so that the electromigration metal line 141 undergoes electromigration, thereby electrically connecting the electromigration metal line 141 to the first metal interconnection line 131 and the second metal interconnection line 132, respectively (e.g., Figure 2 shown).

[0083] When current is applied to the electromigration metal line 141 through the second pad 143 and the third pad 144, the current flows from the anode to the cathode. If the current density in the electromigration metal line 141 is large enough, the electrons move from the cathode to the anode at a high speed under the drive of the electrostatic field, forming an electron wind. The metal ions diffuse directionally from the cathode to the anode under the drive of the electron wind, thereby electromigration occurs, and the metal ions accumulate at the end of the electromigration metal line 141 close to the anode, so that the accumulated metal ions diffuse to both sides of the electromigration metal line 141 close to the anode end, so that the width gradually increases. In addition, since the distance between the electromigration metal line 141 and the first metal interconnection line 131 and the second metal interconnection line 132 on both sides are very close, the increased width of the electromigration metal line 141 close to the anode end can be easily increased to contact the first metal interconnection line 131 and the second metal interconnection line 132 on both sides, thereby achieving electrical connection between the first metal interconnection line 131 and the second metal interconnection line 132.

[0084] like Figure 2 and Figure 3b As shown, when a positive voltage is applied to the second pad 143 and a negative voltage is applied to the third pad 144 or the third pad 144 is grounded, the second pad 143 acts as an anode and the third pad 144 acts as a cathode, and electromigration occurs at the top of the electromigration metal line 141, so that the metal ions accumulated at the top of the electromigration metal line 141 near one end of the second pad 143 diffuse and migrate toward the first metal interconnection line 131 and the second metal interconnection line 132 respectively, and the width increases to form an A1 region, so that the electromigration metal line 141 is electrically connected to the first metal interconnection line 131 and the second metal interconnection line 132 through the A1 region, thereby realizing electrical connection between the first metal interconnection line 131 and the second metal interconnection line 132.

[0085] It should be noted that, in other embodiments, a positive voltage may be applied to the third pad 144, and a negative voltage may be applied to the second pad 143 or the second pad 143 may be grounded. In this case, the third pad 144 serves as an anode and the second pad 143 serves as a cathode. Electromigration occurs at the top of the electromigration metal line 141 so that the A1 region is formed at the top of the electromigration metal line 141 near one end of the third pad 144.

[0086] Preferably, current is applied to the electromigration metal line 141 through the second pad 143 and the third pad 144, so that the current density in the electromigration metal line 141 is in the range of 0.3 MA / cm2 ~10MA / cm 2 .

[0087] The testing method further includes: performing a test on the device structure.

[0088] When the device structure is a MOS transistor, the test items may include an inversion test and an accumulation test to evaluate the quality of the gate oxide layer; when the device structure is a capacitor structure, it is necessary to perform an evaluation test on the quality of the gate oxide layer or the inter-gate dielectric layer to obtain reliability performance such as the breakdown time of the semiconductor device.

[0089] Among them, when the MOS transistor is an NMOS transistor, the inversion test is to apply a positive voltage to the gate layer 12 through the first pad 133 and the source region and the substrate are grounded to form an N channel, and then test to obtain electrical parameters such as saturation current, hot electron current carrying effect and turn-on resistance; the accumulation test is to apply a negative voltage to the gate layer 12 through the first pad 133 and the source region and the substrate are grounded to make holes accumulate at the junction of the substrate and the gate oxide layer, and then obtain parameters such as breakdown voltage. When the MOS transistor is a PMOS transistor, the inversion test is to apply a negative voltage to the gate layer 12 through the first pad 133 and the source region and the substrate are grounded, and the accumulation test is to apply a positive voltage to the gate layer 12 through the first pad 133 and the source region and the substrate are grounded, and the parameters obtained by the test are the same as above.

[0090] When the device structure is a capacitor structure, taking the capacitor structure as a PIP capacitor as an example, a positive voltage is applied to the control gate layer and a negative voltage is applied to the floating gate layer through the first pad 133, and a negative voltage is applied to the control gate layer and a positive voltage is applied to the floating gate layer through the first pad 133, so as to evaluate the quality of the inter-gate dielectric layer when voltages in different directions are applied, and obtain reliability performance parameters such as breakdown time.

[0091] As can be seen from the above content, in the test method of the present invention, since the first metal interconnection line 131 electrically connected to the device structure and the second metal interconnection line 132 electrically connected to the first pad 133 in the test structure are in a disconnected state before the production process is executed, the free positive and negative charges generated in the process of executing the production process cannot be introduced into the first metal interconnection line 131 through the second metal interconnection line 132, and then cannot be introduced into the device structure, thereby effectively avoiding the free positive and negative charges from causing damage to the device structure; and since the test structure includes the electromigration metal line 141, the third metal interconnection line 142, the second pad 143 and the third pad 144, and the two ends of the electromigration metal line 141 are respectively connected to the second pad 143 and the third pad 144 through the third metal interconnection line 142. The electromigration metal line 141 is electrically connected between the first metal interconnection line 131 and the second metal interconnection line 132, so that before the test is performed, when a current of a predetermined value is applied to the electromigration metal line 141 through the second pad 143 and the third pad 144, the electromigration metal line 141 can be electromigrated, and then the electromigration metal line 141 is electrically connected to the first metal interconnection line 131 and the second metal interconnection line 132 respectively under the action of electromigration, that is, the first metal interconnection line 131 and the second metal interconnection line 132 are electrically connected, and the first pad 133 is electrically connected to the device structure through the first metal interconnection line 131 and the second metal interconnection line 132, so that the voltage can be normally applied to the device structure through the first pad 133 subsequently, that is, the subsequent test can be carried out normally.

[0092] Furthermore, the test structure of the present invention can achieve good protection for the device structure without forming a protection diode, thereby simplifying the test structure and saving costs; and since the test structure does not include a protection diode, there will be no problem of the protection diode affecting tests such as inversion tests.

[0093] In summary, the present invention provides a migration test method, including: providing a wafer, the wafer including a test structure, the test structure including a substrate, a device structure, a first metal interconnection line, a second metal interconnection line and an electromigration metal line, the device structure is formed on the substrate, the first metal interconnection line is electrically connected to the device structure, the electromigration metal line is located between the first metal interconnection line and the second metal interconnection line, and the first metal interconnection line, the second metal interconnection line and the electromigration metal line are disconnected from each other; performing a production process, the production process generates free positive and negative charges on the surface of the wafer, and the free positive and negative charges are not introduced into the first metal interconnection line through the second metal interconnection line, and thus are not guided into the device structure; applying a current to the electromigration metal line so that the electromigration metal line undergoes electromigration, and then the electromigration metal line is electrically connected to the first metal interconnection line and the second metal interconnection line respectively. The test method provided by the present invention can effectively avoid the free positive and negative charges from damaging the device structure, and can also enable the test to proceed normally.

[0094] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A test structure, characterized in that: include: substrate; a device structure formed on the substrate; a first metal interconnection line, a second metal interconnection line and a first pad, wherein the first metal interconnection line is electrically connected to the device structure, the second metal interconnection line is electrically connected to the first pad, and the first metal interconnection line and the second metal interconnection line are disconnected, so that free positive and negative charges generated by the production process are not introduced into the first metal interconnection line through the second metal interconnection line, and are not guided into the device structure; an electromigration metal line, the electromigration metal line being located between the first metal interconnection line and the second metal interconnection line, so that when the electromigration metal line undergoes electromigration, the electromigration metal line is electrically connected to the first metal interconnection line and the second metal interconnection line, respectively, thereby enabling the device structure to be tested after a voltage is applied through the first pad; A third metal interconnection line, a second pad and a third pad, wherein both ends of the electromigration metal line are electrically connected to the second pad and the third pad respectively through the third metal interconnection line, so that electromigration occurs after current is applied to the electromigration metal line through the second pad and the third pad.

2. The test structure according to claim 1, characterized in that The first metal interconnection line and the device structure, the second metal interconnection line and the first pad, the two ends of the electromigration metal line and the third metal interconnection line, and the third metal interconnection line and the second pad and the third pad are all electrically connected through conductive plugs.

3. The test structure according to claim 1, characterized in that: The electromigration metal line is more susceptible to electromigration than the third metal interconnection line.

4. The test structure according to claim 3, characterized in that: The longitudinal cross-sectional area of ​​the electromigration metal line is smaller than that of the third metal interconnection line; or, the material of the electromigration metal line is more susceptible to electromigration than the material of the third metal interconnection line.

5. The test structure according to claim 2, characterized in that: A metal diffusion barrier layer is formed between two ends of the electromigration metal line and the conductive plug.

6. The test structure according to claim 1, characterized in that: One end of the first metal interconnection line and the second metal interconnection line close to the electromigration metal line extends toward both ends of the electromigration metal line.

7. The test structure according to any one of claims 1 to 6, characterized in that: The device structure is a MOS transistor, which includes a gate oxide layer and a gate layer formed in sequence on the substrate, and the MOS transistor is an NMOS transistor or a PMOS transistor; the device structure is a capacitor structure, which is composed of the substrate, the gate oxide layer and the control gate layer, or the capacitor structure includes an oxide layer, a floating gate layer, an inter-gate dielectric layer and a control gate layer formed in sequence on the substrate.

8. A testing method, characterized in that: include: A wafer is provided, wherein the wafer comprises a test structure, wherein the test structure comprises a substrate, a device structure, a first metal interconnection line, a second metal interconnection line and an electromigration metal line, wherein the device structure is formed on the substrate, the first metal interconnection line is electrically connected to the device structure, the electromigration metal line is located between the first metal interconnection line and the second metal interconnection line, and the first metal interconnection line, the second metal interconnection line and the electromigration metal line are disconnected from each other; performing a production process, wherein the production process generates free positive charges and negative charges on the surface of the wafer, and the free positive charges and negative charges are not introduced into the first metal interconnection line through the second metal interconnection line, and are not guided into the device structure; Applying current to the electromigration metal line to cause electromigration of the electromigration metal line, thereby causing the electromigration metal line to be electrically connected to the first metal interconnection line and the second metal interconnection line respectively; performing a test on the device structure; Wherein, before applying current to the electromigration metal line, the testing method further comprises: forming a third metal interconnection line electrically connected to both ends of the electromigration metal line; A first pad, a second pad and a third pad are formed, the second metal interconnection line is electrically connected to the first pad, and both ends of the electromigration metal line are electrically connected to the second pad and the third pad respectively through the third metal interconnection line, so that current is applied to the electromigration metal line through the second pad and the third pad, and voltage is applied to the device structure through the first pad for testing.

9. The testing method according to claim 8, characterized in that: Applying current to the electromigration metal line so that the current density in the electromigration metal line is in the range of 0.3 MA / cm 2 ~10MA / cm 2 .

10. The testing method according to claim 8, characterized in that: The production process includes a deposition process or an etching process.

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