A method and system for measuring nanolinewidth based on silicon crystal plane spacing

Abstract

This invention relates to a method and system for measuring nanolinewidth based on silicon crystal plane spacing. The method involves obtaining the pixel span of the silicon crystal plane spacing from an acquired image of the silicon crystal plane spacing, obtaining the half-width at half-maximum (WHM) pixel span from an acquired linewidth structure image, and then determining the nanolinewidth based on the silicon crystal plane spacing pixel span and the WHM pixel span. This improves the accuracy of nanolinewidth measurement and fills the technological gap in the prior art where nanolinewidth measurement based on silicon crystal plane spacing is not available.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of nanowire width measurement, and in particular to a nanowire width measurement method and system based on silicon crystal face spacing. BACKGROUND

[0002] Nanowire width is a key dimension value of integrated circuits, and the accuracy of the value has a huge impact on the performance of chip devices. Studies have shown that when the line width node of integrated circuits reaches 32nm or less, a 10% error in the line width value will cause the device to fail. Therefore, as the key node size of integrated circuits continues to shrink, the measurement of key dimensions in integrated circuits needs to achieve atomic level accuracy to ensure the effectiveness of the device. The 26th International Measurement Conference in 2018 suggested using silicon crystal face spacing as a method of reproducing the definition of meters, which provides a new idea and method for atomic level accuracy measurement of nanowire width in integrated circuits. At present, in the measurement of nanowire width based on a transmission electron microscope, a manual method is generally used for measurement, that is, a straight line is drawn in the image by the software of the instrument to measure the line width. However, the line cannot be accurately perpendicular to the line width structure, and the line position cannot be accurately at the half-height width position, and the like, which can only rely on the experience of the experimental personnel, and cannot guarantee the accuracy of the line width measurement. SUMMARY

[0003] To solve the above problems in the prior art, the present application provides a nanowire width measurement method and system based on silicon crystal face spacing.

[0004] To achieve the above purpose, the present application provides the following solutions:

[0005] A nanowire width measurement method based on silicon crystal face spacing, comprising:

[0006] obtaining a line width structure image in a nanowire width sample plate and a silicon crystal face spacing image of a single crystal silicon substrate;

[0007] obtaining a silicon crystal face spacing pixel span based on the silicon crystal face spacing image;

[0008] obtaining a half-height width pixel span based on the line width structure image;

[0009] determining the nanowire width based on the silicon crystal face spacing, the silicon crystal face spacing pixel span and the half-height width pixel span.

[0010] Preferably, the silicon crystal face spacing pixel span is obtained based on the silicon crystal face spacing image, and specifically comprises:

[0011] performing two-dimensional discrete Fourier transform on the silicon crystal face spacing image to obtain a diffraction image;

[0012] performing spot segmentation on the diffraction image using a threshold segmentation method to obtain a spot set;

[0013] determining the number of bright spots of each spot in the spot set, and taking the spot with the largest number of bright spots as a center spot;

[0014] determining the midpoint coordinates of the center spot;

[0015] taking a pair of spots symmetric to the center spot as a first spot and a second spot;

[0016] respectively determining the midpoint coordinates of the first spot and the midpoint coordinates of the second spot;

[0017] determining the distance from the first spot to the center spot according to the midpoint coordinates of the first spot and the midpoint coordinates of the center spot, and taking this distance as a first spot distance;

[0018] determining the distance from the second spot to the center spot according to the midpoint coordinates of the second spot and the midpoint coordinates of the center spot, and taking this distance as a second spot distance;

[0019] determining a silicon crystal face spacing pixel span according to the first spot distance and the second spot distance.

[0020] Preferably, the silicon crystal face spacing pixel span is:

[0021]

[0022] wherein N d is the silicon crystal face spacing pixel span, N is the pixel value of the silicon crystal face spacing image, d1 is the first spot distance, and d2 is the second spot distance.

[0023] Preferably, the method further comprises:

[0024] rotating the line width structure image around the image center point until the line width top and the line width bottom are both parallel to the x-axis; the image center point is the center point of the line width structure image;

[0025] determining the average intensity curve of the line width structure image in a specific rectangular frame, and performing spline interpolation processing on the average intensity curve; the specific rectangular frame is a rectangular frame that spans the line width structure profile in the line width structure image;

[0026] determining the intensity of the SiO2 layer and the intensity of the Pt layer in the nanowire width sample plate;

[0027] determining the half-intensity according to the intensity of the SiO2 layer and the intensity of the Pt layer;

[0028] The position corresponding to the half-intensity in the average intensity curve after the spline interpolation processing is taken as the line width boundary;

[0029] The specific rectangular frame is moved along the line width profile, and the average intensity curve of the line width structure image in the specific rectangular frame is determined and spline interpolation processing is performed on the average intensity curve, and a line width profile curve is extracted;

[0030] Based on the line width profile curve, the position of the top line width and the position of the bottom line width are determined respectively;

[0031] The half-height width position is determined based on the position of the top line width and the position of the bottom line width;

[0032] The pixel point corresponding to the line width profile curve at the half-height width position is determined;

[0033] The half-height width pixel span is determined based on the pixel point corresponding to the line width profile curve.

[0034] Preferably, the half-height width pixel span is:

[0035] N W =P R -P L +1;

[0036] Wherein, N W is the half-height width pixel span, P R is the pixel point corresponding to the first line width profile curve, and P L is the pixel point corresponding to the second line width profile curve.

[0037] Preferably, the nanowire width is

[0038] W=(d hkl / N d )×N W ;

[0039] Wherein, W is the nanowire width, N d is the silicon crystal plane spacing pixel span, N W is the half-height width pixel span, d hkl is the silicon {hkl} crystal plane spacing, and {hkl} is the Miller index of a group of crystal planes.

[0040] According to the specific embodiments provided by the present application, the following technical effects are disclosed:

[0041] The application provides a nanowire width measurement method based on silicon crystal face spacing, obtains a silicon crystal face spacing pixel span based on an obtained silicon crystal face spacing image, obtains a half-height width pixel span based on an obtained line width structure image, and then determines the nanowire width based on the silicon crystal face spacing, the silicon crystal face spacing pixel span and the half-height width pixel span. The method and system take the silicon crystal face spacing as a basic scale, establish a mathematical relationship between the silicon crystal face spacing, the silicon crystal face spacing pixel span and the pixel span of the line width structure, realize atomic level accuracy measurement of the nanowire width, reduce the uncertainty introduced by direct manual line measurement of the line width in the prior art, and improve the accuracy of the line width measurement.

[0042] Further, the application provides a nanowire width measurement system based on silicon crystal face spacing, which comprises:

[0043] a transmission electron microscope, which is used to collect a line width structure image in a nanowire width sample plate and a silicon crystal face spacing image of a single crystal silicon substrate;

[0044] a memory, which is used to store logical instructions; the logical instructions are used to implement the nanowire width measurement method based on silicon crystal face spacing according to any one of claims 1-6;

[0045] a processor, which is connected with the transmission electron microscope and the memory respectively, and is used to obtain the line width structure image and the silicon crystal face spacing image, and is used to call and execute the logical instructions to obtain the nanowire width.

[0046] Preferably, the processor comprises:

[0047] an image acquisition module, which is used to obtain a line width structure image in a nanowire width sample plate and a silicon crystal face spacing image of a single crystal silicon substrate;

[0048] a first pixel determination module, which is used to obtain a silicon crystal face spacing pixel span based on the silicon crystal face spacing image;

[0049] a second pixel determination module, which is used to obtain a half-height width pixel span based on the line width structure image;

[0050] a nanowire width determination module, which is used to determine the nanowire width based on the silicon crystal face spacing, the silicon crystal face spacing pixel span and the half-height width pixel span.

[0051] Preferably, the memory is a computer readable storage medium.

[0052] Preferably, the nanowire width measurement system based on silicon crystal face spacing further comprises a display.

[0053] The system provided by the application has the same technical effects as the nanowire width measurement method based on silicon crystal face spacing provided above, and thus will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 A flow chart of the nanowire width measurement method based on the silicon crystal face spacing provided by the present application;

[0056] Figure 2 A line width structure image schematic diagram of the 45nm line width sample provided by the embodiment of the present application;

[0057] Figure 3 A silicon crystal face spacing image schematic diagram of the single crystal silicon substrate in the 45nm line width sample provided by the embodiment of the present application;

[0058] Figure 4 A diffraction image schematic diagram obtained by performing two-dimensional discrete Fourier transform on the silicon crystal face spacing image of the single crystal silicon substrate in the 45nm line width sample provided by the embodiment of the present application;

[0059] Figure 5 An image schematic diagram after spot threshold segmentation provided by the embodiment of the present application;

[0060] Figure 6 A center coordinate position schematic diagram of the center spot and a pair of symmetric spots provided by the embodiment of the present application;

[0061] Figure 7 A position diagram of the center coordinate of the center spot and a pair of symmetric spots in the original spectrum provided by the embodiment of the present application;

[0062] Figure 8 A position schematic diagram of the line width structure image after rotation provided by the embodiment of the present application;

[0063] Figure 9 A schematic diagram of a specific rectangular frame across the line width structure contour provided by the embodiment of the present application;

[0064] Figure 10 A schematic diagram of the average intensity curve of the image in the specific rectangular frame and the intensity I SiO2 of the SiO2 layer and the intensity I Pt of the Pt layer, the half-intensity (I SiO2 +I Pt ) / 2 provided by the embodiment of the present application;

[0065] Figure 11A line width boundary position schematic diagram in a line width structure image corresponding to a half-intensity position in a strength curve provided by the embodiment of the present application is shown in the figure;

[0066] Figure 12 A line width profile curve schematic diagram provided by the embodiment of the present application is shown in the figure;

[0067] Figure 13 A pixel point schematic diagram provided by the embodiment of the present application is shown in the figure, in which the top line width, the bottom line width, the position of the half-height width, and the pixel points corresponding to the first line width profile curve and the second line width profile curve at the half-height width. DETAILED DESCRIPTION

[0068] The technical solutions in the embodiments of the present application will be clearly and completely described in the figures of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0069] The purpose of the present application is to provide a nanometer line width measurement method and system based on silicon crystal face spacing, which can improve the accuracy of nanometer line width measurement.

[0070] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the figures and specific embodiments.

[0071] As shown in the figure, the nanometer line width measurement method based on silicon crystal face spacing provided by the present application comprises: Figure 1

[0072] Step 100: obtaining a line width structure image in a nanometer line width sample plate and a silicon crystal face spacing image of a single crystal silicon substrate. When obtaining the two images, a transmission electron microscope is used to obtain them under the same parameters.

[0073] Step 101: obtaining a silicon crystal face spacing pixel span based on the silicon crystal face spacing image. The specific implementation process of this step can be:

[0074] Step 101-1: performing two-dimensional discrete Fourier transform on the silicon crystal face spacing image to obtain a diffraction image.

[0075] Step 101-2: using a threshold segmentation method to segment the spots in the diffraction image.

[0076] Step 101-3: each spot is composed of multiple bright spots, the distance between the bright spots in the same spot is obviously smaller than the distance between the bright spots in different spots, and the spots are extracted according to the distance between the bright spots.

[0077] ​Step 101-4: The spot with the largest number of bright spots is determined as the center spot, and the midpoint coordinates (x0, y0) of the center spot are calculated as:

[0078]

[0079] wherein C x is the horizontal coordinate set of the center spot, C y is the vertical coordinate set of the center spot.

[0080] Step 101-5: Take a pair of spots symmetric to the center spot (i.e., the first spot and the second spot), and calculate the midpoint coordinates (x1, y1) of the first spot and the midpoint coordinates (x2, y2) of the second spot, respectively:

[0081]

[0082] wherein D 1x and D 1y are the horizontal and vertical coordinate sets of the first spot, respectively, and D 2x and D 2y are the horizontal and vertical coordinate sets of the second spot, respectively.

[0083] Step 101-6: Calculate the distances of the center spot to the symmetric spots, i.e., the first spot distance d1 and the second spot distance d2, respectively:

[0084]

[0085] Step 101-7: Calculate the pixel span N d of the silicon crystal face spacing:

[0086]

[0087] wherein N is the pixel size of the silicon crystal face spacing image I Si .

[0088] Step 102: Obtain the half-height width pixel span based on the line width structure image. The specific implementation process of this step can be:

[0089] Step 102-1: Rotate the line width structure image around its own center point until the top and bottom of the line width structure are parallel to the x-axis direction.

[0090] Step 102-2: Determine the average intensity curve of the line width structure image within a certain rectangular frame, and perform spline interpolation processing on the average intensity curve. The certain rectangular frame is a rectangular frame that spans the line width structure profile in the line width structure image.

[0091] Step 102-3: Calculate the intensity I SiO2 of the SiO2 layer and the intensity IPt wherein the intensity I of the SiO2 layer SiO2 wherein the intensity I of the Pt layer Pt based on the minimum value of the Pt layer.

[0092] Step 102-4: the position corresponding to the half-intensity (I SiO2 + I Pt ) / 2 is taken as the line width boundary.

[0093] Step 102-5: the rectangular frame is moved along the line width profile, and the above steps 102-2 to 102-4 are repeated to extract the profile curve of the line width.

[0094] Step 102-6: for the extracted line width profile curve, the positions P TCD and P BCD of the top and bottom line widths are calculated respectively.

[0095] Step 102-7: the half-height width position P MCD =(P TCD +P BCD ) / 2 is calculated.

[0096] Step 102-8: the pixel points corresponding to the left and right profile curves at the half-height width, i.e. the pixel points P L and P R corresponding to the second and first line width profile curves are calculated.

[0097] Step 102-9: the pixel span of the half-height width is calculated as: N W =P R -P L +1.

[0098] Step 103: the nanowire width is determined based on the silicon crystal plane spacing, the pixel span of the silicon crystal plane spacing and the pixel span of the half-height width. Wherein the nanowire width value W=(d hkl / N d )×N W , wherein d hkl represents the silicon {hkl} crystal plane spacing. {hkl} represents the Miller indices of a group of crystal planes.

[0099] A specific embodiment is provided below to illustrate the implementation process of the above-mentioned nanowire width measurement method based on silicon crystal plane spacing.

[0100] It is assumed that the line width structure image and the silicon crystal plane spacing image of a 45nm line width sample have been obtained by using a transmission electron microscope under the same parameters, as shown in Figure 2 and Figure 3As shown, the two images are processed through the following steps to extract the line width structure and perform measurements.

[0101] First, a two-dimensional discrete Fourier transform is performed on the silicon crystal plane spacing image to obtain the diffraction image (e.g. Figure 4 As shown), and threshold segmentation is performed (as shown). Figure 5 (as shown) and calculate the center coordinates of the central spot and a pair of symmetrical spots, as shown. Figure 6 As shown, the corresponding coordinates are (0.0005, 0.0005), (-0.0229, -0.1655), and (0.0239, 0.1665). The distance between the symmetrical point and the center point is calculated to be 0.1677 pixels. -1 Calculate the reciprocal of the silicon interplanar spacing d. 111 The pixel span is 5.9644 pixels. The coordinates of the center spot and the center of a pair of symmetrical spots in the original spectrum are as follows: Figure 7 As shown.

[0102] Secondly, the linewidth structure image is rotated, and the position of the rotated image is as follows: Figure 8 As shown, calculate the rectangular frame (e.g.) Figure 9 The average intensity curve of the image shown is defined using half-intensity positioning linewidth boundaries. The intensity curve and the corresponding SiO2 layer intensity I are shown. SiO2 and the strength I of the Pt layer Pt Half-strength (I) SiO2 +I Pt ) / 2 Figure 10 As shown. The linewidth boundary contour curve can be extracted by moving the rectangle along the linewidth outline and repeating the linewidth boundary positioning process. The positions of the top linewidth, bottom linewidth, and half-height width are calculated as P. TCD =844.9151 pixels, P BCD =1583.6728 pixels, P MCD =(P TCD +P BCD ) / 2 = 1266.5500 pixels. Calculate the left and right contour curves of the line width at half-height (e.g., ...). Figure 12 The pixel P corresponding to (as shown) L =675.2248 pixels, P R =1509.2248 pixels, calculate the pixel span N of the full width at half maximum (FWHM). W =P R -P L +1 = 835.0000 pixels. The positions of the top line width, bottom line width, and half-height width, as well as the corresponding pixels on the first (left) and second (right) line width contour curves at the half-height width, are shown below. Figure 13The half-height position of the intensity curve corresponds to the boundary position of the line width in the line width structure image as shown in the figure. Figure 11

[0103] Finally, the nanowire width W = (d 111 / N d ) x N W = (0.3136 nm / 5.9644 pixel) x 835.0000 pixel = 43.9032 nm is calculated.

[0104] Further, the present application also provides a nanowire width measurement system based on silicon crystal face spacing, which comprises:

[0105] A transmission electron microscope is used to collect the line width structure image in the nanowire width sample plate and the silicon crystal face spacing image of the single crystal silicon substrate.

[0106] A memory is used to store logical instructions. The logical instructions are used to implement the nanowire width measurement method based on silicon crystal face spacing as claimed in any one of claims 1-6. The memory can be a computer readable storage medium.

[0107] A processor is connected with the transmission electron microscope and the memory respectively, and is used to obtain the line width structure image and the silicon crystal face spacing image, and to call and execute the logical instructions to obtain the nanowire width.

[0108] Further, the processor used in the system comprises:

[0109] An image acquisition module is used to obtain the line width structure image in the nanowire width sample plate and the silicon crystal face spacing image of the single crystal silicon substrate.

[0110] A first pixel determination module is used to obtain the silicon crystal face spacing pixel span based on the silicon crystal face spacing image.

[0111] A second pixel determination module is used to obtain the half-height width pixel span based on the line width structure image.

[0112] A nanowire width determination module is used to determine the nanowire width based on the silicon crystal face spacing, the silicon crystal face spacing pixel span and the half-height width pixel span.

[0113] In addition, the nanowire width measurement system based on silicon crystal face spacing provided by the present application further comprises a display for displaying the data information required by the user.

[0114] ​The various embodiments described in this specification are presented for the purpose of illustrating the principles of the present application and its best mode of operation. Each of the embodiments described in this specification has been provided for the purpose of illustration only and the various embodiments are not intended to limit the present application in any way unless otherwise specifically indicated. The same parts and / or features of the various embodiments described in this specification can be referenced using the same reference numerals for the ease of understanding of the present application.

[0115] The principles and implementations of the present application have been described in the above embodiments, which are only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, the specific implementation and application range of the present application can be changed according to the idea of the present application. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A method for measuring the width of a nanowire based on the interplanar spacing of silicon crystals, characterized by, The method comprises the following steps: obtaining a line width structure image in a nanometer line width sample plate and a silicon crystal face spacing image of a single crystal silicon substrate; obtaining a silicon crystal face spacing pixel span based on the silicon crystal face spacing image; obtaining a half-height width pixel span based on the line width structure image; determining a nanometer line width based on the silicon crystal face spacing, the silicon crystal face spacing pixel span and the half-height width pixel span; wherein the silicon crystal face spacing pixel span is obtained based on the silicon crystal face spacing image, and specifically comprises the following steps: performing two-dimensional discrete Fourier transform on the silicon crystal face spacing image to obtain a diffraction image; segmenting the diffraction image into a spot set using a threshold segmentation method; determining the number of bright spots of each spot in the spot set, and taking the spot with the largest number of bright spots as a center spot; determining the midpoint coordinates of the center spot; taking a pair of spots symmetrical to the center spot as a first spot and a second spot; determining the midpoint coordinates of the first spot and the second spot, respectively; determining the distance from the first spot to the center spot according to the midpoint coordinates of the first spot and the midpoint coordinates of the center spot, and taking this distance as a first spot distance; determining the distance from the second spot to the center spot according to the midpoint coordinates of the second spot and the midpoint coordinates of the center spot, and taking this distance as a second spot distance; determining the silicon crystal face spacing pixel span according to the first spot distance and the second spot distance; obtaining the half-height width pixel span based on the line width structure image, specifically comprising the following steps: rotating the line width structure image around the image center point until the top and bottom of the line width are parallel to the x-axis; the image center point is the center point of the line width structure image; determining the average intensity curve of the line width structure image in a specific rectangular frame, and performing spline interpolation processing on the average intensity curve; the specific rectangular frame is a rectangular frame across the line width structure profile in the line width structure image; determining the intensity of the SiO2 layer and the intensity of the Pt layer in the nanometer line width sample plate; determining the half-intensity according to the intensity of the SiO2 layer and the intensity of the Pt layer; taking the position corresponding to the half-intensity in the average intensity curve after spline interpolation processing as the line width boundary; moving the specific rectangular frame along the line width profile, and returning to execute "determining the average intensity curve of the line width structure image in a specific rectangular frame, and performing spline interpolation processing on the average intensity curve" to extract the line width profile curve; determining the position of the top line width and the position of the bottom line width based on the line width profile curve, respectively; determining the half-height width position based on the position of the top line width and the position of the bottom line width; determining the pixel point corresponding to the line width profile curve at the half-height width position; determining the half-height width pixel span based on the pixel point corresponding to the line width profile curve; the half-height width pixel span is: N W = P R - P L + 1 ; wherein N W is the half-width pixel span, P R is the pixel point corresponding to the first line width profile curve. L is the pixel point corresponding to the second line width profile curve.

2. The method of claim 1, wherein the method is performed on a silicon wafer. the silicon crystal face spacing pixel span is: where N d is the pixel span of the silicon lattice spacing, N is the pixel value of the silicon lattice spacing image, d1 is the first spot distance, and d2 is the second spot distance.

3. The method of claim 1, wherein the method is performed on a silicon wafer having a plurality of nanowires formed thereon. the nanometer line width is W = (d hkl / N d ) x N W ; where W is the nanowire width, N d is the pixel span of the silicon lattice spacing, N W is the pixel span of the half-width, d hkl is the silicon {hkl} lattice spacing, and {hkl} is the Miller indices of a family of crystal planes.

4. A nanowire width measurement system based on silicon lattice spacing, comprising: The method comprises the following steps: a transmission electron microscope is used to collect a line width structure image in a nanometer line width sample plate and a silicon crystal face spacing image of a single crystal silicon substrate; A memory is configured to store logic instructions; the logic instructions are configured to implement the method for measuring the nanowire width based on the silicon crystal face spacing as claimed in any one of claims 1-3; A processor is connected with the transmission electron microscope and the memory respectively, and is configured to acquire the line width structure image and the silicon crystal face spacing image, and to call and execute the logic instructions to obtain the nanowire width.

5. The silicon crystal face spacing based nanowire width measurement system of claim 4, wherein, The processor comprises: An image acquisition module is configured to acquire the line width structure image in the nanowire width sample plate and the silicon crystal face spacing image of the single crystal silicon substrate; A first pixel determination module is configured to obtain the silicon crystal face spacing pixel span based on the silicon crystal face spacing image; A second pixel determination module is configured to obtain the half-height width pixel span based on the line width structure image; A nanowire width determination module is configured to determine the nanowire width based on the silicon crystal face spacing, the silicon crystal face spacing pixel span and the half-height width pixel span.

6. The silicon crystal face spacing based nanowire width measurement system of claim 5, wherein, The memory is a computer readable storage medium.

7. The silicon crystal face spacing based nanowire width measurement system of claim 5, wherein, Further comprising: A display.

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