A low power all-MOS self-biased current reference source

Abstract

The present invention relates to a low-power all-MOS self-biased current reference source, belonging to the technical field of reference sources. All circuit elements in the reference source circuit adopt MOS tubes, wherein NMOS tubes working in the deep linear region are used to replace the resistors in the traditional current reference source circuit, and the sizes of PMOS tubes are made uniform. The present invention has the advantages of simple structure, five start-up circuits, small temperature coefficient, low power consumption, etc.

Description

Technical Field

[0001] The invention belongs to the technical field of reference sources and relates to a low-power all-MOS self-bias current reference source. Background Art

[0002] The reference current source is a high-precision, low-temperature-coefficient current source used as a current reference for other circuits in analog integrated circuits. As a key circuit unit of analog integrated circuits, it is widely used in operational amplifiers, A / D converters, and D / A converters. In high-performance analog circuits, high-quality, high-stability current and voltage bias circuits must be supported. The performance of the reference current source will directly affect the circuit's power consumption, power supply rejection ratio, open-loop gain, and temperature characteristics.

[0003] Among the existing current reference source technologies, common ones include reference sources based on BJT tubes (bipolar junction transistors) and MOSFET.

[0004] Among them, the reference source based on BJT tube has a higher threshold and needs to match a higher power supply voltage, which cannot meet the low power consumption requirements in the design of ultra-low power analog / mixed signal integrated circuits. In addition, resistors are also needed in the BJT tube reference source circuit. Under the condition of low power consumption, the resistance value of the resistor also needs to be large, but a large resistor also means a large space occupation, which will undoubtedly increase the area of ​​the chip.

[0005] The MOSFET-based reference source has a good low power consumption effect because the MOS tube in the circuit works in the subthreshold region. Its basic circuit diagram is as follows: Figure 1 As shown in the figure, NMOS tubes MN1 and MN2 in the circuit both work in the subthreshold region, and PMOS tubes MP1 to MP3 have the same width-to-length ratio, so I out =I ref , due to the existence of resistance R s , so the gate-source voltage V gs If the ratio of the size of MN1 to the size of MN2 is assumed to be K, the resistor R s The voltage is I out R s , ignoring the influence of body effect, that is, V THN1 =V THN2 , by I ref R s =V GSN2 -V GSN1 We can get:

[0006]

[0007] Therefore, The magnitude of this current is only related to the aspect ratio of the transistor and the resistance, and the current temperature characteristics are also only affected by the temperature characteristics of the resistance and the thermal voltage U T If the resistor is not temperature compensated, the output current I ref The temperature characteristics will also be poor.

[0008] In this case, the theoretical method is to make the temperature coefficient of the resistor offset the temperature coefficient of the carrier mobility, so that the temperature characteristics of the output reference current can be improved. However, in actual processes, it is difficult to achieve a resistor that matches the temperature characteristics of the carrier mobility. Therefore, the method adopted is to use two different resistors and achieve mutual offset with the temperature coefficient of the carrier mobility by matching the resistance values. This also brings the same problem. Under the requirements of low-power circuits, the resistor needs to be very large to meet the requirements, which takes up a lot of chip area, and if the resistor is not large enough, it will bring the problem of high power consumption. Summary of the invention

[0009] In view of this, the object of the present invention is to provide a low-power all-MOS self-biased current reference source, which uses MOS tubes to replace resistors in the circuit to reduce circuit power consumption and reduce the occupied area.

[0010] In order to achieve the above object, the present invention provides the following technical solutions:

[0011] A low-power all-MOS self-bias current reference source, comprising PMOS tubes MP1-MP5 and NMOS tubes MN1-MN6;

[0012] The source of the PMOS tube MP1 is connected to the power supply, and its drain is respectively connected to the drain and gate of the NMOS tube MN3 and the gate of MN4. The gate of MP1 is respectively connected to the drain of the PMOS tube MP2, the gate of MP5 and the drain of the NMOS tube MN1; the source of the NMOS tube MN3 is respectively connected to the source of MN1 and the drain of MN4; the source of the NMOS tube MN4 is grounded; the source of the PMOS tube MP2 is connected to the power supply, and its gate is respectively connected to the gate of MP3 and the gate of MP5; the PMOS tube M The source of P3 is connected to the power supply, and its drain is respectively connected to the gate of the NMOS tube MN1 and the gate and drain of MN2; the source of the NMOS tube MN2 is respectively connected to the source of MN5 and the drain of MN6; the source of the PMOS tube MP4 is connected to the power supply, and its gate is connected to the gate of MP5, and the drain of MP4 is respectively connected to the drain and gate of the NMOS tube MN5 and the gate of MN6; the source of the NMOS tube MN6 is grounded; the source of the PMOS tube MP5 is connected to the power supply, and its drain serves as the output end of the reference current source.

[0013] Preferably, the PMOS transistors MP1 to MP5 have the same size.

[0014] Preferably, the NMOS transistors MN1, MN2, MN5 and MN6 operate in the subthreshold region, the NMOS transistor MN3 operates in the saturation region, and the NMOS transistor MN4 operates in the deep linear region.

[0015] Preferably, the PMOS transistors MP2 and MP3 form a current mirror structure with a ratio of 1:1; the NMOS transistors MN1 and MN2 also form a current mirror structure with a ratio of 2:1.

[0016] The beneficial effects of the present invention are as follows: the present invention adopts a MOS tube working in a deep linear region to replace the resistor in the traditional reference circuit, thereby solving the disadvantages of the traditional self-biased current reference source outputting a small current and occupying a large area, greatly reducing the chip area, and being very suitable for use in low-power circuits; the method of multiplying the thermovoltage of a positive temperature coefficient with the electron mobility of a negative temperature coefficient is used to obtain a reference current with a low temperature coefficient. The circuit structure of the present invention is simple, without a startup circuit, without a loop, with a small temperature coefficient and extremely low power consumption. .

[0017] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0019] Figure 1 It is a traditional self-biased current reference source circuit;

[0020] Figure 2 It is a low power all-MOS self-biased current reference source circuit. DETAILED DESCRIPTION

[0021] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0022] like Figure 2As shown, it is a low-power full-MOS self-biased current reference source of the present invention, and the reference source circuit includes PMOS tubes MP1-MP5 and NMOS tubes MN1-MN6. The source of the PMOS tube MP1 is connected to the power supply, and its drain is respectively connected to the drain and gate of the NMOS tube MN3 and the gate of MN4, and the gate of MP1 is respectively connected to the drain of the PMOS tube MP2, the gate of MP5 and the drain of the NMOS tube MN1; the source of the NMOS tube MN3 is respectively connected to the source of MN1 and the drain of MN4; the source of the NMOS tube MN4 is grounded; the source of the PMOS tube MP2 is connected to the power supply, and its gate is respectively connected to the gate of MP3 and the gate of MP5; the PMOS tube The source of MP3 is connected to the power supply, and the drain thereof is respectively connected to the gate of the NMOS tube MN1 and the gate and drain of MN2; the source of the NMOS tube MN2 is respectively connected to the source of MN5 and the drain of MN6; the source of the PMOS tube MP4 is connected to the power supply, and the gate thereof is connected to the gate of MP5, and the drain of MP4 is respectively connected to the drain and gate of the NMOS tube MN5 and the gate of MN6; the source of the NMOS tube MN6 is grounded; the source of the PMOS tube MP5 is connected to the power supply, and the drain thereof serves as the output end of the reference current source.

[0023] In the above MOS tubes, the PMOS tubes MP1 to MP5 have the same size, the NMOS tubes MN1, MN2, MN5 and MN6 work in the subthreshold region, the NMOS tube MN3 works in the saturation region, and the NMOS tube MN4 works in the deep linear region. The present invention uses the NMOS tube MN4 in the deep linear region to replace the resistor in the traditional current reference source circuit, and at the same time uses the NMOS tube MN3 in the saturation region to act as a current source, so that the drain of MN4 forms a voltage difference.

[0024] According to the circuit structure, the reference current I ref It can be expressed as:

[0025]

[0026] In the formula, μ n Indicates the electron mobility of the NMOS tube, C ox Represents the gate oxide capacitance per unit area, S N Indicates the width-to-length ratio of the MOS tube, U T It is known from the above formula that the appropriate current can be obtained by adjusting the size of the MOS tube. n It is negatively correlated with temperature and can be expressed as:

[0027]

[0028] In the formula, T0 is the reference temperature, μ0 is the electron mobility at T0, T is the absolute temperature, and m is the temperature index, which is between 1 and 2. It is also known that the thermal voltage U T It is positively correlated with temperature and can be expressed as:

[0029]

[0030] Therefore, I ref The relationship between the temperature T can be expressed as I ref Taking the derivative with respect to temperature T, we get:

[0031]

[0032] Since the value of m is between 1 and 2, the temperature coefficient of this reference source is very small.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A low power all-MOS self-biased current reference source, characterized in that: It includes PMOS tubes MP1 to MP5 and NMOS tubes MN1 to MN6; The source of the PMOS tube MP1 is connected to the power supply, and its drain is respectively connected to the drain and gate of the NMOS tube MN3 and the gate of MN4. The gate of MP1 is respectively connected to the drain of the PMOS tube MP2, the gate of MP5 and the drain of the NMOS tube MN1; the source of the NMOS tube MN3 is respectively connected to the source of MN1 and the drain of MN4; the source of the NMOS tube MN4 is grounded; the source of the PMOS tube MP2 is connected to the power supply, and its gate is respectively connected to the gate of MP3 and the gate of MP5; the PMOS tube M The source of P3 is connected to the power supply, and its drain is respectively connected to the gate of NMOS tube MN1 and the gate and drain of MN2; the source of NMOS tube MN2 is respectively connected to the source of MN5 and the drain of MN6; the source of PMOS tube MP4 is connected to the power supply, and its gate is connected to the gate of MP5, and the drain of MP4 is respectively connected to the drain and gate of NMOS tube MN5 and the gate of MN6; the source of NMOS tube MN6 is grounded; the source of PMOS tube MP5 is connected to the power supply, and its drain serves as the output end of the reference current source; The PMOS tubes MP2 and MP3 form a current mirror structure with a ratio of 1:1; the NMOS tubes MN1 and MN2 form a current mirror structure with a ratio of 2:1; The reference current output by the self-biased current reference source is expressed as: In the formula, μ n Indicates the electron mobility of the NMOS tube, which is negatively correlated with temperature. ox Represents the gate oxide capacitance per unit area, U T Represents thermal voltage, which is positively correlated with temperature; S N1 ~S N6 They respectively represent the width-to-length ratios of the NMOS tubes MN1 to MN6; therefore, the output reference current can be adjusted by adjusting the size of the NMOS tube.

2. The self-bias current reference source according to claim 1, characterized in that: The NMOS tube MN3 operates in the saturation region.

3. The self-bias current reference source according to claim 1, characterized in that: The NMOS tube MN4 operates in the deep linear region.

4. The self-bias current reference source according to claim 1, characterized in that: The sizes of the PMOS tubes MP1 to MP5 are the same.

5. The self-bias current reference source according to claim 1, characterized in that: The NMOS transistors MN1, MN2, MN5 and MN6 operate in the subthreshold region.

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