Trench filling method

Abstract

This application discloses a trench filling method, comprising: placing a wafer on a vacuum chuck of a CVD machine, the wafer being used to integrate a trench-type MOS device, the wafer having trenches formed on its surface, and an oxide layer formed on the wafer and trench surfaces; the vacuum chuck being disposed in the reaction chamber of the CVD machine; preheating the wafer, during which the pressure in the reaction chamber of the CVD machine is a first pressure value; evacuating the reaction chamber of the CVD machine, activating the vacuum adsorption function of the vacuum chuck, and increasing the pressure in the reaction chamber of the CVD machine to a second pressure value; evacuating the reaction chamber of the CVD machine; increasing the pressure in the reaction chamber of the CVD machine to a third pressure value, the third pressure value being greater than the second pressure value; and depositing a silicon dioxide layer on the wafer using a CVD process. This application, by performing stress relief pretreatment on the wafer using a vacuum chuck, can effectively increase the adsorption capacity of the chuck, ensuring a tight fit between the wafer and the chuck.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, and more specifically to a trench filling method. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs, referred to as "MOS" in this application) are electronic devices used in analog and digital circuits.

[0003] Among them, trench MOS devices, due to their lower on-resistance and gate-drain charge density, exhibit lower conduction and switching losses, as well as faster switching speeds. They are commonly used as power devices (also known as "electronic power devices") in consumer electronics, new energy vehicles, servers, and control equipment. Within trench MOS devices, shielded gate trench (SGT) MOS devices have even lower switching losses and can be used as core power control components.

[0004] As semiconductor devices become smaller and smaller, when the critical dimension of the trench in an SGT MOS device is less than 0.5 micrometers (μm), a silicon dioxide layer can be filled in the trench using a high aspect ratio process chemical vapor deposition (HARP CVD) process to overcome the phenomenon of premature trench closure during the growth process.

[0005] As the critical dimensions of SGT MOS devices decrease, their trench depths also increase, leading to a greater impact of wafer warpage on the devices. When wafer warpage is high, insufficient contact between the wafer edge and the heating element during CVD processing can result in lower edge temperatures and consequently, thicker edge thicknesses. Therefore, a trench filling method is urgently needed to address the issue of excessive wafer edge thickness after CVD processing due to high wafer warpage. Summary of the Invention

[0006] This application provides a trench filling method that solves the problem of uneven device uniformity caused by large wafer warpage in the fabrication methods of trench-type MOS devices provided in related technologies. The method includes:

[0007] A wafer is placed on a vacuum chuck of a CVD machine. The wafer is used to integrate trench MOS devices. A trench is formed on the wafer. An oxide layer is formed on the surface of the wafer and the trench. The vacuum chuck is located in the reaction chamber of the CVD machine.

[0008] The wafer is preheated, and during the preheating process, the pressure in the reaction chamber of the CVD machine is a first pressure value.

[0009] The reaction chamber of the CVD machine is evacuated, and the vacuum suction function of the vacuum chuck is activated.

[0010] Increase the pressure in the reaction chamber of the CVD machine to a second pressure value;

[0011] The reaction chamber of the CVD machine is evacuated.

[0012] The pressure value in the reaction chamber of the CVD machine is increased to a third pressure value, which is greater than the second pressure value;

[0013] A silicon dioxide layer is deposited on the wafer using a CVD process.

[0014] In some embodiments, the preheating treatment of the wafer includes:

[0015] Increase the pressure in the reaction chamber of the CVD machine to the first pressure value;

[0016] The wafer is lifted from the vacuum chuck and preheated. After the preheating process is completed, the wafer is lowered and placed back into the vacuum chuck.

[0017] In some embodiments, the first pressure value is greater than the second pressure value and less than the third pressure value.

[0018] In some embodiments, the deposition of a silicon dioxide layer on the wafer via a CVD process includes:

[0019] The silicon dioxide layer is deposited on the wafer using a HARP CVD process.

[0020] In some embodiments, the trench-type MOS device is an SGT MOS device.

[0021] In some embodiments, the warpage of the wafer is greater than 50 micrometers.

[0022] In some embodiments, the oxide layer is formed by a furnace tube oxidation process.

[0023] The technical solution of this application has at least the following advantages:

[0024] By preheating the wafer in the CVD machine after forming the trench and the oxide layer on the trench surface during the fabrication of trench-type MOS devices, and then performing stress relief pretreatment on the wafer using a vacuum chuck before CVD processing, the adsorption capacity of the chuck can be effectively increased, making the wafer and the chuck fit tightly together. This reduces the temperature difference of the wafer in the CVD process and improves the uniformity of the CVD process. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1 This is a flowchart of a trench filling method provided in an exemplary embodiment of this application;

[0027] Figure 2 This is a cross-sectional diagram of a wafer placed on a vacuum chuck;

[0028] Figure 3 This is a cross-sectional diagram of the wafer after it has been lifted from the vacuum chuck.

[0029] Figure 4 This is a schematic diagram of the cross-section after stress relief. Detailed Implementation

[0030] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0033] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0034] refer to Figure 1 It illustrates a flowchart of a trench filling method provided in an exemplary embodiment of this application, which can be applied to the fabrication process of trench-type MOS devices (which may be SGT MOS devices), such as... Figure 1 As shown, the method includes:

[0035] Step S1: Place the wafer on the vacuum chuck of the CVD machine.

[0036] The wafer is used to integrate a trench-type MOS device, on which trenches are formed (the trenches are used to form trench gates), and an oxide layer is formed on the wafer and trench surfaces (the oxide layer is formed on the wafer and trench surfaces through a furnace tube oxidation process). A vacuum chuck is placed in the reaction chamber of the CVD machine.

[0037] refer to Figure 2 This illustrates a cross-sectional schematic of a wafer being placed on a vacuum chuck. For example, such as... Figure 2 As shown, wafer 200 is warped, therefore it is placed on a vacuum chuck (which includes a heated tray 300 and a lift pin 310, as shown). Figure 3 When placed on the heating tray 300 as shown, its edge area cannot be in contact with the heating tray 300. In this embodiment, the height difference Δh between the edge area and the center area is used as the warpage of the wafer (in the calculation, the difference between the highest and lowest areas when the wafer is placed can be used as the warpage). The wafer involved in this embodiment has a warpage greater than 50 micrometers (μm).

[0038] Step S2: The wafer is preheated. During the preheating process, the pressure in the reaction chamber of the CVD machine is the first pressure value.

[0039] For example, step S2 includes, but is not limited to: increasing the pressure in the reaction chamber of the CVD machine to a first pressure value; lifting the wafer from the vacuum chuck and preheating it (the preheating time is 50 to 100 seconds and the preheating pressure is 150 to 450 Torr); and then lowering the wafer back into the vacuum chuck.

[0040] Step S3: Vacuum the reaction chamber of the CVD machine, activate the vacuum suction function of the vacuum chuck, and increase the pressure in the reaction chamber of the CVD machine to the second pressure value.

[0041] Step S4: Vacuum treatment is performed on the reaction chamber of the CVD machine.

[0042] refer to Figure 3 It shows a schematic cross-sectional view of the wafer after it has been lifted from the heated tray; Reference Figure 4 It shows a schematic diagram of the cross-section after stress relief. For example... Figure 3 As shown, the ejector pin 310 extends to lift the wafer 200 for preheating; as Figure 4 As shown, after preheating, the pressure in the reaction chamber is increased to the second pressure value, and then a vacuum treatment is performed to release the stress of the wafer 200, reduce its warpage, and allow its edges to fit more tightly with the heating tray 300.

[0043] Step S5: Increase the pressure in the reaction chamber of the CVD machine to the third pressure value.

[0044] In this embodiment, the first pressure value is greater than the second pressure value and less than the third pressure value, and the third pressure value is greater than the second pressure value. The first pressure value can be from 150 torr to 450 torr, the second pressure value can be from 50 to 300 torr, and the third pressure value can be from 450 to 800 torr.

[0045] refer to Figures 2 to 4 The bottom of the vacuum suction cup is connected to the vacuum tubing. Figures 2 to 4 (Not shown in the image) The vacuum suction cup can be made to have a vacuum adsorption function by opening the valve of the vacuum pipeline, and then the pressure value in the reaction chamber of the CVD machine can be slowly increased to the second pressure value, and then the vacuum can be re-evacuated, and then the pressure value in the reaction chamber of the CVD machine can be increased to the third pressure value.

[0046] Step S6: Deposit a silicon dioxide layer on the wafer using a CVD process.

[0047] Once the pressure in the reaction chamber of the CVD machine stabilizes for a preset time (e.g., 15 to 60 seconds), a silicon dioxide layer can be deposited using the HARP CVD process. After deposition, a vacuum process is performed, and then the vacuum suction function of the vacuum chuck is turned off to transfer the wafer out of the reaction chamber.

[0048] In summary, in the embodiments of this application, by preheating the wafer in the CVD machine after forming the trench and the oxide layer on the trench surface during the fabrication of the trench-type MOS device, and then performing stress relief pretreatment on the wafer using a vacuum chuck before performing the CVD process, the adsorption capacity of the chuck can be effectively increased, making the wafer and the chuck fit tightly together, thereby reducing the temperature difference of the wafer in the CVD process and improving the uniformity of the CVD process.

[0049] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for filling a trench, characterized in that, include: A wafer is placed on a vacuum chuck of a CVD machine. The wafer is used to integrate trench MOS devices. A trench is formed on the wafer. An oxide layer is formed on the surface of the wafer and the trench. The vacuum chuck is located in the reaction chamber of the CVD machine. Increase the pressure in the reaction chamber of the CVD machine to a first pressure value; The wafer is lifted from the vacuum chuck and preheated. After the preheating process is completed, the wafer is lowered and placed back into the vacuum chuck. The reaction chamber of the CVD machine is evacuated, and the vacuum suction function of the vacuum chuck is activated. Increase the pressure in the reaction chamber of the CVD machine to a second pressure value; The reaction chamber of the CVD machine is evacuated. The pressure value in the reaction chamber of the CVD machine is increased to a third pressure value, the third pressure value being greater than the second pressure value, and the first pressure value being greater than the second pressure value and less than the third pressure value; A silicon dioxide layer is deposited on the wafer using a CVD process.

2. The method according to claim 1, characterized in that, The deposition of a silicon dioxide layer on the wafer via a CVD process includes: The silicon dioxide layer is deposited on the wafer using a HARP CVD process.

3. The method according to claim 1 or 2, characterized in that, The trench-type MOS device is an SGT MOS device.

4. The method according to claim 3, characterized in that, The warpage of the wafer is greater than 50 micrometers.

5. The method according to claim 4, characterized in that, The oxide layer is formed through a furnace tube oxidation process.

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