Semiconductor device and method for manufacturing a semiconductor device

Abstract

A semiconductor device includes an active region having a semiconductor element and a surface electrode provided by a wiring electrode material and connected to the semiconductor element on a side adjacent to a surface of the semiconductor chip, and a pad setting region having a pad provided by the wiring electrode material. The pad setting region overlaps the active region in a direction perpendicular to the surface of the semiconductor chip. In a portion where the pad setting region overlaps the active region, the pad is disposed on the surface electrode through an isolation insulating film, the wiring electrode material is two layers, and a double-layer wiring electrode structure is provided. In a portion where the active region does not overlap the pad setting region, the surface electrode has a single-layer wiring electrode structure composed of a single layer of the wiring electrode material.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device having pads on the surface of a semiconductor chip, and a method for manufacturing the semiconductor device. Background Technology

[0002] There exists a semiconductor device in which semiconductor elements, such as switching elements, are formed in a semiconductor chip, as described in, for example, JP 2017-204570 A. In such a semiconductor device, an active region operating as a semiconductor element can be arranged over a wide area, including the center of the semiconductor chip. A region of the semiconductor chip distinct from the active region, specifically, a region adjacent to the active region and along one side of the semiconductor chip, can be used as a pad placement area for setting pads. Summary of the Invention

[0003] In the aforementioned semiconductor devices, since the active region and the pad area are separate regions, the pad area cannot contribute to the operation of the switching element. As a result, due to the area of ​​the pad area, the ratio of the active region to the total area of ​​the semiconductor chip decreases, making it difficult to reduce the on-resistance of the semiconductor element sufficiently.

[0004] Therefore, the inventors of this disclosure have discovered a structure in which the active region extends into the area below the pads in the pad placement area, so that the area below the pads is also used as an active region. With this configuration, the ratio of the active region to the total area of ​​the semiconductor chip can be increased, and the on-resistance of the semiconductor device can be reduced.

[0005] In a semiconductor device with this structure, the semiconductor element is formed in the region below the pad placement area. Therefore, wiring electrode material for forming the pads is arranged in an overlapping manner on the wiring electrode material for forming electrodes connected to the semiconductor element. That is, the wiring electrodes connected to the semiconductor element are disposed as lower wiring electrodes in the first layer, while upper wiring electrodes in the second layer are stacked on top of the lower wiring electrodes. Furthermore, in the pad placement area, the upper wiring electrodes need to be insulated from the lower wiring electrodes. Therefore, it is conceivable to place an insulating film between the lower and upper wiring electrodes in the pad placement area, and to interconnect the lower and upper wiring electrodes in the portion of the active region that does not overlap with the pad placement area.

[0006] However, due to careful research conducted by the inventors of this application, it has been discovered that the overlapping arrangement of wiring electrode materials leads to an excessive increase in thickness, resulting in an increase in warping or deformation of the semiconductor chip at high temperatures.

[0007] The purpose of this disclosure is to provide a semiconductor device that can suppress the increase of semiconductor chip warpage while reducing on-resistance, and a method for manufacturing the device.

[0008] According to one aspect of this disclosure, a semiconductor device is provided by a semiconductor chip and includes: an active region having a semiconductor element and a surface electrode, wherein the surface electrode is provided by a wiring electrode material and is connected to the semiconductor element on a side adjacent to the surface of the semiconductor chip; and a pad placement region having pads provided by the wiring electrode material. The pad placement region is arranged to overlap the active region in a direction perpendicular to the surface of the semiconductor chip. In the portion where the pad placement region overlaps with the active region, the pads are disposed on the surface electrode by an insulating film, such that the wiring electrode material is two-layered, to provide a double-layer wiring electrode structure. In the portion where the active region does not overlap with the pad placement region, the surface electrode has a single-layer wiring electrode structure composed of a single layer of wiring electrode material.

[0009] In this configuration, the surface electrode, which has the largest area in the portion made of wiring electrode material on the side adjacent to the semiconductor chip surface, has a single-layer wiring electrode structure. That is, the area where pads are placed has a double-layer wiring electrode structure because the pads are stacked on top of the surface electrode. On the other hand, the area where only surface electrodes are provided, i.e., the area where the surface electrodes do not overlap with the pads, has a single-layer wiring electrode structure, where the wiring electrode material is not delaminated. Therefore, the increase in semiconductor chip warpage at high temperatures can be suppressed. Thus, in a configuration that provides a wide range of active regions by forming semiconductor elements in the area below the pad placement area, on-resistance can be reduced, and the increase in semiconductor chip warpage can be suppressed.

[0010] According to one aspect of this disclosure, a method for manufacturing a semiconductor device provided by a semiconductor chip, wherein a semiconductor element is formed on a semiconductor substrate, includes: forming a surface electrode in an active region; forming an insulating film on the surface electrode; and forming a pad in a pad placement area overlapping the active region. During the formation of the surface electrode, the surface electrode is formed in the active region where the semiconductor element is formed, thereby connecting the surface electrode to the semiconductor element. The formation of the surface electrode includes (i) forming the semiconductor element on the semiconductor substrate; (ii) after forming the semiconductor element, forming an interlayer insulating film adjacent to a surface of the semiconductor substrate; (iii) forming a contact hole in the interlayer insulating film; (iv) forming a lower layer wiring electrode over the interlayer insulating film including the interior of the contact hole using a first layer wiring electrode material; and (v) patterning the lower layer wiring electrode to form the surface electrode. The formation of the pad includes: (vi) forming an upper layer wiring electrode on the insulating film using a second layer wiring electrode material; and (vii) patterning the upper layer wiring electrode to form a pad in the pad placement area. The formation of the pads also includes: (viii) removing the upper wiring electrode formed on the surface electrode in the portion of the active region that does not overlap with the pad setting area, so that the surface electrode has a single-layer wiring electrode structure composed of the lower wiring electrode; (ix) leaving the upper wiring electrode formed on the surface electrode in the portion of the active region that overlaps with the pad setting area, so that the pad is arranged on the surface electrode, thereby forming a double-layer wiring electrode structure composed of the lower wiring electrode and the upper wiring electrode.

[0011] In this method, during pad formation, the upper wiring electrode formed above the surface electrode is removed from the portion of the active region that does not overlap with the pad placement area, thus giving the surface electrode a single-layer wiring electrode structure consisting of lower wiring electrodes. In the portion where the active region overlaps with the pad placement area, the pad is positioned above the surface electrode, forming a double-layer wiring electrode structure consisting of lower and upper wiring electrodes. Therefore, this method can produce a semiconductor device that can suppress increased semiconductor chip warpage by providing a wide range of active region configurations through the formation of semiconductor elements in the region below the pad placement area, while simultaneously reducing on-resistance. Attached Figure Description

[0012] The purpose, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. Wherein:

[0013] Figure 1 This is a cross-sectional view of the power module according to the first embodiment;

[0014] Figure 2A It is set in Figure 1 The diagram shows the top layout of the semiconductor chips in the power module.

[0015] Figure 2BThis is a top layout diagram of a semiconductor chip, in which the region with a double-layer wiring electrode structure is shown in cross-section.

[0016] Figure 3 In the configuration of forming vertical MOSFETs in a semiconductor chip, along Figure 2A A cross-sectional view taken from line III-III in the diagram;

[0017] Figure 4 In the configuration of forming vertical MOSFETs in a semiconductor chip, along Figure 2A A cross-sectional view taken from line IV-IV in the image;

[0018] Figure 5 This is a cross-sectional view of a semiconductor chip used as a comparative example, corresponding to along... Figure 2A A cross-sectional view taken from line III-III in the diagram;

[0019] Figure 6 This is a cross-sectional view of a semiconductor chip used as a comparative example, corresponding to along... Figure 2A A cross-sectional view taken from line IV-IV in the image;

[0020] Figure 7 This is a graph showing the simulation results of the on-resistance of the semiconductor chips of the first embodiment and the comparative example;

[0021] Figure 8 This is a flowchart illustrating a semiconductor device manufacturing method;

[0022] Figure 9 This is a top layout diagram of a semiconductor chip, in which the region with a double-layer wiring electrode structure is shown in cross-section.

[0023] Figure 10 This is a cross-sectional view of a semiconductor chip according to the second embodiment, corresponding to along... Figure 2A Cross-sectional view taken from line III-III;

[0024] Figure 11 This is a top layout diagram of a semiconductor chip according to the fourth embodiment; and

[0025] Figure 12 This is a top layout diagram of a semiconductor chip according to the fifth embodiment. Detailed Implementation

[0026] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following description of the embodiments, identical or equivalent components are indicated by the same reference numerals.

[0027] (First Embodiment)

[0028] The first embodiment will be described. First, refer to... Figure 1The configuration of the semiconductor device according to this embodiment applied to the power module will be described as an example.

[0029] Figure 1 The power module shown incorporates a semiconductor chip 10 and serves, for example, as a switching element for driving a motor. The semiconductor chip 10 corresponds to the semiconductor device of this embodiment. Specifically, the power module includes the semiconductor chip 10, a heat sink 20, a heat sink 30, etc. The heat sinks 20 and 30 are bonded to the semiconductor chip 10 using a bonding material 50, which includes first to third bonding materials 50a to 50c. The semiconductor chip 10, heat sink 20, and heat sink 30 are encapsulated in a molding resin 60.

[0030] like Figure 1 As shown, the lower surface of the semiconductor chip 10 is bonded to the upper surface of the heat sink 20 via a first bonding material 50a. The heat sink 20 is provided by a stack of metal layers 21, 22, and 23 stacked on top of each other. The metal layer 23 is bonded to the lower surface of the semiconductor chip 10 via the first bonding material 50a. Furthermore, the upper surface of the semiconductor chip 10 is bonded to the heat sink 30 via a second bonding material 50b and a third bonding material 50c. The heat sink 30 is provided by a stack of metal layers 31, 32, and 33 stacked on top of each other. The metal layer 33 is divided into multiple connecting portions 33a and 33b. The connecting portions 33a and 33b are bonded to the upper surface of the semiconductor chip 10 via the second bonding material 50b and the third bonding material 50c, respectively.

[0031] As will be described later, the connection portion 33a is connected to the source electrode 113 of the semiconductor chip 10. The source electrode 113 corresponds to the main surface electrode arranged in the active region Rb of the semiconductor chip 10, such as... Figure 2A As shown. The main surface electrode will be simply referred to as the surface electrode. Similarly, the connection portion 33b is connected to each of the pads 12a to 12e, which are arranged in the pad setting area Re of the semiconductor chip 10. Although Figure 1 Only one connection portion 33b is shown, but the power module includes multiple connection portions 33b corresponding to the number of pads 12a to 12e. The connection portion 33a has a lead portion (not shown) and is electrically connected to an external device via the lead portion extending from the molding resin 60. Each of the connection portions 33b also has a lead portion (not shown) and is electrically connected to an external device via the lead portion extending from the molding resin 60. The metal layer 23 also has a lead portion (not shown) and is electrically connected to an external device via the lead portion extending from the molding resin 60.

[0032] In this embodiment, for example, the bonding material 50, which includes the first to third bonding materials 50a to 50c, is made of a bonding metal such as lead-free solder, which is a conductive material, or a conductive adhesive. The semiconductor chip 10, the heat sink 20, and the heat sink 30 are physically and electrically connected to each other through the bonding material 50.

[0033] With this configuration, electrical connection and heat dissipation with external devices are achieved on the upper surface of the semiconductor chip 10 via second and third bonding materials 50b and 50c and a heat sink 30. Similarly, electrical connection and heat dissipation with external devices are achieved on the lower surface of the semiconductor chip 10 via a first bonding material 50a and a heat sink 20.

[0034] Semiconductor chip 10 is a semiconductor device having a semiconductor substrate in which semiconductor elements are formed. The semiconductor substrate is made of silicon carbide (SiC) or the like. For example, semiconductor chip 10 has a rectangular thin plate shape. Semiconductor chip 10 can be made of materials other than SiC. However, in the case of SiC, compared to the case where semiconductor chip 10 is made of another material, since semiconductor chip 10 is provided with semiconductor elements that require high voltage resistance, the temperature of semiconductor chip 10 may be higher, and the effects due to warpage of semiconductor chip 10 may increase. Therefore, this disclosure is preferably applicable to the case where semiconductor chip 10 is made of SiC.

[0035] Examples of semiconductor elements formed in semiconductor chip 10 include vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) and vertical insulated-gate bipolar transistors (IGBTs). In this embodiment, semiconductor chip 10 is formed with a vertical MOSFET, the detailed structure of which will be described later.

[0036] A connection portion 33a is bonded to a portion of the upper surface of the semiconductor chip 10, and multiple connection portions 33b are connected to multiple portions of the semiconductor chip 10 located outside the portions of the semiconductor chip 10 connected to the connection portion 33a. The surface electrode (i.e., the source electrode 113 of the vertical MOSFET) disposed in the active region Rb of the semiconductor chip 10 is connected to the connection portion 33a. Pads 12a to 12e disposed in the pad setting region Re of the semiconductor chip 10 are connected to the connection portion 33b. Although... Figure 1 Only one connection portion 33b is shown, but the number of connection portions 33b is as many as the pads 12a to 12e. On the other hand, a back electrode, i.e., the drain electrode 114 in the case of a vertical MOSFET, is formed on the back side of the semiconductor chip 10. The surface of the back electrode is completely connected to the metal layer 23 of the heat sink 20.

[0037] In the heat sink 20, metal layers 21 and 23 are disposed on both sides of an insulating layer 22 and are insulated by the insulating layer 22. Metal layers 21 and 23 are each made of a metal with a high thermal conductivity, such as copper, to achieve high heat dissipation. Since metal layers 21 and 23 are insulated from each other, the heat sink 20 is exposed from the molding resin 60 on the metal layer 21 side to facilitate heat dissipation, while the metal layer 23 is insulated from the outside.

[0038] In the heat sink 30, metal layers 31 and 33 are disposed on both sides of an insulating layer 32 and are insulated by the insulating layer 32. Metal layers 31 and 33 are each made of a metal with a high thermal conductivity, such as copper, to achieve high heat dissipation. Since metal layers 31 and 33 are insulated from each other, the heat sink 30 is exposed from the molding resin 60 on the metal layer 31 side to facilitate heat dissipation, while the metal layer 33 is insulated from the outside. The metal layer 33 is divided into multiple parts to form connecting portions 33a and 33b. In a conventional configuration, connecting portion 33b is provided by a bonding wire. When connecting portion 33b is provided by a portion of the metal layer 33 contained in the heat sink 30, high heat dissipation can be achieved.

[0039] The molding resin 60 encapsulates the semiconductor chip 10, heat sink 20, heat sink 30, etc. One surface of heat sink 20 and one surface of heat sink 30 are exposed from the molding resin 60. Similarly, although not shown, one end of the lead portion of each of the metal layers 23 and 33 is exposed from the molding resin 60 and can be electrically connected to an external device.

[0040] Next, the detailed structure of the semiconductor chip 10 of the semiconductor device configured as described above will be described.

[0041] like Figure 2A and 2B As shown, the semiconductor chip 10 has a generally rectangular plate shape. The semiconductor chip 10 has an internal region Ra, an active region Rb, a connection region Rc, an outer peripheral region Rd, and a pad placement region Re.

[0042] The internal region Ra is the area encompassing the central portion of the semiconductor chip 10. The internal region Ra is the area from which the source electrode 113 is exposed. The source electrode 113 corresponds to the surface electrode, which will be described later. The exposed portion of the source electrode 113 serves as the source pad 11.

[0043] The active region Rb is a region of the semiconductor chip 10 in which semiconductor elements are activated. In this embodiment, a vertical MOSFET is formed as a semiconductor element in the active region Rb. The active region Rb is formed up to a predetermined distance inward from the outer edge of the semiconductor chip 10, while surrounding the inner region Ra. In this embodiment, the active region Rb is a rectangular region.

[0044] The connection region Rc is the area disposed between the active region Rb and the peripheral region Rd. The connection region Rc has, for example, a rectangular frame shape and includes a gate wiring layer 120 (which will be described later) that forms the gate liner, etc.

[0045] The peripheral region Rd is a region that surrounds the entire outer edge of the semiconductor chip 10, so as to surround the active region Rb and the connection region Rc. The peripheral region Rd is provided with a peripheral voltage-resistant structure, etc., and in this embodiment has a rectangular frame shape.

[0046] The pad setting area Re is the region where various pads 12a to 12e are set. The pad setting area Re is a region along a portion of the active region Rb, for example, along one side of a rectangular shape of the active region Rb. Figure 2A In the example shown, the pad setting area Re is the region along the underside of the active region Rb. The pad setting area Re is formed to overlap with the active region Rb in the top view when the semiconductor chip 10 is viewed along the normal direction. That is, the pad setting area Re overlaps with the active region Rb in a direction orthogonal to the surface of the semiconductor chip 10.

[0047] In this embodiment, by Figure 2A The area indicated by the double-dotted line is the connection region Rc. The region inside the connection region Rc is the active region Rb, and the region outside the connection region Rc is the peripheral region Rd. Furthermore, Figure 2A The area surrounded by the dashed line is the pad setting area Re.

[0048] Furthermore, a temperature sensing element region 13, in which a temperature sensing element is formed, is disposed in a pad placement region Re that overlaps with the active region Rb of the semiconductor chip 10. The temperature sensing element region 13 is able to understand the temperature rise caused by the semiconductor device based on the temperature detected by the temperature sensing element.

[0049] Pads 12a to 12e are disposed in the pad setting area Re. In this embodiment, the pad setting area Re is from... Figure 2A Starting from the left side, it includes a cathode pad 12a, an anode pad 12b, a gate pad 12c, a first sensing pad 12d, and a second sensing pad 12e. These pads 12a to 12e are electrically connected to corresponding portions of the vertical MOSFET disposed in the active region Rb, and to corresponding portions of the temperature sensing element disposed in the temperature sensing element region 13. Since these pads 12a to 12e are connected to the connection portion 33b, they can be electrically connected to one or more external devices via the leads provided in the connection portion 33b.

[0050] Semiconductor chip 10 has such Figure 3 and Figure 4 The configuration is shown in the cross-sectional view, and the vertical MOSFET is formed in the active region Rb.

[0051] The semiconductor chip 10 includes an n+ type substrate 101 made of a semiconductor material such as Si or SiC. An n- type low-concentration layer 102 having an impurity concentration lower than that of the n+ type substrate 101 is epitaxially grown on the main surface of the n+ type substrate 101.

[0052] <Structure of the active region Rb>

[0053] In the active region Rb, such as Figure 3 and Figure 4 As shown, a JFET portion 102a is formed in the n-type low-concentration layer 102. The JFET portion 102a is configured as a strip and extends in a direction that is longitudinal, away from the n+ type substrate 101. The n-type low-concentration layer 102 including the JFET portion 102a can have the same impurity concentration. However, in this embodiment, the JFET portion 102a has a higher impurity concentration than other portions of the n-type low-concentration layer 102, thereby further reducing the on-resistance.

[0054] A p-type first deep layer 103 is formed between adjacent JFET portions 102a. The first deep layer 103 is also provided in a strip shape, having a longitudinal direction. The JFET portions 102a and the first deep layer 103 have the same thickness.

[0055] On the JFET portion 102a and the first deep layer 103, a current diffusion layer 104 and a second deep layer 105 are alternately and repeatedly disposed. The longitudinal direction of the current diffusion layer 104 and the second deep layer 105 intersects the longitudinal direction of the JFET portion 102a and the first deep layer 103. The current diffusion layer 104 has a width greater than that of the second deep layer 105. The second deep layer 105 is connected to the first deep layer 103. A p-type base region 106 is formed on the current diffusion layer 104 and the second deep layer 105. In addition, an n+ type source region 107 and a p+ type contact region 108 are formed on the p-type base region 106. The n+ type source region 107 is formed on a portion of the p-type base region 106 corresponding to the current diffusion layer 104, while the p+ type contact region 108 is formed on a portion of the p-type base region 106 corresponding to the second deep layer 105.

[0056] The gate trench 109 is formed to pass through the p-type base region 106 and the n+ type source region 107 and reach the current diffusion layer 104. The p-type base region 106 and the n+ type source region 107 are configured to contact the side surfaces of the gate trench 109. The gate trench 109 is formed in a linear arrangement. Figure 3 The horizontal direction in the text refers to the width direction. Figure 3 The vertical direction is the depth direction, and the direction perpendicular to both the width and depth directions is the longitudinal direction. Figure 3Only two gate trenches 109 are shown in the diagram. However, a plurality of gate trenches 109 are arranged at fixed intervals in the horizontal direction, and each of the gate trenches 109 is arranged in a strip shape and inserted between the second deep layers 105.

[0057] A portion of the p-type base region 106 located on the side surface of the gate trench 109 acts as a channel region connecting the n+ type source region 107 and the current diffusion layer 104 during vertical MOSFET operation. A gate insulating film 110 is formed on the inner wall surface of the gate trench 109, including the channel region. A gate electrode 111, composed of doped polysilicon, is formed on the surface of the gate insulating film 110, and the gate insulating film 110 and the gate electrode 111 are embedded in the gate trench 109. As a result, a trench gate structure is formed.

[0058] like Figure 4 As shown, the trench gate structure along the... Figure 2A Extending in the direction corresponding to the horizontal direction. For example... Figure 3 As shown, multiple trench gate structures are along with Figure 2A The vertical direction corresponds to the orientation arrangement. Although not shown, the trench gate structure is formed in... Figure 2A The n+ type source region 107 is formed on the side of the gate trench 109. The n+ type source region 107 is formed in the active region Rb, but not outside the active region Rb. Therefore, the channel region is formed only within the active region Rb.

[0059] An interlayer insulating film 112 is formed on the respective surfaces of the n+ type source region 107, the p+ type contact region 108, and the trench gate structure. Furthermore, a source electrode 113, corresponding to the surface electrode, is formed in the active region Rb on the interlayer insulating film 112. The source electrode 113 is formed by patterning a lower wiring electrode made of wiring electrode material in the first layer. From the source electrode 113, an upper wiring electrode made of wiring electrode material is removed in the second layer. Therefore, the source electrode 113 has a single-layer wiring electrode structure.

[0060] Contact holes 112a are formed in the interlayer insulating film 112 at positions corresponding to the n+ type source region 107 and the p+ type contact region 108. For example... Figure 3 As shown, the source electrode 113 is electrically contacted with the n+ type source region 107 and the p+ type contact region 108 through the contact hole 112a.

[0061] A drain electrode 114 is formed on the rear surface of the n+ type substrate 101, specifically on the rear side opposite to the side where the source electrode 113 is formed on the n+ type substrate 101. The drain electrode 114 corresponds to the back electrode and is electrically connected to the n+ type substrate 101. As described above, a vertical MOSFET with an n-channel reverse trench gate structure is configured. A vertical MOSFET with multiple cells is disposed in the active region Rb. Figure 3 As shown, the surface of the semiconductor chip 10 is covered with a passivation film 115, and a portion of the passivation film 115 corresponding to the source electrode 113 is removed and opened. The region of the passivation film 115 that is opened corresponding to the source electrode 113 is the internal region Ra, and the exposed portion of the source electrode 113 serves as the source pad 11.

[0062] In addition, such as Figure 4 As shown, the portion of the active region Rb that overlaps with the pad setting region Re and the portion of the active region Rb that does not overlap with the pad setting region Re have a substantially similar configuration. However, in the portion of the active region Rb that overlaps with the pad setting region Re, i.e., in the overlapping region, an insulating film 116 is disposed on the surface of the source electrode 113, and pads 12a to 12e are formed on the insulating film 116. Figure 4 A cross-section of the portion where gate pad 12c is located is shown. Other pads 12a, 12b, 12d, and 12e are similarly formed on the source electrode 113, interspersed with insulating films 116. Pads 12a to 12e are formed by patterning upper-layer wiring electrodes (which are the wiring electrodes of the second layer). Therefore, as... Figure 2B As shown, in the portion where the active region Rb overlaps with the pad setting region Re, the semiconductor chip 10 has a double-layer wiring electrode structure, wherein the source electrode 113 and the pads 12a to 12e are stacked on top of each other.

[0063] The portion of the passivation film 115 that corresponds to the pads 12a to 12e in the pad setting area Re is also removed to form an opening. Therefore, the connection portion 33b can be connected to the pads 12a to 12e.

[0064] For example, a temperature sensing diode is formed as a temperature sensing element in temperature sensing element region 13 (which is configured to overlap with active region Rb). The temperature sensing diode is formed, for example, by implanting p-type or n-type impurity ions into polysilicon to form a multi-stage PN diode. The cathode of the temperature sensing diode is connected to cathode pad 12a, and the anode of the temperature sensing diode is connected to anode pad 12b, thereby outputting an electrical signal corresponding to the temperature of semiconductor chip 10.

[0065] Other pads 12c to 12e located in the pad setting area Re are electrically connected to corresponding portions of the vertical MOSFET. Gate pad 12c is electrically connected to the gate electrode 111 via a gate wiring layer 120 forming the gate liner, as will be described later. Therefore, the gate voltage is applied to the gate electrode 111 via gate pad 12c. Gate wiring layer 120 is formed, for example, in a rectangular frame shape surrounding the active region Rb in the connection region Rc, i.e., near the outer edge of the semiconductor chip 10, and wiring extends to the vicinity of gate pad 12c. First sensing pad 12d and second sensing pad 12e are connected to the source electrode 113 of the vertical MOSFET. Specifically, most of the vertical MOSFETs formed in the plurality of cells of the active region Rb serve as main cells, supplying current to loads such as motors through their source and drain electrodes, but a portion of the vertical MOSFETs serves as sensing cells for measuring the current flowing through the main cells. The first sensing pad 12d is connected to the source electrode 113 on one side of the sensing unit and outputs the current flowing between the source and drain electrodes of the vertical MOSFET on one side of the sensing unit to the outside, thereby enabling the measurement of the current flowing in the main unit. The second sensing pad 12e is connected to the source electrode 113 on one side of the main unit and outputs the source potential to the outside through the second sensing pad 12e.

[0066] <Structure of the connection region Rc>

[0067] like Figure 3 As shown, similarly in the connection region Rc, the JFET portion 102a and the first deep layer 103 are formed on the n-type low-concentration layer 102, extending to a position close to the outer peripheral region Rd. However, the current diffusion layer 104 is not disposed on these layers, and only the second deep layer 105 is formed. Furthermore, no trench gate structure is formed; only the p-type base region 106 and the p+ type contact region 108 are formed on the second deep layer 105.

[0068] Furthermore, a gate lead-out 111a, made of doped polysilicon and led out from the gate 111, is formed on the gate insulating film 110 formed on the p-type base region 106 and the p+ type contact region 108. An interlayer insulating film 112 is formed to cover the gate lead-out 111a, and a gate wiring layer 120 is formed on the interlayer insulating film 112. The gate wiring layer 120 constitutes the gate liner and is wired in a rectangular frame shape to, for example, surround the active region Rb and connect to the gate pad 12c. A contact hole 112b is formed in the interlayer insulating film 112 at a position corresponding to the gate wiring layer 120, and the gate wiring layer 120 and the gate lead-out 111a are electrically connected to each other through the contact hole 112b.

[0069] Additionally, a hole extraction layer 130 is formed on the interlayer insulating film 112 in a portion closer to the outer peripheral region Rd than the gate wiring layer 120. A contact hole 112c is formed in the interlayer insulating film 112 at a position corresponding to the hole extraction layer 130, and the hole extraction layer 130 is electrically connected to the p+ type contact region 108 through the contact hole 112c.

[0070] like Figure 2B and Figure 3 As shown, the gate wiring layer 120 and the via extraction layer 130 formed in the connection region Rc are also formed by patterning a lower wiring electrode, which serves as a wiring electrode in the first layer, and an upper wiring electrode, which serves as a wiring electrode in the second layer. In this embodiment, both the gate wiring layer 120 and the via extraction layer 130 have a double-layer wiring electrode structure made of a lower wiring electrode and an upper wiring electrode.

[0071] To electrically isolate pads 12a to 12e from the source electrode 113, an insulating film 116 is formed between the lower and upper wiring electrodes. Therefore, in the gate wiring layer 120 and the via extraction layer 130, the insulating film 116 formed between the lower and upper wiring electrodes is removed, thereby electrically connecting the lower and upper wiring electrodes. In this way, since both the gate wiring layer 120 and the via extraction layer 130 have a double-layer wiring electrode structure, wiring resistance can be reduced.

[0072] In Figure 3 and Figure 4 In the different cross-sections shown, the gate wiring layer 120 is connected to the gate pad 12c, and the via extraction layer 130 is connected to a portion having a ground potential, such as the second sensing pad 12e.

[0073] <Structure of Rd in the peripheral region>

[0074] In the outer peripheral region Rd, the p-type base region 106 and the second deep layer 105 are removed, forming a groove 140. Multiple p-type guard rings 150 are arranged at positions corresponding to the bottom surface of the groove 140 to surround the active region Rb. Due to the presence of the p-type guard rings 150, the equipotential line can extend further to the outside of the active region Rb and terminate, thereby reducing electric field concentration and ensuring the withstand voltage of the outer peripheral region Rd.

[0075] In the outer peripheral region Rd, the surface is completely covered by a passivation film 115 for protection. As described above, a power module is configured with a semiconductor chip 10 corresponding to the semiconductor device of this embodiment.

[0076] For example, when a voltage of approximately 10V is applied to the drain electrode 114 through the metal layer 23, the source electrode 113 is grounded through the connection portion 33a, and a predetermined voltage is applied to the gate electrode 111 through the connection portion 33b, the power module operates. That is, when a gate voltage is applied to the gate electrode 111, a channel region is formed in the portion of the p-type base region 106 that contacts the trench gate structure. As a result, the vertical MOSFET is turned on, and operation is performed to allow current to flow between the source and drain electrodes.

[0077] Even when a high voltage is applied to the drain electrode 114, the first deep layer 103 is fixed at the source potential through the second deep layer 105 and the p-type base region 106, thus suppressing the equipotential line from climbing onto the trench gate structure. Furthermore, since the outer peripheral region Rd is provided with an outer peripheral voltage-resistant structure such as a p-type guard ring 150, the equipotential line is further guided to the outer peripheral side, thereby reducing electric field concentration. Therefore, a vertical MOSFET capable of withstanding high voltages can be realized.

[0078] When the vertical MOSFET operates as described above, the temperature of the semiconductor chip 10 may rise. As a result, if the thickness of each portion provided by the wiring electrodes is large, the warpage of the semiconductor chip 10 may increase. In this embodiment, the thickness of the source pad 11 (i.e., the source electrode 113, which is a pad formed by opening the passivation film 115 with maximum area) is reduced. Therefore, it is possible to suppress the increase in warpage of the semiconductor chip 10 at high temperatures.

[0079] Specifically, the source electrode 113, gate wiring layer 120, via extraction layer 130, and pads 12a to 12e are provided by patterning a lower wiring electrode (which is a wiring electrode in the first layer) and / or an upper wiring electrode (which is a wiring electrode in the second layer). In this embodiment, the gate wiring layer 120 and the via extraction layer 130 have a double-layer wiring electrode structure made of a lower wiring electrode and an upper wiring electrode, while the source electrode 113 has a single-layer wiring electrode structure formed by removing the upper wiring electrode and retaining the lower wiring electrode. Additionally, the pads 12a to 12e have a single-layer wiring electrode structure made of an upper wiring electrode.

[0080] Thus, on the front surface side of the semiconductor chip 10, the source electrode 113 (which has the largest area among the components made of wiring electrode material) has a single-layer wiring structure. In other words, even though the portions where pads 12a to 12e are provided have a double-layer wiring electrode structure with pads 12a to 12e stacked on the source electrode 113, only the portions where the source electrode 113 is provided have a single-layer wiring electrode structure and do not have a stacked structure. Therefore, it is possible to suppress the increase of warpage of the semiconductor chip 10 at high temperatures.

[0081] Therefore, by forming a semiconductor element below the pad setting area Re to use a wide range of semiconductor chips 10 as the active area Rb, the increase in warpage of the semiconductor chip 10 can be suppressed, while the on-resistance is also suppressed. By suppressing the increase in warpage of the semiconductor chip 10, the degradation of semiconductor element characteristics caused by warpage can be suppressed, and the on-resistance can be further reduced. Moreover, since heat can also be dissipated through the connection portion 33b, even if the active area Rb is set to overlap with the pad setting area Re, the heat generated in this part can be dissipated through the connection portion 33b.

[0082] The structure of this embodiment was actually manufactured, and the change in on-resistance was examined against the structures of this embodiment and a comparative example where the source electrode 113 also has a double-layer wiring electrode structure. The structure actually manufactured in this embodiment is... Figure 3 and Figure 4 The structure shown. The comparative example has... Figure 5 and Figure 6 The structure shown. That is to say, as... Figure 5 and Figure 6 As shown, not only pads 12a to 12e, but also source electrode 113, gate wiring layer 120 and via extraction layer 130 have a double-layer wiring electrode structure.

[0083] Figure 7 The evaluation results of the on-resistance are shown. Specifically, the gate voltage was adjusted to achieve a predetermined current value between the source and drain electrodes, while 10V was applied to the drain electrode 114 and the source electrode 113 was set to ground potential. Under these conditions, the on-resistance was measured for each case. In this case, four vertical MOSFETs with different characteristics were fabricated for each case. As a result, regardless of the characteristics of the vertical MOSFETs, the on-resistance in this embodiment was reduced by approximately 5% compared to the comparative example with a double-layer wiring electrode structure for the source electrode 113. Based on the evaluation results, it is understood that the on-resistance can be further reduced by employing the structure of this embodiment. The presumed reason is as follows.

[0084] In the comparative example with a double-layer wiring electrode structure, an oxide layer is formed on the surface of the lower wiring electrode, and the contact resistance between the lower and upper wiring electrodes increases, resulting in an increase in on-resistance. Conversely, in the structure of this embodiment, even if an oxide layer is formed on the source electrode 113 when forming the insulating film 116 as will be described later, the oxide layer can be removed when the upper wiring electrode formed on the oxide layer is removed. Therefore, it is assumed that the contact resistance of the source electrode 113 is reduced, and thus the on-resistance is reduced.

[0085] Next, a method for manufacturing the semiconductor chip 10 configured as described above, i.e., a method for manufacturing a semiconductor device, will be described. It should be noted that in the method for manufacturing a semiconductor device, the processes for forming semiconductor elements, forming the interlayer insulating film 112, and forming contact holes 112a to 112c can be performed using any technique and can be executed using known techniques. Therefore, only the processes following the formation of contact holes 112a to 112c will be described below.

[0086] First, such as Figure 8 As shown in the flowchart, after forming the semiconductor device, an interlayer insulating film 112 is formed, and contact holes 112a to 112c (P1) are formed in the interlayer insulating film 112. Then, the source electrode 113, the gate wiring layer 120, the gate lead-out portion 111a, and the pads 12a to 12e are formed by performing the corresponding processes shown below.

[0087] Specifically, a lower wiring electrode (P2) is formed on the interlayer insulating film 112, including the interior of contact holes 112a to 112e. As the lower wiring electrode, a wiring electrode material such as AlSi is deposited by sputtering as the main material. In this case, the lower wiring electrode is preferably formed after a Ti / TiN layered structure is formed by sputtering to form a barrier metal layer as the substrate, rather than forming the wiring electrode material directly on the semiconductor layer. Next, after applying a photoresist to the lower wiring electrode, exposure and development are performed to form a photoresist mask. Then, the lower wiring electrode is wet-etched using the photoresist mask. If the substrate layer has already been formed, the substrate layer is dry-etched. Afterward, the photoresist mask is stripped and a cleaning process is performed. Furthermore, sintering is performed. As a result, the patterning of the lower wiring electrode is completed, thereby forming the source electrode 113, and portions of the gate wiring layer 120 and the via extraction layer 130 formed by the lower wiring electrode are also formed.

[0088] Subsequently, an isolation insulating film 116 (P3) is formed. For example, a silicon oxide film, such as undoped silicate glass (USG) or a silicon nitride film, is deposited as an insulating material to form the isolation insulating film 116. By using the silicon oxide film or the silicon nitride film, appropriate insulation can be provided for the lower layer wiring electrode and the upper layer wiring electrode. Moreover, the use of the silicon nitride film achieves the effect of suppressing oxidation of the lower layer wiring electrode portion covered with the silicon nitride film. After applying a photoresist to the isolation insulating film 116, exposure and development are performed to form a photoresist mask. Then, the isolation insulating film 116 is patterned by dry etching using the photoresist mask. In this case, the isolation insulating film 116 remains in the area where the pads 12a to 12e are to be formed, while the isolation insulating film 116 does not remain on the surface of the portion of the lower layer wiring electrode forming the source electrode 113 or the surface of the portion of the lower layer wiring electrode forming the gate wiring layer 120 and the via extraction layer 130. Afterwards, when the photoresist mask is stripped and a cleaning process is performed, the isolation insulating film 116 with the desired pattern is formed.

[0089] Furthermore, an upper wiring electrode is formed to cover the portion consisting of the lower wiring electrode, such as the source electrode 113, including the top (P4) of the insulating film 116. For example, as the upper wiring electrode, a wiring electrode material such as AlSi is deposited by sputtering. In this case, the upper wiring electrode is preferably formed after a Ti / TiN layered structure is formed by sputtering to form a barrier metal layer as a base layer, rather than directly forming the wiring electrode material. Next, after applying a photoresist to the upper wiring electrode, exposure and development are performed to form a photoresist mask. Then, the upper wiring electrode is wet-etched using the photoresist mask. If the base layer has already been formed, the base layer is dry-etched. Afterward, the photoresist mask is stripped and a cleaning process is performed, followed by sintering. As a result, the patterning of the upper wiring electrode is completed, and a portion of the gate wiring layer 120 and the via extraction layer 130 consisting of the upper wiring electrode is formed. Similarly, pads 12a to 12e are formed.

[0090] In the patterning of the upper layer wiring electrodes, the removal of the lower layer wiring electrodes can be prevented by controlling the etching time when removing the upper layer wiring electrodes. When a barrier metal layer is formed as a substrate layer, the barrier metal layer can serve as an etch-blocking layer. When the insulating film 116 is formed, an oxide layer can be formed on the surface of the source electrode 113. However, the oxide layer can be removed simultaneously with the removal of the upper layer wiring electrodes. Therefore, the contact resistance of the source electrode 113 can be reduced, and the on-resistance can also be reduced.

[0091] Subsequently, the semiconductor chip 10 can be manufactured by various processes, such as a process of forming a passivation film 115 made of, for example, polyimide isoindolequinazole dione (PIQ), a process of forming a drain electrode 114 as a back electrode, and a slicing process by cutting.

[0092] (Second Embodiment)

[0093] The second embodiment is described below. In this embodiment, the region with the double-layer wiring electrode structure differs from that in the first embodiment. Other configurations are similar to those in the first embodiment. Therefore, only the configurations that differ from the first embodiment will be described below.

[0094] like Figure 9 As shown, in this embodiment, only the areas corresponding to pads 12a to 12e in the pad setting area Re have a double-layer wiring electrode structure, while all other areas have a single-layer wiring electrode structure. Specifically, as... Figure 10 As shown, in this embodiment, not only the source electrode 113 in the portion of the active region Rb that does not overlap with the pad setting region Re, but also the gate wiring layer 120 and the via extraction layer 130 have a single-layer wiring electrode structure.

[0095] Using this structure, the thickness of the gate wiring layer 120 and the via extraction layer 130 can be reduced, and the increase in warpage of the semiconductor chip 10 can be suppressed at high temperatures. In the case where the gate wiring layer 120 and the via extraction layer 130 form a double-layer wiring electrode structure as in the first embodiment, it is necessary to remove the isolation insulating film 116 formed between the lower and upper wiring electrodes. However, when the gate wiring layer 120 and the via extraction layer 130 are composed only of the lower wiring electrode, it is not necessary to remove the isolation insulating film 116 from the region corresponding to the portion of the gate wiring layer 120 that connects to the gate pad 12c and the region corresponding to the portion of the via extraction layer 130 that connects to the second sensing pad 12e. Therefore, when the isolation insulating film 116 is composed of a silicon nitride film, the oxidation of the gate wiring layer 120 and the via extraction layer 130 can be further suppressed.

[0096] (Third Embodiment)

[0097] The third embodiment is described below. In this embodiment, the proportion of the region having the double-layer wiring electrode structure is limited to the opposite of the configuration in the first and second embodiments, while other configurations are the same as in the first and second embodiments. Therefore, only the configurations different from the first and second embodiments will be described below.

[0098] As described above, in the first embodiment, the regions where pads 12a to 12e are provided have a double-layer wiring electrode structure for the gate wiring layer 120 and the via extraction layer 130. In the second embodiment, the regions where pads 12a to 12e are provided also have a double-layer wiring electrode structure. The area of ​​the region with the double-layer wiring electrode structure is preferably 30% or less of the active region Rb. Specifically, the warpage of the semiconductor chip 10 at high temperatures increases with the increase of the area of ​​the double-layer wiring electrode structure. Furthermore, the area of ​​the active region Rb is considered to be the area of ​​the region that generates heat. There is a correlation between the area of ​​the active region Rb and the area of ​​the region with the double-layer wiring electrode structure. When the ratio of the area of ​​the region with the double-layer wiring electrode structure to the area of ​​the active region Rb is 30% or less, the increase in warpage of the semiconductor chip 10 is suppressed within a more preferred range.

[0099] Therefore, by setting the layout of each part so that the ratio of the area of ​​the region with the double-layer wiring electrode structure to the area of ​​the active region Rb is 30% or less, the increase in warpage of the semiconductor chip 10 can be further suppressed.

[0100] (Fourth Embodiment)

[0101] The fourth embodiment is described below. This embodiment defines a pad layout in the semiconductor chip 10 that differs from the first to third embodiments, while other configurations are similar to those in the first to third embodiments. Therefore, only the configurations different from the first to third embodiments will be described below.

[0102] In this embodiment, as Figure 11 As shown, the layout of the internal region Ra constituting the source pad 11 and the pads 12a to 12e formed in the semiconductor chip 10 is linearly symmetrical with respect to the line L. The line L is the center line that passes through the center of the internal region Ra constituting the rectangular source pad 11 in the center line of the semiconductor chip 10. The source pad 11 itself is linearly symmetrical with respect to the line L. Similarly, the pads 12a to 12e are arranged linearly symmetrically with respect to the line L.

[0103] With this configuration, the warpage of the semiconductor chip 10 can remain uniform relative to the straight line L centered on it. Therefore, warpage is easier to predict and easier to design the semiconductor chip 10 by taking warpage into account.

[0104] (Fifth Embodiment)

[0105] The fifth embodiment is described below. This embodiment differs from the first to fourth embodiments in the number of pads in the semiconductor chip 10. Other configurations are similar to those in the first to fourth embodiments. Therefore, only the configurations different from the first to fourth embodiments will be described below.

[0106] In this embodiment, as Figure 12As shown, in addition to the internal region Ra that constitutes the source pad 11, the semiconductor chip 10 also includes a gate pad 12c, but does not include other pads 12a, 12b, 12d, and 12e. That is, the number of pads with a double-layer wiring electrode structure is only one.

[0107] The warpage of the semiconductor chip 10 increases with the increase of the area of ​​the region with the double-layer wiring electrode structure. Therefore, it is preferable to reduce the number of pads with the double-layer wiring electrode structure, preferably five or less. In the first to fourth embodiments, the number of pads with the double-layer wiring electrode structure is five. However, the number of pads with the double-layer wiring electrode structure can be less than five. Therefore, by setting the number of pads to less than 5, for example, to 1 (which is the minimum number, as in this embodiment), the increase in warpage of the semiconductor chip 10 can be further suppressed.

[0108] In this embodiment, the gate pad 12c is arranged along the central portion of one side of the rectangular semiconductor chip 10, and the internal region Ra constituting the source pad 11 is formed such that it surrounds the gate pad 12c in a concave shape, which defines an opening surrounding the gate pad 12c (i.e., Figure 12 (Lower side of the middle). Furthermore, similar to the fourth embodiment, the source pad 11 itself is line-symmetrical with respect to the line L, and the gate pad 12c is line-symmetrical with respect to the line L. However, this layout is an example of a layout for the semiconductor chip 10 when the number of pads with the double-layer wiring electrode structure is five or fewer. The semiconductor chip 10 can have any other layout, as long as the number of pads meets the requirements.

[0109] (Other embodiments)

[0110] While this disclosure has been described with reference to the above embodiments, it is not limited to the above embodiments, but includes various modifications and equivalent modifications. Furthermore, various combinations and aspects, as well as other combinations and aspects including only one element, more than one element, or less than one element, are also within the spirit and scope of this disclosure.

[0111] For example, in each of the above embodiments, a vertical MOSFET is used as an example of a semiconductor element provided in the active region Rb. However, the semiconductor element can be provided by any other element such as a vertical IGBT or a diode or a combination of different types of elements.

[0112] Although an example of a semiconductor chip constituting semiconductor device 10 has been given, the semiconductor device may have the same characteristics as... Figure 2AThis is another structure that is different from the one shown. That is, in addition to the surface electrode such as the source electrode 113 provided in the active region Rb, the semiconductor chip 10 also has pads 12a to 12e provided in the pad setting region Re, wherein the pads 12a to 12e have a double-layer wiring electrode structure, while the surface electrode has a single-layer wiring electrode structure.

[0113] In each of the above embodiments, the entire pad setting area Re overlaps with the active area Rb. Alternatively, the pad setting area Re may partially overlap with the active area Rb.

[0114] In each of the above embodiments, single-layer wiring electrode structure and double-layer wiring electrode structure refer to the number of layers of wiring electrode material such as AlSi. The number of layers of wiring electrode material referred to here does not include metal layers, such as barrier metal layers that are not made of wiring electrode material.

Claims

1. A semiconductor device provided by a semiconductor chip, the semiconductor device comprising: An active region having a semiconductor element and a surface electrode, the surface electrode being provided by a lower wiring electrode made of a wiring electrode material in a first layer disposed above an interlayer insulating film on the semiconductor element, and connected to the semiconductor element on a side adjacent to the surface of the semiconductor chip; and A pad placement area having pads provided by an upper wiring electrode in a second layer disposed above the lower wiring electrode and made of the wiring electrode material, wherein... The pad area is arranged to overlap the active area in a direction perpendicular to the surface of the semiconductor chip. In the portion where the pad placement area overlaps with the active area, the pads are arranged on the surface electrode via an insulating film, such that the wiring electrode material is two-layered to provide a double-layer wiring electrode structure. In the portion of the active region that does not overlap with the pad setting area, the surface electrode has a single-layer wiring electrode structure consisting of the lower wiring electrode as a single-layer wiring electrode material, and is exposed from the insulating film such that the exposed portion of the surface electrode serves as the electrode pad of the surface electrode.

2. The semiconductor device according to claim 1, wherein The pads are connected to a wiring layer provided by the wiring electrode material and connected to the semiconductor element, and The wiring layer has a single-layer wiring electrode structure composed of the single-layer wiring electrode material.

3. The semiconductor device according to claim 1, wherein... The area of ​​the portion having the double-layer wiring electrode structure is 30% or less of the area of ​​the active region.

4. The semiconductor device according to claim 1, wherein Each of the surface electrodes and the pads is symmetrical about a straight line, which is the center line of the semiconductor chip that passes through the center of the surface electrode.

5. The semiconductor device of claim 1, wherein the number of pads is five or fewer.

6. The semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film.

7. The semiconductor device according to claim 1, wherein the insulating film is a silicon nitride film.

8. The semiconductor device of claim 1, wherein the wiring electrode material is made of AlSi.

9. The semiconductor device according to any one of claims 1 to 8, wherein The semiconductor chip includes a semiconductor substrate made of silicon carbide, and The semiconductor element is disposed in the semiconductor substrate.

10. A method for manufacturing a semiconductor device, the semiconductor device having a semiconductor chip, the semiconductor chip including a semiconductor substrate and semiconductor elements formed on the semiconductor substrate, the method comprising: A surface electrode is formed within an active region forming the semiconductor element, the surface electrode being connected to the semiconductor element, wherein the formation of the surface electrode includes (i) forming the semiconductor element on the semiconductor substrate; (ii) after the formation of the semiconductor element, forming an interlayer insulating film adjacent to the surface of the semiconductor substrate; (iii) forming a contact hole in the interlayer insulating film; (iv) forming a lower layer wiring electrode over the interlayer insulating film, including the interior of the contact hole, using a first layer wiring electrode material; and (v) patterning the lower layer wiring electrode to form the surface electrode. An insulating film is formed on the surface electrode; A pad is formed within a pad placement area overlapping the active region, wherein the formation of the pad includes: (vi) forming an upper layer wiring electrode on the insulating film using a second layer wiring electrode material; and (vii) patterning the upper layer wiring electrode, thereby forming the pad in the pad placement area, wherein The formation of the pad further includes: (viii) removing the upper wiring electrode formed on the surface electrode in the portion of the active region that does not overlap with the pad placement area, such that the surface electrode has a single-layer wiring electrode structure composed of the lower wiring electrode; (ix) leaving the upper wiring electrode formed on the surface electrode in the portion of the active region that overlaps with the pad placement area, such that the pad is arranged on the surface electrode, thereby forming a double-layer wiring electrode structure composed of the lower wiring electrode and the upper wiring electrode.

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