Semiconductor device

Abstract

The utility model discloses a semiconductor device, which comprises at least one unit cell structure. The unit cell structure comprises a substrate; the channel layer is located on one side of the substrate, and the barrier layer is located on the side, away from the substrate, of the channel layer; the source electrode and the drain electrode are located on the side, away from the substrate, of the barrier layer in a spaced mode; the doped III-V group semiconductor layer is located on the side, away from the substrate, of the barrier layer, and the doped III-V group semiconductor layer surrounds the drain electrode; and the first source field plate is located on one side, far away from the substrate, of the barrier layer, and the first source field plate surrounds the drain electrode. According to the HEMT device provided by the utility model, the isolation between devices can be realized without adopting an ion implantation process, and the electric field is uniform when the HEMT device is turned off and the drain electrode is in a pressure-bearing state, so that the drain electrode has good high-voltage bearing capacity.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0002] For existing gallium nitride (GaN) high electron mobility transistor (HEMT) devices, ion implantation is used to achieve isolation between devices, preventing leakage current caused by the high voltage at the drain when the HEMT device is turned off, thus avoiding short circuits between devices. However, ion implantation requires a portion of the device area, reducing the active region area of ​​the HEMT, increasing the on-resistance between the source and drain, and also increasing the manufacturing cost of the HEMT. Furthermore, in existing HEMT isolation structures that do not employ ion implantation, there is an uneven electric field between the upper and lower drain terminals, i.e., an uneven voltage field across the drain when the device is turned off. Utility Model Content

[0003] This invention provides a semiconductor device to solve the problem of uneven drain voltage field in the isolation structure of existing HEMT devices that do not use ion implantation to achieve device isolation, when the device is off.

[0004] In a first aspect, this utility model provides a semiconductor device, wherein the semiconductor device comprises: at least one unit cell structure; the unit cell structure comprises:

[0005] Substrate;

[0006] The channel layer and the barrier layer are located on one side of the substrate, and the barrier layer is located on the side of the channel layer away from the substrate.

[0007] The source and drain are spaced apart on the side of the barrier layer away from the substrate.

[0008] A group III-V semiconductor layer is located on the side of the barrier layer away from the substrate, and the group III-V semiconductor layer surrounds the drain electrode;

[0009] The gate is located on the side of the group III-V semiconductor layer away from the substrate;

[0010] The first source field plate is located on the side of the barrier layer away from the substrate and is connected to the source; the first source field plate surrounds the drain.

[0011] The vertical projection of the first source field plate onto the substrate lies between the vertical projection of the III-V semiconductor layer onto the substrate and the vertical projection of the drain onto the substrate; the vertical distance between the centerline of the first source field plate and the centerline of the III-V semiconductor layer is less than the vertical distance between the centerline of the first source field plate and the centerline of the drain.

[0012] Optionally, the unit cell structure may also include: a second source field plate;

[0013] The second source field plate is connected to the source; the second source field plate is located on the side of the first source field plate away from the substrate, and the second source field plate surrounds the drain.

[0014] Optionally, the vertical projection of the second source field plate onto the substrate is located between the vertical projection of the III-V semiconductor layer onto the substrate and the vertical projection of the drain onto the substrate; the vertical distance between the centerline of the second source field plate and the centerline of the III-V semiconductor layer is less than the vertical distance between the centerline of the second source field plate and the centerline of the drain.

[0015] Optionally, the vertical projection of the second source field plate onto the substrate partially overlaps with the vertical projection of the first source field plate onto the substrate.

[0016] Alternatively, the vertical projection of the second source field plate onto the substrate does not overlap with the vertical projection of the first source field plate onto the substrate.

[0017] Optionally, the unit cell structure further includes: a first dielectric layer, a second dielectric layer, a first metal layer, a first metal plug, and a second metal plug;

[0018] The first dielectric layer is located on the side of the barrier layer, drain, source, III-V group semiconductor layer and gate away from the substrate, and the first source field plate is located on the side of the first dielectric layer away from the substrate.

[0019] The second dielectric layer is located on the side of the first dielectric layer and the first source field plate away from the substrate; the first metal layer is located on the side of the second dielectric layer away from the substrate;

[0020] The first dielectric layer includes a first contact hole, and the second dielectric layer includes a second contact hole and a third contact hole. The vertical projection of the first contact hole onto the substrate is located within the vertical projection of the source electrode onto the substrate. The vertical projection of the second contact hole onto the substrate coincides with the vertical projection of the first contact hole onto the substrate. The vertical projection of the third contact hole onto the substrate is located within the vertical projection of the first source field plate onto the substrate. A first metal plug fills the first contact hole and the second contact hole to connect the source electrode to the first metal layer. A second metal plug fills the third contact hole to connect the first source field plate to the first metal layer.

[0021] Optionally, the unit cell structure includes: a first dielectric layer, a second dielectric layer, a third dielectric layer, a second metal layer, a third metal plug, a fourth metal plug, and a fifth metal plug;

[0022] The first dielectric layer is located on the side of the barrier layer, drain, source, III-V group semiconductor layer and gate away from the substrate, and the first source field plate is located on the side of the first dielectric layer away from the substrate; the second dielectric layer is located on the side of the first dielectric layer and the first source field plate away from the substrate, and the second source field plate is located on the side of the second dielectric layer away from the substrate.

[0023] The third dielectric layer is located on the side of the second dielectric layer and the second source field plate away from the substrate; the second metal layer is located on the side of the third dielectric layer away from the substrate;

[0024] The first dielectric layer includes a first contact hole, the second dielectric layer includes a second contact hole and a third contact hole, and the third dielectric layer includes a fourth contact hole, a fifth contact hole, and a sixth contact hole. The vertical projection of the first contact hole onto the substrate is located within the vertical projection of the source electrode onto the substrate. The vertical projections of the second and fourth contact holes onto the substrate coincide with the vertical projection of the first contact hole onto the substrate. The vertical projection of the third contact hole onto the substrate is located within the vertical projection of the first source field plate onto the substrate. The vertical projection of the fifth contact hole onto the substrate coincides with the vertical projection of the third contact hole onto the substrate. The vertical projection of the sixth contact hole onto the substrate is located within the vertical projection of the second source field plate onto the substrate. A third metal plug fills the first, second, and fourth contact holes to connect the source electrode to the second metal layer. A fourth metal plug fills the third and fifth contact holes to connect the first source field plate to the second metal layer. A fifth metal plug fills the sixth contact hole to connect the second source field plate to the second metal layer.

[0025] Optionally, the distance between the side of the first source field plate near the drain and the side of the drain near the first source field plate is constant.

[0026] Optionally, the distance between the side of the second source field plate near the drain and the side of the drain near the second source field plate is constant.

[0027] Optionally, the III-V semiconductor layer includes a P-type doped nitride layer, which includes a P-type doped gallium nitride layer.

[0028] Optionally, the first dielectric layer includes an aluminum nitride dielectric layer or an aluminum oxide dielectric layer, and the second dielectric layer includes a silicon nitride dielectric layer or a silicon oxide dielectric layer.

[0029] The technical solution of this embodiment of the invention involves surrounding the drain with a doped III-V semiconductor layer. When the GaNHEMT device is off, the doped III-V semiconductor layer can deplete the two-dimensional electron gas of the active layer in its corresponding region. The high voltage of the drain is confined within the annular doped III-V semiconductor layer, effectively achieving isolation between HEMT devices and preventing leakage current from the drain when the HEMT device is off, thus avoiding short circuits between devices. This embodiment of the invention eliminates the need for ion implantation to achieve isolation between devices, effectively increasing the area of ​​the active region, reducing the on-resistance of the source and drain, and lowering process costs. Furthermore, this embodiment of the invention also includes a first source field plate surrounding the drain, ensuring a uniform electric field when the HEMT device is off and the drain is under pressure, resulting in good high voltage withstand capability for the drain.

[0030] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0033] Figure 2 This is a top view of a semiconductor device provided in an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0035] Figure 4 This is a top view of another semiconductor device provided in an embodiment of the present invention;

[0036] Figure 5 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0037] Figures 6-9 This is a schematic diagram of the structure corresponding to each step in the preparation method of a semiconductor device provided by this utility model embodiment;

[0038] Figure 10 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention;

[0039] Figures 11-12 This is a schematic diagram of some steps in another method for fabricating a semiconductor device provided in this embodiment of the present invention.

[0040] Figure 13 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention;

[0041] Figure 14 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention;

[0042] Figure 15This is a schematic diagram of some steps in a method for fabricating a semiconductor device provided in another embodiment of this utility model. Detailed Implementation

[0043] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0045] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Figure 2 This is a top view of a semiconductor device provided in an embodiment of the present invention. Figure 2 The unit cell structure 10 shown can be Figure 1 The top view of a portion of the membrane layer in the unit cell structure 10 shown. Figure 2 A top view of the unit cell structure 10 in the diagram shows Figure 1 The doped group III-V semiconductor layer 16, source 14, drain 15, and first source field plate 17 of the middle unit cell structure 10 Figure 2 The active layer 20 shown can be Figure 1 The interface where the channel layer 12 and the barrier layer 13 meet. For example... Figure 1 and Figure 2As shown, the semiconductor device 1 includes: at least one unit cell structure 10, the unit cell structure 10 including: a substrate 11; a channel layer 12 and a barrier layer 13, the channel layer 12 being located on one side of the substrate 11, and the barrier layer 13 being located on the side of the channel layer 12 away from the substrate 11; a source 14 and a drain 15, the source 14 and drain 15 being spaced apart on the side of the barrier layer 13 away from the substrate 11; a doped III-V semiconductor layer 16, located on the side of the barrier layer 13 away from the substrate 11, the doped III-V semiconductor layer 16 surrounding the drain 15; and a first source field plate 17, located on the side of the barrier layer 13 away from the substrate 11, the first source field plate 17 being connected to the source 14, and the first source field plate 17 surrounding the drain 15. The vertical projection of the first source field plate 17 onto the substrate 11 is located between the vertical projection of the doped III-V semiconductor layer 16 onto the substrate 11 and the vertical projection of the drain 15 onto the substrate 11. The vertical distance between the center line of the first source field plate 17 and the center line of the doped III-V semiconductor layer 16 is smaller than the vertical distance between the center line of the first source field plate 17 and the center line of the drain 15.

[0046] Specifically, a GaN HEMT device may include multiple unit cell structures 10. Each unit cell structure 10 may include a substrate 11, a channel layer 12, and a barrier layer 13. The substrate 11 may be a Si substrate, a sapphire substrate, or a GaN substrate. The channel layer 12 may be intrinsic GaN as the channel layer, and the barrier layer 13 may be made of AlGaN material. Figure 2 The active layer 20 shown is the interface between the channel layer 12 and the barrier layer 13. When the GaN HEMT device is turned on, a two-dimensional electron gas with high mobility is formed at the interface between the channel layer 12 and the barrier layer 13, thereby forming a conductive channel.

[0047] Sources 14 and drains 15 are arranged at intervals on the side of the barrier layer 13 away from the substrate 11, and both sources 14 and drains 15 are in contact with the barrier layer 13. The sources 14 and drains 15 of multiple unit cell structures 10 are arranged in a cross pattern, and the sources 14 of multiple unit cell structures 10 can be connected to each other, and the drains 15 of multiple unit cell structures 10 can be connected to each other.

[0048] A doped III-V semiconductor layer 16 is located on one side of the barrier layer 13 and is in contact with the barrier layer 13. The doped III-V semiconductor layer 16 is disposed around the drain 15. The doped III-V semiconductor layer 16, the barrier layer 13, and the channel layer 12 can form a PIN structure. In the off state of the GaN HEMT device, the doped III-V semiconductor layer 16 can deplete the two-dimensional electron gas of the active layer 20 in its corresponding region. The high voltage of the drain is confined inside the annular doped III-V semiconductor layer 16, which can effectively achieve isolation between HEMT devices and effectively prevent leakage current from the high voltage of the drain when the HEMT device is turned off, thereby causing a short circuit between devices. Each unit cell structure 10 is also provided with a gate 22, which is located on the side of the doped III-V semiconductor layer 16 away from the substrate 11. The gate 22 can also be disposed around the drain 15.

[0049] The unit cell structure 10 also includes a first source field plate 17. The first source field plate 17 can be disposed on the side of the barrier layer 13 away from the substrate 11. The first source field plate 17 can be connected to the source 14, and the first source field plate 17 can be insulated from the doped III-V semiconductor layer 16 on a different layer. The first source field plate 17 can also be disposed around the drain 15. The first source field plate 17 can introduce an electric field distribution opposite to that of the drain 15. In the HEMT device off state, the potential difference between the first source field plate 17 and the drain 15 will redistribute the electric field lines. The first source field plate 17 can provide symmetrical electric field modulation to ensure that the electric field is uniformly distributed circumferentially along the drain 15. The first source field plate 17 can be disposed close to the doped III-V semiconductor layer 16 and the gate 22. In the off state of the GaN HEMT device, the first source field plate 17 can reduce the high electric field between the gate structure and the drain 15, and in the region close to the gate structure, so as to avoid the edge region of the gate structure near the drain 15 being broken down in the off state of the GaN HEMT device, thus affecting the reliability of the GaN HEMT device.

[0050] The technical solution of this embodiment of the invention involves setting a doped III-V semiconductor layer 16 around the drain 15. When the GaN HEMT device is off, the doped III-V semiconductor layer 16 can deplete the two-dimensional electron gas of the active layer 20 in its corresponding region. The high voltage of the drain is confined within the annular doped III-V semiconductor layer 16, effectively achieving isolation between HEMT devices and preventing leakage current from the drain when the HEMT device is off, thus avoiding short circuits between devices. This embodiment of the invention eliminates the need for ion implantation to achieve isolation between devices, effectively increasing the area of ​​the active region 20, reducing the on-resistance of the source 14 and drain 15, and lowering process costs. Furthermore, this embodiment of the invention sets a first source field plate 17 around the drain 15, ensuring a uniform electric field at the drain 15 under pressure when the HEMT device is off, thus giving the drain 15 good high voltage withstand capability.

[0051] Optionally, based on the above embodiments, Figure 3 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 4 This is a top view of another semiconductor device provided in an embodiment of the present invention. Figure 4 The unit cell structure 10 shown can be Figure 3 The top view of a portion of the membrane layer in the unit cell structure 10 shown. Figure 4 A top view of the unit cell structure 10 in the diagram shows Figure 3 A portion of the doped III-V group semiconductor layer 16, source 14, drain 15, first source field plate 17, and second source field plate 18 in the middle unit cell structure 10. Figure 4 The active layer 20 shown can be Figure 3 The interface where the channel layer 12 and the barrier layer 13 meet. For example... Figure 3 and Figure 4 As shown, the unit cell structure 10 also includes: a second source field plate 18, which is located on the side of the first source field plate 17 away from the substrate 11, the second source field plate 18 is connected to the first source 14, and the second source field plate 18 surrounds the drain 15.

[0052] Specifically, the unit cell structure 10 may also include a second source field plate 18, which may be located in a different layer from the first source field plate 17, and the second source field plate 18 may be connected to the first source field plate 17 and the source 14.

[0053] Each unit cell 10 contains a first source field plate 17 and a second source field plate 18. The first source field plate 17 surrounds the drain 15, and the second source field plate 18 also surrounds the drain 15. The second source field plate 18 can also introduce an electric field distribution opposite to that of the drain 15. When the HEMT device is off, the potential difference between the second source field plate 18 and the drain 15 will redistribute the electric field lines. The second source field plate 18 can provide symmetrical electric field modulation, ensuring that the electric field is uniformly distributed circumferentially along the drain 15. The arrangement of the first source field plate 17 and the second source field plate 18 can further optimize the electric field distribution, improve the breakdown voltage, suppress current collapse, and improve high-frequency characteristics.

[0054] Optionally, based on the above embodiments, continue to refer to... Figure 3 and Figure 4 The vertical projection of the second source field plate 18 onto the substrate 11 lies between the vertical projections of the doped III-V semiconductor layer 16 onto the substrate 11 and the vertical projection of the drain 15 onto the substrate 11. The vertical distance between the centerline of the second source field plate 18 and the centerline of the doped III-V semiconductor layer 16 is smaller than the vertical distance between the centerline of the second source field plate 18 and the centerline of the drain 15.

[0055] Specifically, the second source field plate 18 can also be positioned close to the doped III-V semiconductor layer 16 and the gate 22. In the off state of the GaN HEMT device, the second source field plate 18 can reduce the high electric field between the gate structure and the drain 15, and in the region close to the gate structure, so as to avoid the edge region of the gate structure near the drain 15 being broken down in the off state of the GaN HEMT device, thus affecting the reliability of the GaN HEMT device.

[0056] Optionally, based on the above embodiments, continue to refer to... Figure 3 and Figure 4 The vertical projection of the second source field plate 18 onto the substrate 11 partially overlaps with the vertical projection of the first source field plate 17 onto the substrate 11. Alternatively, the vertical projection of the second source field plate 18 onto the substrate 11 does not overlap with the vertical projection of the first source field plate 17 onto the substrate 11.

[0057] Specifically, the arrangement of the first source field plate 17 and the second source field plate 18 can further optimize the electric field distribution, improve the breakdown voltage, suppress current collapse, and improve high-frequency characteristics. The first source field plate 17 and the second source field plate 18 can reduce the high electric field between the gate structure and the drain 15, and in the region close to the gate structure, to prevent the edge region of the gate structure near the drain 15 from being broken down when the GaN HEMT device is turned off, thus affecting the reliability of the GaN HEMT device.

[0058] Optionally, based on the above embodiments, continue to refer to... Figure 1 and Figure 2 The unit cell structure 10 further includes a first dielectric layer 19 and a second dielectric layer 21. The first dielectric layer 19 is located on the side away from the substrate 11, consisting of the barrier layer 13, drain 15, source 14, and the doped III-V semiconductor layer 16. A first source field plate 17 is located on the side of the first dielectric layer 19 away from the substrate 11. The second dielectric layer 21 is located on the side of the first dielectric layer 19 and the first source field plate 17 away from the substrate 11. The unit cell structure 10 also includes a first metal layer 23, a first metal plug 24, and a second metal plug 25. The first metal layer 23 is located on the side of the second dielectric layer 21 away from the substrate 11. The first dielectric layer 19 includes a first contact hole 27, and the second dielectric layer 21 includes a second contact hole 26 and a third contact hole 30. The vertical projection of the first contact hole 27 onto the substrate 11 lies within the vertical projection of the source 14 onto the substrate 11. The vertical projection of the second contact hole 26 onto the substrate 11 coincides with the vertical projection of the first contact hole 27 onto the substrate 11. The vertical projection of the third contact hole 30 onto the substrate 11 lies within the vertical projection of the first source field plate 17 onto the substrate 11. The first metal plug 24 fills the first contact hole 27 and the second contact hole 26 to connect the source 14 to the first metal layer 23. The second metal plug 25 fills the third contact hole 30 to connect the first source field plate 17 to the first metal layer 23.

[0059] Specifically, each unit cell structure 10 further includes a first dielectric layer 19 and a second dielectric layer 21, both of which may include insulating materials such as silicon dioxide or silicon nitride. When fabricating the unit cell structure 10, a source 14, a drain 15, a doped III-V semiconductor layer 16, and a gate 22 can be formed first on the side of the barrier layer 13 away from the substrate 11. Then, a first dielectric layer 19 is formed on the side of the source 14, drain 15, doped III-V semiconductor layer 16, gate 22, and barrier layer 13 away from the substrate 11. The first dielectric layer 19 may have a first contact hole 27. A first source field plate 17 is formed on the side of the first dielectric layer 19 away from the substrate 11. The first dielectric layer 19 can effectively insulate and isolate the gate 22 and the first source field plate 17.

[0060] Then, a second dielectric layer 21 is formed on the side of the first source field plate 17 and the first dielectric layer 19 away from the substrate 11. The second dielectric layer 21 may include a second contact hole 26 and a third contact hole 30. A first metal plug 24 is filled in the first contact hole 27 and the second contact hole 26, and a second metal plug 25 is filled in the third contact hole 30. Finally, a first metal layer 23 is formed on the side of the second dielectric layer 21 away from the substrate 11. The first metal layer 23 is connected to the source 14 through the first metal plug 24, and the first metal layer 23 is also connected to the first source field plate 17 through the second metal plug 25, thereby realizing the connection between the source 14 and the first source field plate.

[0061] Within each unit cell structure 10, the second dielectric layer 21 corresponding to the side of the first source field plate 17 away from the source 14 in the same unit cell structure 10 may also be provided with a seventh contact hole 29. The seventh contact hole 29 may be filled with a sixth metal plug 28. The sixth metal plug 28 may be connected to the same first metal layer 23 with the source 14 in the adjacent unit cell structure 10, so that the side of the first source field plate 17 away from the source 14 in the same unit cell structure 10 is connected to the source 14 in the adjacent unit cell structure 10.

[0062] Optionally, based on the above embodiments, continue to refer to... Figure 3 and Figure 4 The unit cell structure 10 includes a first dielectric layer 19, a second dielectric layer 21, and a third dielectric layer 31. The third dielectric layer 31 is located on the side of the second dielectric layer 21 and the second source field plate 18 away from the substrate 11. Figure 3 and Figure 4 The structure shown does not include the first metal layer. The unit cell structure 10 also includes a second metal layer 41, a third metal plug 32, a fourth metal plug 42, and a fifth metal plug 33. The second metal layer 41 is located on the side of the third dielectric layer 31 away from the substrate 11. The third dielectric layer 31 includes a fourth contact hole 34, a fifth contact hole 35, and a sixth contact hole 36. The vertical projection of the fourth contact hole 34 onto the substrate 11 coincides with the vertical projection of the first contact hole 27 onto the substrate 11; the vertical projection of the fifth contact hole 35 onto the substrate 11 coincides with the vertical projection of the third contact hole 30 onto the substrate 11; and the vertical projection of the sixth contact hole 36 onto the substrate 11 is within the vertical projection of the second source field plate 18 onto the substrate 11. The third metal plug 32 fills the first contact hole 27, the second contact hole 26, and the fourth contact hole 34 to connect the source 14 to the second metal layer 41. The fourth metal plug 42 fills the third contact hole 30 and the fifth contact hole 35 to connect the first source field plate 17 to the second metal layer 41. The fifth metal plug 33 fills the sixth contact hole 36 to connect the second source field plate 18 and the second metal layer 41.

[0063] Specifically, each unit cell structure 10 may include a first dielectric layer 19, a second dielectric layer 21, and a third dielectric layer 31. The third dielectric layer 31 may also include insulating materials such as silicon dioxide or silicon nitride. When fabricating the unit cell structure 10, a source 14, a drain 15, a doped III-V semiconductor layer 16, and a gate 22 may be formed on the side of the barrier layer 13 away from the substrate 11. Then, a first dielectric layer 19 may be formed on the side of the source 14, drain 15, doped III-V semiconductor layer 16, gate 22, and barrier layer 13 away from the substrate 11. The first dielectric layer 19 may be provided with a first contact hole 27. A first source field plate 17 is formed on the side of the first dielectric layer 19 away from the substrate 11. The first dielectric layer 19 can effectively insulate and isolate the gate 22 and the first source field plate 17.

[0064] Then, a second dielectric layer 21 is formed on the side of the first source field plate 17 and the first dielectric layer 19 away from the substrate 11. The second dielectric layer 21 may include a second contact hole 26 and a third contact hole 30. Then, a second source field plate 18 is formed on the side of the second dielectric layer 21 away from the substrate 11. A third dielectric layer 31 is formed on the second source field plate 18 and the side of the second dielectric layer 21 away from the substrate 11. The third dielectric layer 31 may include a fourth contact hole 34, a fifth contact hole 35, and a sixth contact hole 36. A third metal plug 32 is filled in the first contact hole 27, the second contact hole 26, and the fourth contact hole 34. A fourth metal plug 42 is filled in the third contact hole 30 and the fifth contact hole 35. A fifth metal plug 33 is filled in the sixth contact hole 36. Finally, a second metal layer 41 is formed on the side of the third dielectric layer 31 away from the substrate 11. The second metal layer 41 is connected to the source electrode 14 through a third metal plug 32, and is also connected to the first source field plate 17 through a fourth metal plug 42. The second metal layer 41 is also connected to the second source field plate 18 through a fifth metal plug 33. This achieves the connection between the source electrode 14, the first source field plate 17, and the second source field plate 18.

[0065] Within each unit cell 10, a seventh contact hole 29 may be provided on the second dielectric layer 21 corresponding to the side of the first source field plate 17 away from the source 14 in the same unit cell 10, and an eighth contact hole 37 may be provided on the corresponding third dielectric layer 31. A ninth contact hole 38 may be provided on the third dielectric layer 31 corresponding to the side of the second source field plate 18 away from the source 14 in the same unit cell 10. The vertical projection of the seventh contact hole 29 onto the substrate 11 may coincide with the vertical projection of the eighth contact hole 37 onto the substrate 11. The seventh contact hole 29 and the eighth contact hole 37 may be filled with a seventh metal plug 39. The seventh metal plug 39 may be connected to the same second metal layer 41 with the source 14 in the adjacent unit cell 10, thereby connecting the side of the first source field plate 17 away from the source 14 in the same unit cell 10 with the source 14 in the adjacent unit cell 10. The ninth contact hole 38 can be filled with an eighth metal plug 40, which can be connected to the same second metal layer 41 as the source 14 in the adjacent unit cell structure 10, so that the side of the second source field plate 18 away from the source 14 in the same unit cell structure 10 is connected to the source 14 in the adjacent unit cell structure 10.

[0066] Optionally, based on the above embodiments, continue to refer to... Figures 1-4 The distance between the side of the first source field plate 17 near the drain 15 and the side of the drain 15 near the first source field plate 17 is constant.

[0067] Specifically, the vertical distance between the side of the first source field plate 17 near the drain 15 and the side of the drain 15 near the first source field plate 17 in each unit cell structure 10 can be kept constant. This setting can avoid the electric field concentration in a local area of ​​the drain 15. The constant distance makes the electric field uniformly distributed in the transverse direction along the channel, ensuring that the electric field is uniformly distributed in the circumference of the drain 15.

[0068] Optionally, based on the above embodiments, continue to refer to... Figure 3 and Figure 4 The distance between the side of the second source field plate 18 near the drain 15 and the side of the drain 15 near the second source field plate 18 is constant.

[0069] Specifically, the vertical distance between the side of the second source field plate 18 in each unit cell structure 10 that is close to the drain 15 and the side of the drain 15 that is close to the second source field plate 18 can be kept constant. This setting can further avoid the concentration of electric field in local areas of the drain 15. The constant distance makes the electric field uniformly distributed in the transverse direction along the channel, ensuring that the electric field is uniformly distributed in the circumference of the drain 15.

[0070] Optionally, based on the above embodiments, continue to refer to... Figures 1-4 The doped III-V semiconductor layer 16 includes a P-type doped nitride layer, which includes a P-type doped gallium nitride layer.

[0071] Specifically, the doped III-V semiconductor layer 16 may include a P-type doped nitride layer. For example, the P-type doped nitride layer may include a P-type doped gallium nitride layer (P-GaN) or a P-type doped aluminum gallium nitride layer (P-AlGaN). The doped III-V semiconductor layer 16, the barrier layer 13, and the channel layer 12 can form a PIN structure. In the off state of the GaN HEMT device, the doped III-V semiconductor layer 16 can deplete the two-dimensional electron gas of the active layer 20 in its corresponding region. The high voltage at the drain is confined within the annular doped III-V semiconductor layer 16, which can effectively achieve isolation between HEMT devices and effectively prevent leakage current from the high voltage at the drain when the HEMT device is turned off, thereby causing a short circuit between devices.

[0072] Figure 5 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figures 6-9 This is a schematic diagram of the structure corresponding to each step in the fabrication method of a semiconductor device provided by this utility model embodiment, as shown below. Figure 5 As shown, the preparation method includes:

[0073] S100: Provides a substrate.

[0074] Specifically, such as Figure 6As shown, when fabricating a GaN HEMT device, a substrate 11 is first provided. The substrate 11 can be a Si substrate, a sapphire substrate, or a GaN substrate.

[0075] S110: A channel layer and a barrier layer are formed sequentially on one side of the substrate.

[0076] Specifically, such as Figure 7 As shown, a channel layer 12 is formed on one side of the substrate 11, and a barrier layer 13 is formed on the side of the channel layer 12 away from the substrate 11. The channel layer 12 can be made of intrinsic GaN, and the barrier layer 13 can be made of AlGaN material.

[0077] S120: At least one source and at least one drain are formed on the side of the barrier layer away from the substrate; the source and drain are spaced apart; at least two source and at least two drain are cross-distributed.

[0078] Specifically, such as Figure 8 As shown, at least one source 14 and at least one drain 15 are formed on the side of the barrier layer 13 away from the substrate 1. Both the source 14 and the drain 15 can contact the barrier layer 13. The source 14 and the drain 15 are arranged in pairs and spaced apart. When the number of source 14 is greater than or equal to two and the number of drain 15 is greater than or equal to two, the source 14 and the drain 15 are arranged in a cross pattern, and all source 14 and all drain 15 can be connected to each other.

[0079] S130: A doped group III-V semiconductor layer corresponding to the source or drain is formed on the side of the barrier layer away from the substrate, and the doped group III-V semiconductor layer surrounds the drain.

[0080] Specifically, such as Figure 9 As shown, a doped III-V semiconductor layer 16 is formed on the side of the barrier layer 13 away from the substrate 11, corresponding one-to-one with the source 14 or drain 15. The doped III-V semiconductor layer 16 surrounds the drain 15. The doped III-V semiconductor layer 16, the barrier layer 13, and the channel layer 12 can form a PIN structure. In the off state of the GaN HEMT device, the doped III-V semiconductor layer 16 can deplete the two-dimensional electron gas of the active layer 20 in its corresponding region. The high voltage of the drain is confined inside the annular doped III-V semiconductor layer 16, which can effectively achieve isolation between HEMT devices and effectively prevent leakage current from the high voltage of the drain when the HEMT device is turned off, thereby causing a short circuit between devices. Each unit cell structure 10 also has a gate 22, which is located on the side of the doped III-V semiconductor layer 16 away from the substrate 11. The gate 22 can also surround the drain 15.

[0081] S140: A first source field plate corresponding to the source or drain is formed on the side of the barrier layer away from the substrate. The first source field plate is connected to the source. The first source field plate surrounds the drain.

[0082] Specifically, such as Figure 1 As shown, a first source field plate 17 is formed on the side of the barrier layer 13 away from the substrate 11, corresponding one-to-one with the source 14 or the drain 15. The first source field plate 17 can be connected to the source 14, and the first source field plate 17 can be disposed in a different layer from the doped III-V semiconductor layer 16. The first source field plate 17 can also be disposed around the drain 15. The first source field plate 17 can introduce an electric field distribution opposite to the potential of the drain 15. In the HEMT device off state, the potential difference between the first source field plate 17 and the drain 15 will redistribute the electric field lines. The first source field plate 17 can provide symmetrical electric field modulation to ensure that the electric field is uniformly distributed circumferentially along the drain 15.

[0083] The technical solution of this embodiment of the invention involves setting a doped III-V semiconductor layer 16 around the drain 15. When the GaN HEMT device is off, the doped III-V semiconductor layer 16 can deplete the two-dimensional electron gas of the active layer 20 in its corresponding region. The high voltage of the drain is confined within the annular doped III-V semiconductor layer 16, effectively achieving isolation between HEMT devices and preventing leakage current from the drain when the HEMT device is off, thus avoiding short circuits between devices. This embodiment of the invention eliminates the need for ion implantation to achieve isolation between devices, effectively increasing the area of ​​the active region 20, reducing the on-resistance of the source 14 and drain 15, and lowering process costs. Furthermore, this embodiment of the invention sets a first source field plate 17 around the drain 15, ensuring a uniform electric field at the drain 15 under pressure when the HEMT device is off, thus giving the drain 15 good high voltage withstand capability.

[0084] Optionally, based on the above embodiments, Figure 10 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention. Figures 11-12 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided by this utility model embodiment, as shown below. Figure 10 As shown, the preparation method includes:

[0085] S200: Provides a substrate.

[0086] S210: A channel layer and a barrier layer are formed sequentially on one side of the substrate.

[0087] S220: At least one source and at least one drain are formed on the side of the barrier layer away from the substrate; the source and drain are spaced apart; at least two source and at least two drain are cross-distributed.

[0088] S230: A doped group III-V semiconductor layer corresponding to the source or drain is formed on the side of the barrier layer away from the substrate, and the doped group III-V semiconductor layer surrounds the drain.

[0089] S240: A first dielectric layer is formed on the side of the barrier layer, drain, source, and doped III-V semiconductor layer away from the substrate; the first dielectric layer includes a first contact hole corresponding to the source, and the vertical projection of the first contact hole onto the substrate is located within the vertical projection of the source onto the substrate.

[0090] Specifically, such as Figure 11 As shown, when fabricating a GaN HEMT device, a source 14, a drain 15, a doped III-V semiconductor layer 16, and a gate 22 can be formed on the side of the barrier layer 13 away from the substrate 11. Then, a first dielectric layer 19 is formed on the side of the source 14, drain 15, doped III-V semiconductor layer 16, gate 22, and barrier layer 13 away from the substrate 11. The first dielectric layer 19 can be provided with a first contact hole 27. The vertical projection of the first contact hole 27 onto the substrate 11 can be located within the vertical projection of the source 14 onto the substrate 11.

[0091] S250: A first source field plate corresponding to the source or drain is formed on the side of the first dielectric layer away from the substrate; the first source field plate is connected to the source; the first source field plate surrounds the drain.

[0092] Specifically, such as Figure 12 As shown, a first source field plate 17 is formed on the side of the first dielectric layer 19 away from the substrate 11. The first dielectric layer 19 can effectively insulate and isolate the gate 22 and the first source field plate 17.

[0093] S260: A second dielectric layer is formed on the side of the first dielectric layer and the first source field plate away from the substrate; the second dielectric layer includes a second contact hole and a third contact hole, the vertical projection of the second contact hole on the substrate coincides with the vertical projection of the first contact hole on the substrate; the vertical projection of the third contact hole on the substrate is located within the vertical projection of the first source field plate on the substrate.

[0094] Specifically, such as Figure 12 As shown, a second dielectric layer 21 is formed on the side of the first source field plate 17 and the first dielectric layer 19 away from the substrate 11. The second dielectric layer 21 may include a second contact hole 26 and a third contact hole 30.

[0095] S270: A first metal plug is formed in the first contact hole and the second contact hole, and a second metal plug is formed in the third contact hole.

[0096] Specifically, such as Figure 1As shown, a first metal plug 24 is filled in the first contact hole 27 and the second contact hole 26, and a second metal plug 25 is filled in the third contact hole 30.

[0097] S280: A first metal layer is formed on the side of the second dielectric layer away from the substrate; the first metal layer is connected to the source through a first metal plug, and the first metal layer is also connected to the first source field plate through a second metal plug.

[0098] Specifically, such as Figure 1 As shown, a first metal layer 23 is formed on the side of the second dielectric layer 21 away from the substrate 11. The first metal layer 23 is connected to the source electrode 14 through a first metal plug 24. The first metal layer 23 is also connected to the first source field plate 17 through a second metal plug 25, thereby realizing the connection between the source electrode 14 and the first source field plate.

[0099] Optionally, based on the above embodiments, Figure 13 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention, such as... Figure 13 As shown, the preparation method includes:

[0100] S300: Provides a substrate.

[0101] S310: A channel layer and a barrier layer are formed sequentially on one side of the substrate.

[0102] S320: At least one source and at least one drain are formed on the side of the barrier layer away from the substrate; the source and drain are spaced apart; at least two source and at least two drain are cross-distributed.

[0103] S330: A doped group III-V semiconductor layer corresponding to the source or drain is formed on the side of the barrier layer away from the substrate, and the doped group III-V semiconductor layer surrounds the drain.

[0104] S340: A first source field plate corresponding to the source or drain is formed on the side of the barrier layer away from the substrate. The first source field plate is connected to the source. The first source field plate surrounds the drain.

[0105] S350: A second source field plate is formed on the side of the first source field plate away from the substrate, corresponding one-to-one with the source or drain; the second source field plate is connected to the source; the second source field plate surrounds the drain.

[0106] Specifically, such as Figure 3As shown, a second source field plate 18 is formed on the side of the first source field plate 17 away from the substrate 11, corresponding one-to-one with the source 14 or the drain 15. The second source field plate 18 can be located on a different layer from the first source field plate 17, and the second source field plate 18 can be connected to both the first source field plate 17 and the source 14. Each unit cell structure 10 of the GaN HEMT device is provided with a first source field plate 17 and a second source field plate 18. The first source field plate 17 is arranged around the drain 15, and the second source field plate 18 is also arranged around the drain 15. The second source field plate 18 can also introduce an electric field distribution opposite to that of the drain 15. In the HEMT device off state, the potential difference between the second source field plate 18 and the drain 15 will redistribute the electric field lines. The second source field plate 18 can provide symmetrical electric field modulation to ensure that the electric field is uniformly distributed circumferentially along the drain 15. The arrangement of the first source field plate 17 and the second source field plate 18 can further optimize the electric field distribution, improve the breakdown voltage, suppress current collapse and improve high-frequency characteristics.

[0107] Optionally, based on the above embodiments, Figure 14 This is a flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 15 This is a schematic diagram of some steps in a method for fabricating a semiconductor device according to another embodiment of the present invention, as shown below. Figure 14 As shown, the preparation method includes:

[0108] S400: Provides a substrate.

[0109] S410: A channel layer and a barrier layer are formed sequentially on one side of the substrate.

[0110] S420: At least one source and at least one drain are formed on the side of the barrier layer away from the substrate; the source and drain are spaced apart; at least two source and at least two drain are cross-distributed.

[0111] S430: A doped group III-V semiconductor layer corresponding to the source or drain is formed on the side of the barrier layer away from the substrate, and the doped group III-V semiconductor layer surrounds the drain.

[0112] S440: A first dielectric layer is formed on the side of the barrier layer, drain, source, and doped III-V semiconductor layer away from the substrate; the first dielectric layer includes a first contact hole corresponding to the source, and the vertical projection of the first contact hole onto the substrate is located within the vertical projection of the source onto the substrate.

[0113] S450: A first source field plate corresponding to the source or drain is formed on the side of the first dielectric layer away from the substrate; the first source field plate is connected to the source; the first source field plate surrounds the drain.

[0114] S460: A second dielectric layer is formed on the side of the first dielectric layer and the first source field plate away from the substrate; the second dielectric layer includes a second contact hole and a third contact hole, the vertical projection of the second contact hole on the substrate coincides with the vertical projection of the first contact hole on the substrate; the vertical projection of the third contact hole on the substrate is located within the vertical projection of the first source field plate on the substrate.

[0115] S470: A second source field plate is formed on the side of the second dielectric layer away from the substrate, corresponding one-to-one with the source or drain. The second source field plate is connected to the source. The second source field plate surrounds the drain.

[0116] Specifically, such as Figure 15 As shown, the second source field plate 18 can be formed on the side of the second dielectric layer 21 away from the substrate 11. The second source field plate 18 can be located on a different layer from the first source field plate 17. The arrangement of the first source field plate 17 and the second source field plate 18 can further optimize the electric field distribution, improve the breakdown voltage, suppress current collapse, and improve high-frequency characteristics.

[0117] S480: A third dielectric layer is formed on the side of the second dielectric layer and the second source field plate away from the substrate; the third dielectric layer includes a fourth contact hole, a fifth contact hole and a sixth contact hole; the vertical projection of the fourth contact hole on the substrate coincides with the vertical projection of the first contact hole on the substrate, the vertical projection of the fifth contact hole on the substrate coincides with the vertical projection of the third contact hole on the substrate, and the vertical projection of the sixth contact hole on the substrate is within the vertical projection of the second source field plate on the substrate.

[0118] Specifically, such as Figure 15 As shown, a third dielectric layer 31 is formed on the side of the second source field plate 18 and the second dielectric layer 21 away from the substrate 11. The third dielectric layer 31 may include a fourth contact hole 34, a fifth contact hole 35 and a sixth contact hole 36.

[0119] S490: A third metal plug is formed in the first contact hole, the second contact hole and the fourth contact hole, a fourth metal plug is formed in the third contact hole and the fifth contact hole, and a fifth metal plug is formed in the sixth contact hole.

[0120] Specifically, such as Figure 3 As shown, a third metal plug 32 is filled in the first contact hole 27, the second contact hole 26 and the fourth contact hole 34, a fourth metal plug 42 is filled in the third contact hole 30 and the fifth contact hole 35, and a fifth metal plug 33 is filled in the sixth contact hole 36.

[0121] S491: A second metal layer is formed on the side of the third dielectric layer away from the substrate; the second metal layer is connected to the source via a third metal plug, the second metal layer is also connected to the first source field plate via a fourth metal plug, and the second metal layer is also connected to the second source field plate via a fifth metal plug.

[0122] Specifically, such as Figure 3 As shown, a second metal layer 41 is formed on the side of the third dielectric layer 31 away from the substrate 11. The second metal layer 41 is connected to the source electrode 14 through a third metal plug 32, and is also connected to the first source field plate 17 through a fourth metal plug 42. Furthermore, the second metal layer 41 is connected to the second source field plate 18 through a fifth metal plug 33. This achieves the connection between the source electrode 14, the first source field plate 17, and the second source field plate 18.

[0123] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0124] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A semiconductor device, characterized in that, include: At least one single-cell structure; The unit cell structure includes: Substrate; A channel layer and a barrier layer, wherein the channel layer is located on one side of the substrate and the barrier layer is located on the side of the channel layer away from the substrate; The source and the drain are spaced apart on the side of the barrier layer away from the substrate; A group III-V semiconductor layer is located on the side of the barrier layer away from the substrate, and the group III-V semiconductor layer surrounds the drain electrode; A gate, the gate being located on the side of the group III-V semiconductor layer away from the substrate; A first source field plate is located on the side of the barrier layer away from the substrate, and the first source field plate is connected to the source electrode; the first source field plate surrounds the drain electrode; The vertical projection of the first source field plate onto the substrate is located between the vertical projection of the III-V semiconductor layer onto the substrate and the vertical projection of the drain onto the substrate; the vertical distance between the centerline of the first source field plate and the centerline of the III-V semiconductor layer is less than the vertical distance between the centerline of the first source field plate and the centerline of the drain.

2. The semiconductor device according to claim 1, characterized in that, The unit cell structure further includes: a second source field plate; The second source field plate is connected to the source electrode; the second source field plate is located on the side of the first source field plate away from the substrate, and the second source field plate surrounds the drain electrode.

3. The semiconductor device according to claim 2, characterized in that, The vertical projection of the second source field plate onto the substrate is located between the vertical projection of the III-V semiconductor layer onto the substrate and the vertical projection of the drain onto the substrate; the vertical distance between the centerline of the second source field plate and the centerline of the III-V semiconductor layer is less than the vertical distance between the centerline of the second source field plate and the centerline of the drain.

4. The semiconductor device according to claim 2, characterized in that, The vertical projection of the second source field plate onto the substrate overlaps with the vertical projection of the first source field plate onto the substrate. Alternatively, the vertical projection of the second source field plate onto the substrate does not overlap with the vertical projection of the first source field plate onto the substrate.

5. The semiconductor device according to claim 1, characterized in that, The unit cell structure further includes: a first dielectric layer, a second dielectric layer, a first metal layer, a first metal plug, and a second metal plug; The first dielectric layer is located on the side of the barrier layer, the drain, the source, the III-V semiconductor layer, and the gate away from the substrate, and the first source field plate is located on the side of the first dielectric layer away from the substrate; The second dielectric layer is located on the side of the first dielectric layer and the first source field plate away from the substrate; the first metal layer is located on the side of the second dielectric layer away from the substrate; The first dielectric layer includes a first contact hole, and the second dielectric layer includes a second contact hole and a third contact hole. The vertical projection of the first contact hole onto the substrate is located within the vertical projection of the source electrode onto the substrate. The vertical projection of the second contact hole onto the substrate coincides with the vertical projection of the first contact hole onto the substrate. The vertical projection of the third contact hole onto the substrate is located within the vertical projection of the first source field plate onto the substrate. The first metal plug fills the first contact hole and the second contact hole to connect the source electrode to the first metal layer. The second metal plug fills the third contact hole to connect the first source field plate to the first metal layer.

6. The semiconductor device according to claim 2, characterized in that, The unit cell structure includes: a first dielectric layer, a second dielectric layer, a third dielectric layer, a second metal layer, a third metal plug, a fourth metal plug, and a fifth metal plug; The first dielectric layer is located on the side of the barrier layer, the drain, the source, the III-V semiconductor layer, and the gate away from the substrate, and the first source field plate is located on the side of the first dielectric layer away from the substrate; the second dielectric layer is located on the side of the first dielectric layer and the first source field plate away from the substrate, and the second source field plate is located on the side of the second dielectric layer away from the substrate. The third dielectric layer is located on the side of the second dielectric layer and the second source field plate away from the substrate; the second metal layer is located on the side of the third dielectric layer away from the substrate; The first dielectric layer includes a first contact hole, the second dielectric layer includes a second contact hole and a third contact hole, and the third dielectric layer includes a fourth contact hole, a fifth contact hole, and a sixth contact hole. The first contact hole's vertical projection onto the substrate lies within the vertical projection of the source electrode onto the substrate. The vertical projections of the second and fourth contact holes onto the substrate coincide with the vertical projection of the first contact hole onto the substrate. The third contact hole's vertical projection onto the substrate lies within the vertical projection of the first source field plate onto the substrate. The vertical projection of the fifth contact hole onto the substrate coincides with the vertical projection of the third contact hole onto the substrate. The sixth contact hole's vertical projection onto the substrate lies within the vertical projection of the second source field plate onto the substrate. A third metal plug fills the first, second, and fourth contact holes to connect the source electrode to the second metal layer. A fourth metal plug fills the third and fifth contact holes to connect the first source field plate to the second metal layer. A fifth metal plug fills the sixth contact hole to connect the second source field plate to the second metal layer.

7. The semiconductor device according to claim 1, characterized in that, The distance between the side of the first source field plate near the drain and the side of the drain near the first source field plate is constant.

8. The semiconductor device according to claim 2, characterized in that, The distance between the side of the second source field plate near the drain and the side of the drain near the second source field plate is constant.

9. The semiconductor device according to claim 1, characterized in that, The III-V group semiconductor layer includes a P-type doped nitride layer, wherein the P-type doped nitride layer includes a P-type doped gallium nitride layer.

10. The semiconductor device according to claim 5 or 6, characterized in that, The first dielectric layer includes an aluminum nitride dielectric layer or an aluminum oxide dielectric layer, and the second dielectric layer includes a silicon nitride dielectric layer or a silicon oxide dielectric layer.

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