A Method for Analyzing the Backside EMMI Failure of BGA / LGA Devices

Abstract

The present invention discloses a method for analyzing the backside EMMI failure of BGA / LGA devices. This method analyzes the substrate layout of BGA / LGA devices obtained by grinding technology and uses X-ray technology to determine the one-to-one correspondence between the bonding wires and the device solder balls, providing accurate electrical connections for the backside EMMI of the devices and realizing the backside EMMI analysis of BGA / LGA devices. When performing backside EMMI on integrated circuits, it is first necessary to achieve correct electrical connections. Since there are numerous IO ports and the bonding wires are first re-routed through the substrate and then connected to the external solder joints. The present invention can quickly and simply obtain the one-to-one correspondence between the bonding wires and the external solder joints of BGA / LGA devices, thereby providing accurate electrical connections for the backside EMMI of BGA / LGA devices, realizing the backside EMMI failure analysis of BGA / LGA devices, expanding the applicability of the backside EMMI failure analysis of integrated circuits, and reducing the limitations of the backside EMMI of integrated circuits.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and particularly to a method for analyzing the backside EMMI failure of BGA / LGA devices. Background Art

[0002] For semiconductor devices, the Emission Microscope (EMMI) has been proven to be a quite useful and highly efficient defect localization tool, which is used to detect photons excited by electron-hole recombination and hot carriers.

[0003] With the reduction of device size and the increase of integration, the number of metal layers in the chip is increasing. Excessive metal layers will block the manifestation of the light emission effect of leakage from the front side. Therefore, for chips with more than 3 metal layers, EMMI is generally performed from the back side.

[0004] When performing backside EMMI, the back side of the device needs to be polished to expose the substrate of the silicon wafer encapsulated in the package, so that photons can pass through the silicon wafer and be received by the detector, thereby realizing defect localization.

[0005] When performing backside polishing, the lead-out terminals on the back side of the device are also polished off, leaving only the ends of the bonding wires. Then, probes are inserted into the signal input / output (IO) terminals and the power supply or ground terminals to achieve correct power-on.

[0006] Chinese Patent No. 201310028028.1 discloses a method for preparing a backside optical failure localization sample of an integrated circuit, including: Step 1, perform open / short circuit tests on the sample, apply a current using a tester ATE machine to determine whether the voltage is within the normal range, and proceed to the next analysis after determining that the open / short circuit test voltage is within the normal range; Step 2, use a manual polishing machine to polish the backside encapsulation material of the failed sample; Step 3, after opening the package, use an ultrasonic cleaner to clean the device, remove the residues remaining on the back side of the chip, and select room temperature constant temperature for 8-15 minutes of ultrasonic cleaning to obtain a clean sample and let it dry naturally; Step 4, measure the electrical characteristic parameters of the sample again using ATE (automatic tester) to confirm that the characteristics of the sample are exactly the same as before sample preparation, which can greatly improve the success rate of non-destructive opening and the speed of failure analysis. The present invention also relates to a method for analyzing the failure of this sample.

[0007] Chinese Patent No. 201010605339.6 discloses a method for failure analysis of semiconductor devices, which includes the steps of: removing the copper layer on the back of the semiconductor device; thinning the silicon layer on the back of the semiconductor device; and using a low-light microscope (EMMI) and / or an OBIRCH (Optical Beam Induced Resistance Change) electrical positioning device to locate the failure point on the back of the semiconductor device. By removing copper, thinning the silicon layer and locating the failure point on the back of the semiconductor device, this failure analysis method saves time and improves efficiency and success rate.

[0008] Chinese Patent No. 201310028028.1 introduces a sample preparation and analysis method for backside optical failure location of integrated circuits. This method is a conventional method for backside EMMI of integrated circuits and is applicable to devices with packages such as DIP, SOP, LCC, QFN, etc. It can obtain the back of the chip well without damaging the lead frame and achieve electrical connection for failure point location. However, for BGA / LGA devices, if the back of the chip needs to be exposed, the entire lead frame must be ground away, and it is impossible to determine the electrical connection mode of the failure point using this method.

[0009] Chinese Patent No. 201010605339.6 mainly aims at the situation where large blocks of aluminum (such as DMOS) cover the surface of semiconductor devices, and photons cannot penetrate the aluminum when using EMMI for failure analysis. Summary of the Invention

[0010] The technical object of the present invention is to provide a backside EMMI failure analysis method for BGA / LGA devices, which can effectively improve the analysis efficiency of backside EMMI of such devices without requiring the device design manufacturer to provide the correspondence between bonding wires and external solder joints. The technical principle of the present invention is to analyze the substrate layout of BGA / LGA devices obtained by grinding technology and adopt X-ray technology to determine the one-to-one correspondence between bonding wires and device solder balls, provide accurate electrical connection for backside EMMI of the device, and thus realize backside EMMI analysis of BGA / LGA devices. When performing backside EMMI of integrated circuits, correct electrical connection must be achieved first. The prior art is only applicable to devices with packages such as DIP, SOP, LCC, QFN, etc. Because they have fewer IO ports and the bonding wires correspond to the IO ports one by one, it is easy to achieve electrical connection for backside EMMI. For backside EMMI of BGA / LGA devices, because they have numerous IO ports and the bonding wires are first re-routed through the substrate and then connected to the external solder joints ( Figure 1 ), a simple one-to-one correspondence cannot be achieved. It is necessary to rely on the correspondence between bonding wires and external solder joints provided by the device design manufacturer to determine the electrical connection relationship of backside EMMI. For device users, such correspondence is generally unavailable, which brings great limitations to the failure analysis of BGA / LGA devices.

[0011] To solve the problems in the above-mentioned background technology and achieve the technical objectives of the present invention, the technical solution adopted by the present invention is a method for analyzing the backside EMMI failure of BGA / LGA devices, and this method includes the following steps:

[0012] In the first step, perform a volt-ampere (IV) characteristic test on the BGA / LGA device to obtain the volt-ampere characteristic curve of the failed pin, and determine the position of the failed pin in the external solder joints.

[0013] In the second step, grind off the external solder joints of the failed BGA / LGA device to expose the pads and vias, determine the positions of the pads and vias of the failed pin according to the data sheet of the BGA / LGA device, and take a photo of this layer of layout.

[0014] In the third step, grind the substrate of the failed pin of the BGA / LGA device to expose the copper-clad layer, and determine the position of the failed pin via in the copper-clad layer.

[0015] In the fourth step, repeat the substrate grinding in the third step, perform layer-by-layer grinding until the last layer of metal wiring on the substrate is exposed, and confirm the position where the failed pin via is located.

[0016] In the fifth step, perform a volt-ampere curve test on the metal wiring where the failed pin via is located to obtain a volt-ampere curve, and compare it with the volt-ampere characteristic curve obtained in the first step for confirmation; if the volt-ampere curve in the fifth step is the same as or similar to the volt-ampere characteristic curve obtained in the first step (due to resistance changes caused by grinding the substrate), then proceed to the sixth step. If they are not the same, there are two possibilities: 1) The positioning of the failed pin is incorrect, then it is necessary to compare the substrate layouts obtained in the second to fifth steps and reconfirm the position of the failed pin; 2) The failure location is on the substrate rather than on the chip.

[0017] In the sixth step, perform an X-ray photograph on the BGA / LGA device to determine the position of the bonding wire connected to the metal wiring connected to the failed pin via, and record this position.

[0018] In the seventh step, grind off the last layer of metal wiring to expose the silicon wafer substrate and the bonding wire head, and find the position of the bonding wire recorded in the sixth step.

[0019] In the eighth step, insert the probe to the head end of the bonding wire of the failed pin and the power supply or ground end to achieve correct power supply.

[0020] In the ninth step, perform backside EMMI. Through backside EMMI, one-to-one correspondence between the bonding wire and the external solder joint is achieved, thereby providing accurate electrical connection for the backside EMMI of the integrated circuit and realizing the backside EMMI failure analysis of the integrated circuit.

[0021] The technical effects that the present invention can achieve are:

[0022] The existing integrated circuit backside EMMI technology is only applicable to devices with packages such as DIP, SOP, LCC, QFN, etc. It can obtain the backside of the chip well without damaging the lead frame and achieve electrical connection for failure point location. For the backside EMMI of BGA / LGA devices, since it is necessary to rely on the corresponding relationship between the bonding wires and the external solder joints provided by the device design manufacturer to determine the electrical connection relationship of the backside EMMI. For device users, generally such corresponding relationships cannot be obtained, which brings great limitations to the failure analysis of BGA / LGA devices.

[0023] The present invention can quickly and simply obtain the one-to-one correspondence between the bonding wires and the external solder joints of BGA / LGA devices, thereby providing accurate electrical connection for the backside EMMI of BGA / LGA devices, realizing the backside EMMI failure analysis of BGA / LGA devices, expanding the applicability of the integrated circuit backside EMMI failure analysis, and reducing the limitations of the integrated circuit backside EMMI. Brief Description of the Drawings

[0024] Some specific embodiments of the present invention will be described in detail hereinafter with reference to the accompanying drawings in an illustrative but not restrictive manner.

[0025] The same reference numerals in the drawings denote the same or similar components or parts. Those skilled in the art should understand that these

[0026] drawings are not necessarily drawn to scale. In the drawings:

[0027] Figure 1 It shows a longitudinal structure diagram of a BGA device.

[0028] Figure 2 It is the backside of the failed sample in the embodiment of the present invention.

[0029] Figure 3 It is the morphology of the backside of the failed sample in the embodiment of the present invention after grinding off the solder joints.

[0030] Figure 4 It is the copper-clad layer of the substrate of the failed sample in the embodiment of the present invention.

[0031] Figure 5 It is the X-ray photo of the substrate of the failed sample in the embodiment of the present invention.

[0032] Figure 6 It is the effect diagram of performing backside EMMI in the embodiment of the present invention. Detailed Description of the Specific Embodiments

[0033] The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0034] A method for backside EMMI failure analysis of BGA / LGA devices. In the first step, perform a volt-ampere (IV) characteristic test on the failed pins of the BGA / LGA device. The backside topography of the device is shown in Figure 2 .

[0035] In the second step, grind off the external solder joints of the failed BGA / LGA device to expose the pads and vias. According to the device's data sheet, determine the positions of the pads and vias of the failed pins, as shown in Figure 3 ;

[0036] In the third step, grind the substrate to expose the copper-clad layer and determine the position of the via of the failed pin in the copper-clad layer, as shown in Figure 4 ;

[0037] In the fourth step, repeat the third step, grind the substrate layer by layer until the last layer is exposed to reveal the metal wiring, as shown in Figure 5 ;

[0038] In the fifth step, perform an IV curve test on the metal wiring where the via of the failed pin is located and compare it with the IV curve obtained in the first step for confirmation;

[0039] In the sixth step, take an X-ray photo of the device to determine the positional relationship between the bonding wires and the metal wiring of the failed pins, as shown in Figure 5 ;

[0040] In the seventh step, grind the substrate to expose the silicon wafer substrate and the bonding wire heads;

[0041] In the eighth step, insert the probe into the head end of the bonding wire of the failed pin and the power supply or ground end to achieve correct power-on.

[0042] In the ninth step, perform backside EMMI.

Claims

1. A method for backside EMMI failure analysis of BGA / LGA devices, characterized in that, The method includes the following steps: In the first step, perform a volt-ampere characteristic test on the BGA / LGA device to obtain the volt-ampere characteristic curve of the failed pin and determine the position of the failed pin in the external solder joints; In the second step, grind away the external solder joints of the failed BGA / LGA device to expose the pads and vias, determine the positions of the pads and vias of the failed pin according to the data sheet of the BGA / LGA device, and take a photo of this layer of layout; In the third step, grind the substrate of the failed pin of the BGA / LGA device to expose the copper-clad layer and determine the position of the via of the failed pin in the copper-clad layer; In the fourth step, repeat the substrate grinding in the third step, perform layer-by-layer grinding until the last layer of metal wiring on the substrate is exposed, and confirm the position where the via of the failed pin is located; In the fifth step, perform a volt-ampere curve test on the metal wiring where the via of the failed pin is located to obtain a volt-ampere curve, and compare and confirm it with the volt-ampere characteristic curve obtained in the first step; In the sixth step, take an X-ray photo of the BGA / LGA device to determine the position of the bonding wire connected to the metal wiring connected to the via of the failed pin, and record this position; In the seventh step, grind away the last layer of metal wiring to expose the silicon wafer substrate and the bonding wire head, and find the position of the bonding wire recorded in the sixth step; In the eighth step, insert the probe into the head end of the bonding wire of the failed pin and the power supply or ground end to achieve correct power-on; In the ninth step, perform backside EMMI; through backside EMMI, establish a one-to-one correspondence between the bonding wire and the external solder joint, thereby providing an accurate electrical connection for the backside EMMI of the integrated circuit and realizing the backside EMMI failure analysis of the integrated circuit; In the fifth step, if the volt-ampere curve in the fifth step is the same as or similar to the volt-ampere characteristic curve obtained in the first step, then proceed to the sixth step; if they are not the same, there are two possibilities: 1) The positioning of the failed pin is incorrect, and in this case, it is necessary to compare the substrate layout obtained in the second to fifth steps and reconfirm the position of the failed pin; 2) The failure location is on the substrate rather than on the chip.

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