Stepped slot insulated gate bipolar transistor and its fabrication method

Abstract

This invention provides a stepped trench insulated-gate bipolar transistor and its fabrication method. The method includes forming an N-type carrier storage layer on an N-type silicon substrate; forming a front-side P-type well region above the N-type carrier storage layer; etching a first trench and forming a highly doped storage layer via As ion implantation; depositing an oxide layer within the first trench; etching a second trench and forming a shielding gate oxide layer within the second trench; etching a third trench and forming a control gate within the third trench; forming a doped contact region on the front side of the N-type silicon substrate, above the P-type well region, and forming an emitter on the contact region; forming a back-side N-well region on the back side of the N-type silicon substrate via N-type ion implantation, and then forming a back-side P-well region via P-type ion implantation, wherein the back-side P-well region is located at the bottom, and the back-side N-well region is located above the back-side P-well region. This invention improves the efficiency of forming a highly doped storage layer and can significantly reduce the conduction loss of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a stepped groove insulated gate bipolar transistor and its fabrication method. Background Technology

[0002] The rapid development of power technology has created a huge demand for high-speed, low-cost, and high-efficiency power electronic devices. Over the past few decades, the Insulated Gate Bipolar Transistor (IGBT) has improved its breakdown characteristics and on-state voltage drop (V0). ON ) and shutdown energy loss (E OFF The development of IGBTs has been driven by the need for an optimal balance between performance and energy density. To date, various IGBT structures and technologies have been proposed and studied to improve their performance, such as field-terminated IGBTs (FS-IGBTs), injection-enhanced gate transistors (IEGTs), and carrier storage slot-gate bipolar transistors (CSTBTs). Specifically, CSTBTs can significantly reduce the on-state voltage by improving the carrier distribution in slot-type IGBTs, making them promising candidates for next-generation power electronic devices.

[0003] However, existing CSTBTs still have limitations, and achieving a high-doping concentration CS layer using current technology remains a technical challenge. Because the CS layer is located at the bottom of the P-body, directly adjusting the doping concentration through high-energy ion implantation is not feasible. Typically, the CS layer is formed through n-type ion implantation (mainly phosphorus) followed by multiple high-temperature annealing and diffusion processes. Therefore, the carrier distribution in the CS layer is always wider than ideal, and the implantation efficiency remains relatively low. Summary of the Invention

[0004] The purpose of this invention is to provide a stepped trench insulated gate bipolar transistor and its fabrication method, which improves the efficiency of forming a highly doped storage layer and can significantly reduce the conduction loss of the device.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a method for fabricating a stepped-groove insulated-gate bipolar transistor, comprising:

[0006] An N-type carrier storage layer is formed by implanting ions onto an N-type silicon substrate.

[0007] Ions are injected above the N-type carrier storage layer to form a front-side P-type well region;

[0008] The first trench is etched to form the first trench, and As ions are implanted in the first trench to form a highly doped storage layer below the N-type carrier storage layer.

[0009] A first oxide layer is deposited in the first trench;

[0010] The second trench is etched, and a shielding gate oxide layer is formed in the second trench;

[0011] The third trench is etched, and a left-right symmetrical control gate is formed in the third trench;

[0012] A doping contact region is formed on the front side of the N-type silicon substrate and above the P-type well region, and an emitter is formed on the contact region.

[0013] A back-side N-well region is formed on the back side of the N-type silicon substrate by N-type ion implantation, and then a back-side P-well region is formed by P-type ion implantation, wherein the back-side P-well region is located at the bottom and the back-side N-well region is located above the back-side P-well region.

[0014] In some embodiments, the etching forms a first trench, and As ion implantation is performed within the first trench to form a highly doped storage layer beneath the N-type carrier storage layer, including:

[0015] The first trench is etched on the N-type silicon substrate until the first trench extends to the bottom of the N-type carrier storage layer;

[0016] A highly doped storage layer is formed within the first trench by As ion implantation, and the highly doped storage layer is located below the N-type carrier storage layer.

[0017] In some embodiments, the deposition of the first oxide layer in the first trench includes:

[0018] The first oxide layer completely fills the first trench;

[0019] The surface of the first oxide layer was planarized using chemical mechanical polishing.

[0020] In some embodiments, etching the second trench and forming a shielding gate oxide layer within the second trench includes:

[0021] A second trench is etched on the first oxide layer, the bottom of the second trench passing through the second oxide layer and the highly doped storage layer and extending to the N-type drift region on the N-type silicon substrate;

[0022] A second oxide layer is deposited in the second trench to form the shielding gate oxide layer.

[0023] In some embodiments, after depositing the second oxide layer in the second trench to form the shielding gate oxide layer, the process includes:

[0024] A first polysilicon layer is filled on the second oxide layer, and the first polysilicon layer completely fills the second trench;

[0025] The etching of the third trench, and the formation of a left-right symmetrical control gate within the third trench, includes:

[0026] The third trench is etched on both sides of the first polysilicon layer, and the third trench extends to the second oxide layer;

[0027] A second polysilicon layer is deposited in the third trench to form the control gate, which is symmetrical from left to right.

[0028] In some embodiments, forming a doped contact region on the front side of the N-type silicon substrate and above the P-type well region, and forming an emitter on the contact region, includes:

[0029] After planarizing the second polycrystalline silicon layer using chemical mechanical polishing, N-type ion implantation and P-type ion implantation are performed on the front side of the N-type silicon substrate and above the P-type well region to form the contact region.

[0030] The beneficial effects of this invention are as follows: by performing additional arsenic ion implantation during the formation of the stepped trench, a highly doped carrier storage layer is achieved, thereby improving the efficiency of forming a highly doped storage layer. The highly doped storage layer results in a higher hole carrier density near the emitter, which significantly reduces the conduction loss of the device.

[0031] In a second aspect, embodiments of the present invention provide a stepped-groove insulated-gate bipolar transistor, which is fabricated using the aforementioned method for fabricating a stepped-groove insulated-gate bipolar transistor, wherein the stepped-groove insulated-gate bipolar transistor includes an N-type silicon substrate.

[0032] The front side of the N-type silicon substrate has a front-side P-type well region, a carrier storage layer, a highly doped storage layer, a contact region, and an emitter. The emitter is located above the contact region, the contact region is located above the front-side P-type well region, the front-side P-type well region is located above the carrier storage layer, and the carrier storage layer is located above the highly doped storage layer.

[0033] The N-type silicon substrate has a second trench and a third trench, and a shielding gate oxide layer is formed in the second trench, and a left-right symmetrical control gate is formed in the third trench.

[0034] The back side of the N-type silicon substrate has a back P-well region and a back N-well region, wherein the back P-well region is located at the bottom and the back N-well region is located above the back P-well region.

[0035] The beneficial effects of this invention are as follows: During the formation of the stepped trench, the additional injection of As ions improves the efficiency of forming a highly doped storage layer. Furthermore, the highly doped storage layer in this embodiment results in a higher hole carrier density near the emitter, thereby significantly reducing the device's conduction loss. The newly introduced carriers accumulate only on the emitter side; when the device is turned off, these carriers are first depleted from the emitter side, which will affect the device's E... OFF The impact is negligible. Attached Figure Description

[0036] Figure 1 A flowchart illustrating the fabrication method of a stepped groove insulated gate bipolar transistor according to an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the structure of a stepped slot insulated gate bipolar transistor provided by the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art to which this invention pertains. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Unless otherwise specified, the term "connection" as used herein can refer to a direct connection or an indirect connection, i.e., a connection through an intermediate object.

[0039] To address the problems existing in the prior art, embodiments of the present invention provide a method for fabricating a stepped groove insulated gate bipolar transistor, comprising:

[0040] S101: Ions are implanted on an N-type silicon substrate to form an N-type carrier storage layer.

[0041] In this step, an N-type silicon substrate is formed using epitaxial technology, and then N-type ions, such as phosphorus (P) ions, are implanted deep into the N-type silicon substrate to form an N-type carrier storage layer. The doping concentration of the N-type carrier storage layer is 4 × 10⁻⁶. 14 cm -3 .

[0042] S102: Ions are injected above the N-type carrier storage layer to form a front-side P-type well region.

[0043] In this step, P-type ions, such as boron (B) ions, are implanted shallowly into the N-type silicon substrate to form a front-side P-type well region above the N-type carrier storage layer. The doping concentration of the P-type well region is 3 × 10⁻⁶. 16 cm -3 .

[0044] S103: Etch to form a first trench, and perform As ion implantation in the first trench to form a highly doped storage layer below the N-type carrier storage layer.

[0045] In this step, a relatively wide and shallow first trench is formed by dry etching until it extends to the bottom of the N-type carrier storage layer. Then, a highly doped storage layer is formed within the first trench by As ion implantation. This highly doped storage layer is located below the N-type carrier storage layer. The doping concentration of the highly doped storage layer is 1.5 × 10⁻⁶. 17 cm -3 .

[0046] S104: Deposit a first oxide layer in the first trench.

[0047] Specifically, this step involves depositing the first oxide layer in the first trench until the first oxide layer completely fills the first trench.

[0048] S105: Etch the second trench and form a shielding gate oxide layer in the second trench.

[0049] In this step, the surface of the first oxide layer is planarized beforehand using chemical mechanical polishing, and then a second trench is etched on the first oxide layer. The second trench is a deep trench, with its bottom penetrating the second oxide layer, the highly doped storage layer, and extending to the N-type drift region on the N-type silicon substrate. By embedding the bottom of the second trench (deep trench) into the N-type drift region, the Miller capacitance of the device can be reduced, while simultaneously improving the breakdown voltage characteristics.

[0050] Next, a second oxide layer is deposited in the second trench to form the shielding gate oxide layer.

[0051] S106: Etch the third trench and form a left-right symmetrical control gate in the third trench.

[0052] In this step, a first polysilicon layer is filled on the second oxide layer, and the first polysilicon layer completely fills the second trench. Then, the third trench is etched on both sides of the first polysilicon layer using photolithography. The third trench extends to the second oxide layer. Then, a second polysilicon layer is deposited in the third trench to form the control gate that is symmetrical from left to right.

[0053] S107: A doping contact region is formed on the front side of the N-type silicon substrate and above the P-type well region, and an emitter is formed on the contact region.

[0054] S108: A back N-well region is formed on the back side of the N-type silicon substrate by N-type ion implantation, and then a back P-well region is formed by P-type ion implantation, wherein the back P-well region is located at the bottom and the back N-well region is located above the back P-well region.

[0055] In traditional processes, the carrier storage layer (CS layer) is formed by long-term annealing after N-type phosphorus ion implantation. This method is inefficient, has a wide doping distribution, and a low peak doping concentration, leading to a weakened CS layer effect. In this embodiment, As ions are additionally implanted during the formation of the stepped trenches (i.e., the first trench and the second trench), improving the efficiency of forming a highly doped storage layer. Furthermore, the highly doped storage layer in this embodiment results in a higher hole carrier density near the emitter, significantly reducing the device's on-state loss. Newly introduced carriers accumulate only on the emitter side; when the device is turned off, these carriers are first depleted from the emitter side, which will affect the device's turn-off energy loss (E0). OFF The impact is negligible.

[0056] While using a deeper trench gate in conventional CSTBT devices can improve the breakdown voltage of highly doped memory layers, this structure significantly increases the main capacitance, especially the gate / collector capacitance (C). GC C GC The Miller effect caused by this will significantly degrade switching performance. In this embodiment, the deep trench (second trench) structure connects to the emitter instead of the gate, which has a negative impact on device C. GC The effect is negligible. Under constant on-state voltage drop (VON), the gate-collector charge (C) in this embodiment is negligible. GC ) and shutdown energy loss (E OFF The decline in all these factors makes it a promising candidate for future applications in power electronic devices.

[0057] In another embodiment of the present invention, a stepped-groove insulated-gate bipolar transistor is provided. It should be noted that the stepped-groove insulated-gate bipolar transistor is fabricated using the method described in the above embodiments. (Refer to...) Figure 2As shown, the substrate includes an N-type silicon substrate. The front side of the N-type silicon substrate has a front-side P-type well region 3, a carrier storage layer 4, a highly doped storage layer 6, a contact region 2, and an emitter 1. The emitter 1 is located above the contact region 2, the contact region 2 is located above the front-side P-type well region 3, the front-side P-type well region 3 is located above the carrier storage layer 4, and the carrier storage layer 4 is located above the highly doped storage layer 5. The N-type silicon substrate has a second trench and a third trench. A shielding gate oxide layer is formed in the second trench, and a left-right symmetrical control gate 5 is formed in the third trench. The bottom of the second trench extends to an N-type drift region 7 on the N-type silicon substrate. The back side of the N-type silicon substrate has a back-side P-well region 8 and a back-side N-well region 9, wherein the back-side P-well region 9 is located at the bottom, and the back-side N-well region 8 is located above the back-side P-well region 9.

[0058] In this embodiment, additional As ions are injected during the formation of the stepped trenches (i.e., the first trench and the second trench), improving the efficiency of forming a highly doped storage layer. Furthermore, the highly doped storage layer in this embodiment results in a higher hole carrier density near the emitter, significantly reducing the device's on-state loss. The newly introduced carriers accumulate only on the emitter side; when the device is turned off, these carriers are first depleted from the emitter side, which will affect the device's turn-off energy loss (E). OFF The impact is negligible.

[0059] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.

Claims

1. A method for fabricating a stepped-groove insulated-gate bipolar transistor, characterized in that, include: An N-type carrier storage layer is formed by implanting ions onto an N-type silicon substrate. Ions are injected above the N-type carrier storage layer to form a front-side P-type well region; The first trench is etched to form the first trench, and As ions are implanted in the first trench to form a highly doped storage layer below the N-type carrier storage layer. A first oxide layer is deposited in the first trench; The second trench is etched, and a shielding gate oxide layer is formed in the second trench; The third trench is etched, and a left-right symmetrical control gate is formed in the third trench; A doping contact region is formed on the front side of the N-type silicon substrate and above the P-type well region, and an emitter is formed on the contact region. A back-side N-well region is formed on the back side of the N-type silicon substrate by N-type ion implantation, and then a back-side P-well region is formed by P-type ion implantation, wherein the back-side P-well region is located at the bottom and the back-side N-well region is located above the back-side P-well region.

2. The preparation method according to claim 1, characterized in that, The etching forms a first trench, and As ions are implanted within the first trench to form a highly doped storage layer beneath the N-type carrier storage layer, including: The first trench is etched on the N-type silicon substrate until the first trench extends to the bottom of the N-type carrier storage layer; A highly doped storage layer is formed within the first trench by As ion implantation, and the highly doped storage layer is located below the N-type carrier storage layer.

3. The preparation method according to claim 2, characterized in that, The deposition of the first oxide layer in the first trench includes: The first oxide layer completely fills the first trench; The surface of the first oxide layer was planarized using chemical mechanical polishing.

4. The preparation method according to claim 3, characterized in that, The etching of the second trench and the formation of a shielding gate oxide layer within the second trench includes: A second trench is etched on the first oxide layer, the bottom of the second trench passing through the first oxide layer and the highly doped storage layer and extending to the N-type drift region on the N-type silicon substrate; A second oxide layer is deposited in the second trench to form the shielding gate oxide layer.

5. The preparation method according to claim 4, characterized in that, After depositing a second oxide layer in the second trench to form the shielding gate oxide layer, the process includes: A first polysilicon layer is filled on the second oxide layer, and the first polysilicon layer completely fills the second trench; The etching of the third trench, and the formation of a left-right symmetrical control gate within the third trench, includes: The third trench is etched on both sides of the first polysilicon layer, and the third trench extends to the second oxide layer; A second polysilicon layer is deposited in the third trench to form the control gate, which is symmetrical from left to right.

6. The preparation method according to claim 5, characterized in that, The process of forming a doped contact region on the front side of the N-type silicon substrate and above the P-type well region, and forming an emitter on the contact region, includes: After planarizing the second polycrystalline silicon layer using chemical mechanical polishing, N-type ion implantation and P-type ion implantation are performed on the front side of the N-type silicon substrate and above the P-type well region to form the contact region.

7. A stepped slot insulated gate bipolar transistor, characterized in that, The stepped-groove insulated-gate bipolar transistor is fabricated using the fabrication method of any one of claims 1 to 6, wherein the stepped-groove insulated-gate bipolar transistor includes an N-type silicon substrate; The front side of the N-type silicon substrate has a front-side P-type well region, a carrier storage layer, a highly doped storage layer, a contact region, and an emitter. The emitter is located above the contact region, the contact region is located above the front-side P-type well region, the front-side P-type well region is located above the carrier storage layer, and the carrier storage layer is located above the highly doped storage layer. The N-type silicon substrate has a second trench and a third trench, and a shielding gate oxide layer is formed in the second trench, and a left-right symmetrical control gate is formed in the third trench. The back side of the N-type silicon substrate has a back P-well region and a back N-well region, wherein the back P-well region is located at the bottom and the back N-well region is located above the back P-well region.

Images