Wireless controlled low power supply starting circuit and starting method

Abstract

The application relates to a wireless control low-power power supply starting circuit, which comprises a signal receiving module, a voltage generating module, a decoding module and a load driving module, the signal receiving module is responsible for outputting low levels with different time lengths according to the length of received network information; the voltage generating module is connected with the signal receiving module and outputs corresponding voltages according to the time length of the low level output by the signal receiving module; the decoding module is responsible for generating signals to start the power supply to supply power to the load according to the voltage of the voltage generating module; and the load driving module is responsible for receiving the signals of the decoding module to start or disconnect the load power supply. Since different output pins of the decoder are adopted to control the starting and shutdown of different load power supplies, the starting of each load power supply does not interfere with the power supply to the load. In addition, since the MCU which needs to be programmed with a large program is not involved, the energy loss caused by the MCU running the program can be reduced, and the system power consumption is further reduced.

Description

Technical Field

[0001] This invention relates to a wireless control low-power power output technology, specifically a wireless control low-power power start-up circuit and start-up method. Background Technology

[0002] The concept of smart city transportation is gaining increasing popularity among scholars, with sensors deployed throughout cities greatly facilitating people's travel and daily life. Numerous sensors transmit information wirelessly, but these devices typically have short lifespans due to size and battery capacity limitations, requiring strict power management. Currently, most smart city nodes communicate wirelessly via various links, such as IEEE 802.15.4, IEEE 802.15.4g, IEEE 802.11 (Bluetooth), and Low Energy 802.11. Wake-up Radio (MuR) technology is emerging as a promising method for low-power wireless communication, enabling purely asynchronous, on-demand communication while significantly reducing unnecessary energy waste. By connecting an auxiliary ultra-low-power receiver to the wireless device, the master MCU (Microcontroller Unit) can switch it to a minimum power mode, in which case the slave device is in listening mode. It is reactivated when the master device sends a special radio frequency (RF) signal to the slave device, causing an interrupt.

[0003] Currently, for low-power wireless devices requiring large program installations, most rely on MCU-based programmable load switching circuits to receive and determine wake-up or sleep signals because the RF signals transmitted by the nodes cannot be identified. The MCU's role is address decoding and interference filtering; it monitors and decodes the RF signal after rectification and amplification, and notifies the master node via an interrupt. This additional MCU hardware intervention incurs extra energy consumption. For low-power wireless devices that do not require program installation, a correlator circuit can be used for RF signal matching without MCU decoding. In the correlator circuit, the node address is stored in a reference signal buffer, and the input bits of the RF signal are associated with the reference signal. When a new byte is available, all samples are shifted one bit to the right in the correlator and compared with pre-stored samples. If the stored bit and input bit match, the wake-up interrupt pin is activated. While eliminating the MCU reduces energy consumption, it prevents the node from actively returning to sleep mode after waking up. Furthermore, when devices use the same channel or radio frequency for transmission and reception, interference signals may mistakenly wake up the node, leading to unnecessary safety hazards. Summary of the Invention

[0004] To address the shortcomings of the existing technologies, this invention proposes a low-power power-on circuit and startup method for wireless control.

[0005] The technical solution of the invention is as follows:

[0006] A low-power power-on circuit for wireless control includes a signal receiving module, a voltage generation module, a decoding module, and a load driving module. The signal receiving module receives network information sent by the master device and outputs low-level signals of different durations based on the length of the received network information. The voltage generation module is connected to the signal receiving module and outputs a corresponding voltage based on the duration of the low-level signals output by the signal receiving module, and transmits this voltage to the decoding module. The decoding module receives the voltage from the voltage generation module and generates a signal based on the magnitude of the voltage to start the power supply and provide power to the corresponding load. The load driving module receives the signal from the decoding module and starts or disconnects the load power supply based on the signal.

[0007] Furthermore, the voltage generation module includes a PNP transistor Q3. The emitter of transistor Q3 is connected to the power supply, the collector of transistor Q3 is grounded through resistor R3 and C1 in sequence, and the base of transistor Q3 is connected to the output terminal of the signal receiving module.

[0008] Furthermore, the decoding module includes dual-limit voltage comparators D1, D2, and D3. The connection point of capacitors C1 and R3 is connected to the input terminals of the three dual-limit voltage comparators D1, D2, and D3. The threshold values ​​of dual-limit voltage comparators D1, D2, and D3 are set to be greater than 2.5V, 1V-2.5V, and 0-1V, respectively. The outputs of dual-limit voltage comparators D1, D2, and D3 are connected to the input terminals of the decoder through D flip-flops U1, U3, and U5, respectively. Each output terminal of the decoder is connected to each load power supply. The input terminal of the series D flip-flop counter is connected to the connection point of capacitors C1 and R3, and the output terminal is connected to the enable terminal of the decoder. The decoder is a 74HC138 decoder.

[0009] Furthermore, the load drive module includes PNP transistors Q1 and Q2, an NPN transistor Q4, and an NOT gate U4. The input of NOT gate U4 is connected to the output of the decoder, the output of NOT gate U4 is connected to the input of D flip-flop U2, and the output of D flip-flop U2 is connected to the base of transistor Q1. A resistor R1 is connected between the emitter and base of transistor Q2, the base of transistor Q2 is grounded through resistor R14, and the collector of transistor Q1 is connected to the base of transistor Q2. The base of transistor Q2 is connected to the base of transistor Q1. The collector of transistor Q2 is grounded through resistors R2 and R5 in sequence. The collector of transistor Q4 is connected to the collector of transistor Q1. The emitter of transistor Q4 is grounded through resistor R6. The output of NOT gate U4 is connected to the base of transistor Q4 through a forward-conducting diode D3 and resistor R4 in sequence. The connection point of diode D3 and resistor R4 is connected to the connection point of resistors R2 and R5. The collector of transistor Q2 is grounded through the load.

[0010] Furthermore, the outputs of the dual-limit voltage comparators D1, D2, and D3 are grounded through resistors R10, R11, and R12, respectively, and the outputs of the D flip-flops U1, U3, and U5 are grounded through resistors R9, R8, and R7, respectively.

[0011] The present invention also provides a low-power power-on method for wireless control, comprising the following steps:

[0012] The first step is for the signal reading module to listen to the network information sent by the master device to wake up the low-power power supply and obtain the duration of the signal from the network information.

[0013] The second step is that the signal reading module sends a low level to the voltage generation module. The duration of this low level is proportional to the duration of the signal. The PNP transistor Q3 in the voltage generation module is turned on, charging the capacitor C1 and transmitting the voltage of the capacitor C1 to the input terminals of the three dual-limit voltage comparators D1, D2 and D3.

[0014] The third step involves using the three dual-limit voltage comparators D1, D2, and D3 in the decoding module to conduct the corresponding D flip-flops based on the voltage values ​​output by the three dual-limit voltage comparators D1, D2, and D3, and increment the counter of the conducted D flip-flops by 1.

[0015] Fourth step: When the series D flip-flop counter counts to 3, the series D flip-flop counter outputs a low level to the EN pin of the 74HC138 decoder, and at the same time the series D flip-flop counter returns to zero.

[0016] Fifth, the low level is flipped to a high level by a NOT gate. An odd number of times a pin of the 74HC138 decoder is turned on can supply power to the load of the self-locking circuit, thereby realizing low-power power-on without MCU wireless control. An even number of times the pin of the 74HC138 decoder is turned on again can realize the shutdown function.

[0017] Furthermore, the method for turning on the corresponding D flip-flops with the voltage values ​​output by the three dual-limit voltage comparators D1, D2 and D3 is as follows: the threshold of dual-limit voltage comparator D1 is set to be greater than 2.5V, the threshold of dual-limit voltage comparator D2 is set to 1V-2.5V, and the threshold of dual-limit voltage comparator D3 is set to 0V-1V.

[0018] When the voltage input to the three dual-limit voltage comparators is greater than 2.5V, D flip-flop U1 is turned on; when the voltage input to the three dual-limit voltage comparators is between 1V and 2.5V, D flip-flop U3 is turned on; when the voltage input to the three dual-limit voltage comparators is between 0V and 1V, D flip-flop U5 is turned on.

[0019] Compared with the prior art, the present invention has the following advantages:

[0020] 1. This invention can use a slave device to control the on and off of multiple load power supplies. Since different output pins of the decoder are used to control the on and off of different load power supplies, the start-up of each load power supply does not interfere with the power supply to the load.

[0021] 2. The method of this invention can ensure that when the power-on circuit fails to power normally, the wake-up radio frequency signal can be temporarily stored in the D flip-flop and will not be lost, so that the electronic device will not be affected by abnormal interference and thus will not be affected in normal operation.

[0022] 3. The low-power power-on circuit for wireless control involved in this invention does not involve an MCU that requires programming a large program, thus reducing the energy loss caused by the MCU running the program and further reducing the system power consumption. Attached Figure Description

[0023] Figure 1 This is the circuit schematic diagram of the present invention. Detailed Implementation

[0024] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings. In the description of this application, it should be understood that, unless otherwise explicitly stated, the terms "installation," "placement," "setting," "connection," and "fixing," etc., should be interpreted broadly and may be understood as fixed connection or detachable connection, etc., depending on the specific technical solution in which they are applied. Those skilled in the art can understand the specific meaning of the above terms based on the specific circumstances involved in the technical solution.

[0025] Figure 1 The circuit shown is a low-power power-on circuit for wireless control, comprising a signal receiving module, a voltage generation module, a decoding module, and a load driving module. The signal receiving module, which can be implemented using an RF module, is responsible for receiving network information sent by the master device. Upon receiving network information, it outputs a low-level signal of varying duration based on the length of the received network information. The voltage generation module is connected to the signal receiving module and outputs a voltage of corresponding amplitude based on the duration of the low-level signal from the signal receiving module, transmitting this voltage to the decoding module. The decoding module receives the voltage from the voltage generation module and generates a signal based on the magnitude of this voltage to start the power supply and provide power to the corresponding load. The load driving module receives the signal from the decoding module and starts or disconnects the load power supply based on this signal.

[0026] In the technical solution of this invention, the voltage generation module includes a PNP transistor Q3 used as a switching transistor. The emitter of transistor Q3 is connected to the power supply, the collector of transistor Q3 is grounded through resistor R3 and capacitor C1, and the base of transistor Q3 is connected to the output terminal of the signal receiving module. When the signal receiving module receives network information sent by the master device, it sends a low-level signal of a certain duration to transistor Q3 in the voltage generation module according to the wake-up data contained in the network information. After receiving the low-level signal, the base of transistor Q3 turns on, and the power supply charges capacitor C1 through transistor Q3. The charging time of capacitor C1 through transistor Q3 is determined by the conduction time of the transistor. The longer the low-level signal from the signal receiving module to the base of the transistor, the longer the conduction time of the transistor, and the greater the charging voltage of capacitor C1.

[0027] The decoding module includes three dual-limit voltage comparators D1, D2, and D3 arranged in parallel. The connection point of capacitor C1 and resistor R3 is connected to the input terminals of the three dual-limit voltage comparators D1, D2, and D3 respectively, meaning that the voltage of capacitor C1 is used as the input of the three dual-limit voltage comparators D1, D2, and D3. The output terminals of dual-limit voltage comparators D1, D2, and D3 are grounded through resistors R10, R11, and R12 respectively. The threshold values ​​of the three dual-limit voltage comparators D1, D2, and D3 are set to greater than 2.5V, 1V-2.5V, and 0-1V respectively. The three dual-limit voltage comparators can then conduct according to the threshold range in which the voltage of capacitor C1 falls. For example, when the voltage across capacitor C1, i.e., the voltage input to the three dual-limit voltage comparators D1, D2, and D3, is greater than 2.5V, comparator D1 conducts. Simultaneously, the signal from comparator D1 is connected to the D flip-flop U1, which briefly records the information to prevent data loss. When the voltage across capacitor C1 is within other threshold ranges, the operating principle remains as described above.

[0028] The outputs of dual-limit voltage comparators D1, D2, and D3 are connected to the decoder inputs via D flip-flops U1, U3, and U5, respectively. The decoder outputs are connected to the respective load power supplies. The outputs of D flip-flops U1, U3, and U5 are grounded via resistors R9, R8, and R7, respectively. The input of the series D flip-flop counter is connected to the junction of capacitor C1 and resistor R3, and its output is connected to the enable pin of the decoder (a 74HC138 decoder). Because the input of the series D flip-flop counter is connected to capacitor C1, each time the signal receiving module receives network information from the master device, the value of capacitor C1 changes, thus changing the count value of the series D flip-flop counter. After the series D flip-flop counter counts three times, it outputs a low-level signal to the decoder's enable pin and simultaneously resets the series D flip-flop counter to zero, awaiting the next network information transmission from the master device. After receiving a low-level enable signal at the enable terminal of the decoder, the signal already at the input terminal of the decoder will be converted by the decoder to generate corresponding outputs to the connected load drive modules.

[0029] The load drive module includes PNP transistors Q1 and Q2, an NPN transistor Q4, and an NOT gate U4. The input of NOT gate U4 is connected to one of the decoder's outputs, and its output is connected to the input of a D flip-flop U2. The output of the D flip-flop U2 is connected to the base of transistor Q1. A resistor R1 connects the emitter and base of transistor Q2. The base of transistor Q2 and the collector of transistor Q1 are grounded through resistor R14. The collector of transistor Q1 is connected to the base of transistor Q2, and its collector is grounded sequentially through resistors R2 and R5. The collector of transistor Q4 is connected to the collector of transistor Q1, and its emitter is grounded through resistor R6. The output of NOT gate U4 is connected to the base of transistor Q4 sequentially through a forward-conducting diode D3 and resistor R4. The connection point of diode D3 and resistor R4 is connected to the connection point of resistors R2 and R5, and the collector of transistor Q2 is grounded through the load. When the first output Y0 of decoder 74HC138 is low, it generates a high level through NOT gate U4 to supply power to the back-end circuit, thus enabling the back-end circuit to supply power to the load.

[0030] The present invention also provides a low-power power-on method for wireless control, comprising the following steps:

[0031] The first step is for the signal reading module to listen to the network information sent by the master device to wake up the low-power power supply, and obtain the duration of the signal from the network information.

[0032] The second step is that the signal reading module sends a low level to the voltage generation module. The duration of this low level is proportional to the duration of the signal. The PNP transistor Q3 in the voltage generation module is turned on, charging the capacitor C1 and transmitting the voltage of the capacitor C1 to the input terminals of the three dual-limit voltage comparators D1, D2 and D3.

[0033] The third step is to use the three dual-limit voltage comparators D1, D2 and D3 in the decoding module to turn on the corresponding D flip-flops according to the voltage values ​​output by the three dual-limit voltage comparators D1, D2 and D3, and increment the counter of the turned-on D flip-flops by 1.

[0034] Fourth step: When the series D flip-flop counter counts to 3, the series D flip-flop counter outputs a low level to the EN pin of the 74HC138 decoder, and at the same time the series D flip-flop counter returns to zero.

[0035] Fifth, the low level is flipped to a high level by a NOT gate. An odd number of times a pin of the 74HC138 decoder is turned on can supply power to the load of the self-locking circuit, thereby realizing low-power power-on without MCU wireless control. An even number of times the pin of the 74HC138 decoder is turned on again can realize the shutdown function.

[0036] Furthermore, the method for turning on the corresponding D flip-flops with the voltage values ​​output by the three dual-limit voltage comparators D1, D2 and D3 is as follows: the threshold of dual-limit voltage comparator D1 is set to be greater than 2.5V, the threshold of dual-limit voltage comparator D2 is set to 1V-2.5V, and the threshold of dual-limit voltage comparator D3 is set to 0V-1V.

[0037] When the voltage input to the three dual-limit voltage comparators is greater than 2.5V, D flip-flop U1 is turned on; when the voltage input to the three dual-limit voltage comparators is between 1V and 2.5V, D flip-flop U3 is turned on; when the voltage input to the three dual-limit voltage comparators is between 0V and 1V, D flip-flop U5 is turned on.

Claims

1. A low-power power-on circuit with wireless control, characterized in that: It includes a signal receiving module, a voltage generation module, a decoding module, and a load driving module; The signal receiving module is responsible for receiving network information sent by the master device. After receiving the network information, it outputs a low level for different durations according to the length of the received network information. The voltage generation module is connected to the signal receiving module. It outputs a corresponding voltage based on the duration of the low level output by the signal receiving module and transmits the voltage to the decoding module. The decoding module is responsible for receiving the voltage from the voltage generation module and generating a signal based on the magnitude of the voltage to start the power supply to provide power to the corresponding load. The load drive module is responsible for receiving signals from the decoding module and starting or disconnecting the load power supply according to the signals. The voltage generation module includes a PNP transistor Q3. The emitter of the transistor Q3 is connected to the power supply, the collector of the transistor Q3 is grounded through a resistor R3 and a capacitor C1 in sequence, and the base of the transistor Q3 is connected to the output terminal of the signal receiving module. The decoding module includes dual-limit voltage comparators D1, D2, and D3. The connection point of capacitor C1 and resistor R3 is connected to the input terminals of the three dual-limit voltage comparators D1, D2, and D3. The threshold values ​​of the dual-limit voltage comparators D1, D2, and D3 are set to be greater than 2.5V, 1V-2.5V, and 0-1V, respectively. The outputs of the dual-limit voltage comparators D1, D2, and D3 are connected to the input of the decoder via D flip-flops U1, U3, and U5, respectively. Each output of the decoder is connected to a load power supply. The input of the series D flip-flop counter is connected to the connection point of capacitors C1 and R3, and its output is connected to the enable terminal of the decoder. The decoder is a 74HC138 decoder.

2. The low-power power-on circuit for wireless control as described in claim 1, characterized in that: The load drive module includes PNP transistors Q1 and Q2, NPN transistor Q4, and NOT gate U4; The input terminal of the NOT gate U4 is connected to the output terminal of the decoder, the output terminal of the NOT gate U4 is connected to the input terminal of the D flip-flop U2, and the output terminal of the D flip-flop U2 is connected to the base of the transistor Q1. A resistor R1 is connected between the emitter and base of transistor Q2. The base of transistor Q2 is grounded through resistor R14. The collector of transistor Q1 is connected to the base of transistor Q2. The collector of transistor Q2 is grounded through resistors R2 and R5 in sequence. The collector of transistor Q4 is connected to the collector of transistor Q1, the emitter of transistor Q4 is grounded through resistor R6, and the output of NOT gate U4 is connected to the base of transistor Q4 in sequence through forward-conducting diode D3 and resistor R4. The connection point of diode D3 and resistor R4 is connected to the connection point of resistor R2 and resistor R5; The collector of the transistor Q2 is grounded through the load.

3. The low-power power-on circuit for wireless control as described in claim 2, characterized in that: The output terminals of the dual-limit voltage comparators D1, D2 and D3 are grounded through resistors R10, R11 and R12 respectively, and the output terminals of the D flip-flops U1, U3 and U5 are grounded through resistors R9, R8 and R7 respectively.

4. A low-power power-on method with wireless control, characterized in that, Includes the following steps: The first step is for the signal reading module to listen to the network information sent by the master device to wake up the low-power power supply, and obtain the duration of the signal from the network information. The second step is that the signal reading module sends a low level to the voltage generation module. The duration of this low level is proportional to the duration of the signal. The PNP transistor Q3 in the voltage generation module is turned on, charging the capacitor C1 and transmitting the voltage of the capacitor C1 to the input terminals of the three dual-limit voltage comparators D1, D2 and D3. The third step is to use the three dual-limit voltage comparators D1, D2 and D3 in the decoding module to turn on the corresponding D flip-flops according to the voltage values ​​output by the three dual-limit voltage comparators D1, D2 and D3, and increment the counter of the turned-on D flip-flops by 1. Fourth step: When the series D flip-flop counter counts to 3, the series D flip-flop counter outputs a low level to the EN pin of the 74HC138 decoder, and at the same time the series D flip-flop counter returns to zero. Fifth step: The low level is flipped to a high level through the NOT gate. An odd number of times a pin of the 74HC138 decoder is turned on can supply power to the load of the self-locking circuit, thereby realizing low-power power-on without MCU wireless control. An even number of times the pin of the 74HC138 decoder is turned on again can realize the shutdown function.

5. The low-power power-on method for wireless control as described in claim 4, characterized in that, The method for turning on the corresponding D flip-flops by the voltage values ​​output by the three dual-limit voltage comparators D1, D2 and D3 is as follows: the threshold of dual-limit voltage comparator D1 is set to be greater than 2.5V, the threshold of dual-limit voltage comparator D2 is set to 1V-2.5V, and the threshold of dual-limit voltage comparator D3 is set to 0V-1V. When the voltage input to the three dual-limit voltage comparators is greater than 2.5V, the D flip-flop U1 is turned on; When the voltage input to the three dual-limit voltage comparators is between 1V and 2.5V, the D flip-flop U3 is turned on; when the voltage input to the three dual-limit voltage comparators is between 0V and 1V, the D flip-flop U5 is turned on.

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