Amplifier circuit

Abstract

The present invention provides an amplifier circuit, comprising: an output stage, comprising at least a first P-type transistor and a first N-type transistor, the first P-type transistor being connected in series with the first N-type transistor; a first current source, configured to provide a first input current; a second current source; a third current source, configured to provide a second input current; a fourth current source; and a voltage clamping circuit, receiving a first bias voltage and a second bias voltage and having a first end and a second end; wherein, when the second input current is a positive current and the first input current is a negative current or zero current, the first end provides a first clamping voltage greater than the first bias voltage to the gate of the first P-type transistor, and when the first input current is a positive current and the second input current is a negative current or zero current, the second end provides a second clamping voltage less than the second bias voltage to the gate of the first N-type transistor.

Description

Technical Field

[0001] The present invention relates to an amplifier circuit, and more particularly to an amplifier circuit which uses a voltage clamp circuit before an amplifier output stage to achieve high-speed and wide voltage output. Background Art

[0002] With the increasing adoption of low-voltage circuits, the demand for high-speed, wide-voltage circuits is becoming increasingly common. For example, the common class AB amplifier, with its advantages of high speed, full voltage swing, and strong drive capability, is well-suited for use as an output stage. However, in typical wide-voltage circuit applications, high-speed operation becomes quite challenging due to parasitic capacitance and slew rate limitations.

[0003] In conventional amplifier circuits, the gate voltage operating range of the P-type transistor and the N-type transistor of the output stage of an AB-type amplifier is between the ground voltage GND and the system voltage AVDD (including both endpoints). Therefore, it takes a long time for the gate voltages of the P-type transistor and the N-type transistor of the AB-type amplifier to reach the upper and lower limits of the voltage operating range, resulting in an inability to meet high-speed operation requirements. Summary of the Invention

[0004] According to the purpose of the present invention, an embodiment of the present invention provides an amplifier circuit, comprising: an output stage, comprising at least a first P-type transistor and a first N-type transistor, the first P-type transistor and the first N-type transistor being connected in series; a first current source, configured to provide a first input current; a second current source, configured to provide a first bias current; a third current source, configured to provide a second input current; a fourth current source, configured to provide a second bias current; and a voltage clamp circuit, configured to receive a first bias voltage and a second bias voltage less than the first bias voltage, and having a first end and a second end, the first end being electrically connected to the first current source, the second current source, and a gate of the first P-type transistor, and the second end being electrically connected to the third current source, the fourth current source, and the gate of the first N-type transistor. When the second input current is a positive current and the first input current is a negative current or zero current, the first end provides a first clamp voltage greater than the first bias voltage to the gate of the first P-type transistor, and when the first input current is a positive current and the second input current is a negative current or zero current, the second end provides a second clamp voltage less than the second bias voltage to the gate of the first N-type transistor. In summary, the amplifier circuit according to the embodiment of the present invention can achieve high-speed and broadband operation.

[0005] To further understand the technology, means and effects of the present invention, reference may be made to the following detailed description and accompanying drawings, which may provide a thorough and specific understanding of the purposes, features and concepts of the present invention. However, the following detailed description and accompanying drawings are intended only to provide a reference and illustration of the implementation of the present invention and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are provided to enable those skilled in the art to further understand the present invention and are incorporated into and constitute a part of the specification of the present invention. The accompanying drawings illustrate exemplary embodiments of the present invention and, together with the description of the present invention, are used to explain the principles of the present invention.

[0007] Figure 1 is a circuit diagram of an amplifier circuit according to an embodiment of the present invention.

[0008] Figure 2 is a circuit diagram of an amplifier circuit according to another embodiment of the present invention.

[0009] Figure 3A FIG. 4 is a circuit diagram of a first bias generator of an amplifier circuit according to an embodiment of the present invention.

[0010] Figure 3B FIG. 4 is a circuit diagram of a second bias generator of an amplifier circuit according to an embodiment of the present invention.

[0011] Figure Number:

[0012] 1 amplifier circuit;

[0013] 11 a first current source;

[0014] 12 second current source;

[0015] 13 a third current source;

[0016] 14 fourth current source;

[0017] 15 voltage clamping circuit;

[0018] 16 output stages;

[0019] MP1 P-type shielded transistor;

[0020] MN1 N-type shielded transistor;

[0021] MP2 P-type transistor;

[0022] MN2 N-type transistor;

[0023] GND ground voltage;

[0024] AVDD system voltage;

[0025] VBIASP first bias;

[0026] VBIASN second bias voltage;

[0027] Iin1 first input current;

[0028] Iin2 second input current;

[0029] VOUT output voltage;

[0030] I1 current;

[0031] Vgs_MP1, Vgs_MN1 gate-source voltage. DETAILED DESCRIPTION

[0032] Reference will now be made in detail to exemplary embodiments of the present invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and the description to refer to the same or similar parts. The exemplary embodiments are merely one way to implement the design concepts of the present invention, and the following examples are not intended to limit the present invention.

[0033] An embodiment of the present invention provides an amplifier circuit that primarily uses a voltage clamp circuit to limit the voltage operating range of the gates of the P-type transistor and the N-type transistor of an AB-type amplifier in an output stage. The voltage operating range of the gate of the P-type transistor of the AB-type amplifier is set to a range between a first clamping voltage and a system voltage AVDD (including both endpoints of the first clamping voltage and the system voltage AVDD), and the voltage operating range of the gate of the P-type transistor of the AB-type amplifier is set to a range between a ground voltage GND and a second clamping voltage (including both endpoints of the ground voltage GND and the second clamping voltage). The first clamping voltage is greater than a first bias voltage VBIASP, the second clamping voltage is less than a second bias voltage VBIASN, the first bias voltage VBIASP is greater than the second bias voltage VBIASN, and both the first bias voltage VBIASP and the second bias voltage VBIASN are greater than the ground voltage GND and less than the system voltage AVDD. For example, the first clamping voltage is the first bias voltage VBIASP plus the gate-source voltage Vgs_MP1 of the P-type shielding transistor, and the second clamping voltage is the second bias voltage VBIASN minus the gate-source voltage Vgs_MN1 of the N-type shielding transistor. In this way, the P-type transistor and the N-type transistor of the AB-type amplifier can reach the upper and lower limits of the voltage operating range (for example, upper and lower limits defined by the user) more quickly, thereby improving the operating speed and achieving broadband operation. In addition, the P-type shielding transistor and the N-type shielding transistor can be any type of P-type transistor and N-type transistor. The word "shielding" only describes their function of pulling the first bias voltage high and pulling the second bias voltage low, thereby achieving an effect similar to shielding the first bias and the second bias.

[0034] Please refer to Figure 1 , Figure 1is a circuit diagram of an amplifier circuit according to an embodiment of the present invention. Amplifier circuit 1 includes a first current source 11, a second current source 12, a third current source 13, a fourth current source 14, a voltage clamp circuit 15, and an output stage 16. Output stage 16 includes at least a P-type transistor MP2 and an N-type transistor MN2. The source of P-type transistor MP2 is electrically connected to system voltage AVDD, the drain of P-type transistor MP2 and the drain of N-type transistor MN2 are electrically connected to each other, the source of N-type transistor MN2 is electrically connected to ground voltage GND, and the gate of P-type transistor MP2 and the gate of N-type transistor MN2 are electrically connected to a first clamping voltage and a second clamping voltage provided by a first terminal and a second terminal of voltage clamp circuit 15, respectively. A first terminal of voltage clamp circuit 15 is electrically connected to first current source 11 and second current source 12, and a second terminal of voltage clamp circuit 15 is electrically connected to third current source 13 and fourth current source 14.

[0035] The second current source 12 and the fourth current source 14 are respectively used to provide a first bias current and a second bias current to the first terminal and the second terminal of the voltage clamp circuit 15, and the first current source 11 and the third current source 13 are respectively used to provide a first input current Iin1 and a second input current Iin2 to the first terminal and the second terminal of the voltage clamp circuit 15. The first input current Iin1 and the second input current Iin2 are opposite currents to each other; alternatively, one of the first input current Iin1 and the second input current Iin2 is a forward current, and the other of the first input current Iin1 and the second input current Iin2 is zero current.

[0036] When the first input current Iin1 is a forward current, the second input current Iin2 is a reverse current (or zero current) and is less than the second bias current, and the current I1 of the voltage clamp circuit 15 is greater than zero, the gate of the P-type transistor MP2 approaches the system voltage AVDD, the gate voltage of the N-type transistor MN2 is a second clamping voltage (e.g., the second bias voltage VBIASN minus the gate-source voltage Vgs_MN1 of the N-type shield transistor MN1) that is less than the second bias voltage VBIASN, and the output voltage VOUT of the output stage 16 is the ground voltage GND.

[0037] When the first input current Iin1 is a reverse current (or zero current) and is less than the first bias current, the second input current Iin2 is a forward current, and the current I1 of the voltage clamp circuit 15 is greater than zero, the gate of the N-type transistor MN2 is close to the ground voltage GND, the gate voltage of the P-type transistor MP2 is a first clamping voltage greater than the first bias voltage VBIASP (for example, the first bias voltage VBIASP plus the gate-source voltage Vgs_MP1 of the P-type shield transistor MP1), and the output voltage VOUT of the output stage 16 is the system voltage AVDD.

[0038] P-type transistor MP2 is electrically connected in series with N-type transistor MN2 to form an AB-type amplifier. By reducing the operating voltage range of the gates of P-type transistor MP2 and N-type transistor MN2, the gate voltages of the P-type transistor MP2 and N-type transistor MN2 configured as the AB-type amplifier can more quickly reach the upper and lower limits of the default voltage operating range after transition. In this way, the AB-type amplifier of output stage 16 can operate at high speed and wide bandwidth. Although the present invention sacrifices the quiescent current of the gates of P-type transistor MP2 and N-type transistor MN2 in order to maintain the gate voltages of P-type transistor MP2 and N-type transistor MN2, the increased power consumption is not significant. In addition, in the embodiment of the present invention, amplifier circuit 1 is nonlinear and can therefore be used in high-speed, wideband, nonlinear amplification applications, such as as a comparator.

[0039] Furthermore, the voltage clamping circuit 15 can be implemented in a variety of ways, and it only needs to be able to provide a first clamping voltage and a second clamping voltage at its first end and second end respectively, and the present invention is not limited thereto. Figure 1 In the embodiment, the voltage clamp circuit 15 primarily includes a P-type shield transistor MP1 and an N-type shield transistor MN1. The gates of the P-type shield transistor MP1 and the N-type shield transistor MN1 are electrically connected to a first bias voltage VBIASP and a second bias voltage VBIASN, respectively. The drain of the P-type shield transistor MP1 and the drain of the N-type shield transistor MN1 are electrically connected to each other. The source of the P-type shield transistor MP1 is electrically connected to a first current source 11, a second current source 12, and the gate of the P-type transistor MP2. The source of the N-type shield transistor MN1 is electrically connected to a third current source 13, a fourth current source 14, and the gate of the N-type transistor MN2. Therefore, in this embodiment, the first clamp voltage is the first bias voltage VBIASP plus the gate-source voltage Vgs_MP1 of the P-type shield transistor MP1, and the second clamp voltage is the second bias voltage VBIASN minus the gate-source voltage Vgs_MN1 of the N-type shield transistor MN1. In another implementation, the voltage clamping circuit 15 includes a buck voltage regulator and a boost voltage regulator. The boost voltage regulator receives a first bias voltage at its input, and its output provides a first clamping voltage greater than the first bias voltage. The buck voltage regulator receives a second bias voltage at its input, and its output provides a second clamping voltage less than the second bias voltage. It should be noted that the aforementioned voltage clamping circuit 15 is only one implementation of the present invention, and other circuit combinations that achieve similar functions may also be used to implement the present invention.

[0040] Please refer to Figure 2 , Figure 2FIG. 1 is a circuit diagram of an amplifier circuit according to another embodiment of the present invention. Figure 2 middle, Figure 1 The details of the first current source 11, second current source 12, third current source 13, and fourth current source 14 are further disclosed. Furthermore, an inverter INV can be electrically connected to the output stage 16 to serve as a buffer for the output voltage VOUT. P-type transistors MP5-MP9 are configured as a second power supply 12 to provide a first bias current; N-type transistors MN5-MN9 are configured as a fourth power supply 14 to provide a second bias current; a reference current source CS2 and N-type transistors MN3 and MN4 are configured as a first current source 11 to provide a first input current Iin1, wherein the first current source 11 is electrically connected to the gate of the P-type transistor MP2 via a P-type transistor MP8; and a reference current source CS1 and P-type transistors MP3 and MP4 are configured as a third current source 13 to provide a second input current Iin2, wherein the second current source 12 is electrically connected to the gate of the N-type transistor MN2 via an N-type transistor MP8.

[0041] Specifically, reference current source CS1 is electrically connected to the sources of P-type transistors MP3 and MP4, the gates of which are electrically connected to input signals InP and InN, respectively, and the drains of which are electrically connected to the sources of N-type transistors MN7 and MN8, respectively. Reference current source CS2 is electrically connected to the sources of N-type transistors MN3 and MN4, the gates of which are electrically connected to input signals InP and InN, respectively, and the drains of which are electrically connected to the sources of P-type transistors MP7 and MP8, respectively.

[0042] The sources of P-type transistors MP5 and MP6 are electrically connected to system voltage AVDD. The gates of P-type transistors MP5 and MP6 are electrically connected to each other and to the drain of P-type transistor MP7. The drains of P-type transistors MP5 and MP6 are electrically connected to the sources of P-type transistors MP7 and MP8, respectively. The gates of P-type transistors MP7 and MP8 are electrically connected to each other, and the drains of P-type transistors MP7 and MP8 are electrically connected to the source of P-type transistor MP9 and the first terminal of voltage clamp circuit 15, respectively. The gate of P-type transistor MP9 receives bias voltage BP, and the drain of P-type transistor MP9 is electrically connected to the drain of N-type transistor MN7.

[0043] The sources of N-type transistors MN5 and MN6 are electrically connected to ground voltage GND. The gates of N-type transistors MN5 and MN6 are electrically connected to each other and to the drain of N-type transistor MN7. The drains of N-type transistors MN5 and MN6 are electrically connected to the sources of N-type transistors MN7 and MN8, respectively. The gates of N-type transistors MN7 and MN8 are electrically connected to each other, and the drains of N-type transistors MN7 and MN8 are electrically connected to the source of N-type transistor MN9 and the second terminal of voltage clamp circuit 15, respectively. The gate of N-type transistor MN9 receives bias voltage BN, and the drain of N-type transistor MN9 is electrically connected to the drain of P-type transistor MP7.

[0044] Please refer to Figure 3A , Figure 3A 1 is a circuit diagram of a first bias voltage generator for an amplifier circuit according to an embodiment of the present invention. Amplifier circuit 1 further includes a first bias voltage generator. A first bias voltage VBIASP and a bias voltage BN can be generated by the first bias generator. The first bias generator includes N-type transistors MN10 and MN11, a resistor R1, and a reference current source CS3. The source of N-type transistor MN10 is electrically connected to ground voltage GND, the gate of N-type transistor MN10 is electrically connected to the drain of N-type transistor MN10, and the drain of N-type transistor MN10 is electrically connected to the source of N-type transistor MN11. The gate of N-type transistor MN11 is electrically connected to the drain of N-type transistor MN11 and provides bias voltage BN. The drain of N-type transistor MN10 is electrically connected to one end of resistor R1, and the other end of resistor R1 is electrically connected to reference current source CS3 and provides first bias voltage VBIASP.

[0045] Please refer to Figure 3B , Figure 3B 1 is a circuit diagram of a second bias voltage generator for an amplifier circuit according to an embodiment of the present invention. Amplifier circuit 1 further includes a second bias voltage generator. Second bias voltage VBIASN and bias voltage BP can be generated by the second bias generator. The second bias generator includes P-type transistors MP10 and MP11, a resistor R2, and a reference current source CS4. The source of P-type transistor MP10 is electrically connected to system voltage AVDD, the gate of P-type transistor MP10 is electrically connected to the drain of P-type transistor MP10, and the drain of P-type transistor MP10 is electrically connected to the source of P-type transistor MP11. The gate of P-type transistor MP11 is electrically connected to the drain of P-type transistor MP11 and provides bias voltage BP. The drain of P-type transistor MP10 is electrically connected to one end of resistor R2, and the other end of resistor R2 is electrically connected to reference current source CS4 and provides second bias voltage VBIASN.

[0046] In summary, the present invention provides a voltage clamp circuit to limit the operating voltage range of the gates of the P-type transistor and the N-type transistor of the output stage of the AB-type amplifier. This allows the gates of the P-type transistor and the N-type transistor to be maintained at a first clamping voltage and a second clamping voltage, respectively, during transitions. This increases the speed at which the gate voltages of the P-type transistor and the N-type transistor of the AB-type amplifier reach the upper and lower limits of the default voltage operating range. Consequently, the amplifier circuit of the present invention is capable of achieving high-speed and broadband operation.

[0047] It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to those skilled in the art and are to be included within the spirit and purview of this application and the scope of the appended claims.

Claims

1. An amplifier circuit, characterized in that: The amplifier circuit comprises: an output stage comprising a first P-type transistor and a first N-type transistor, wherein the first P-type transistor and the first N-type transistor are connected in series; A first current source, configured to provide a first input current; a second current source, configured to provide a first bias current; a third current source, configured to provide a second input current; a fourth current source, configured to provide a second bias current; and a voltage clamp circuit receiving a first bias voltage and a second bias voltage less than the first bias voltage, and having a first end and a second end, wherein the first end is electrically connected to the first current source, the second current source, and the gate of the first P-type transistor, and the second end is electrically connected to the third current source, the fourth current source, and the gate of the first N-type transistor; When the second input current is a positive current and the first input current is a negative current or zero current, the first end provides a first clamping voltage greater than the first bias voltage to the gate of the first P-type transistor; when the first input current is a positive current and the second input current is a negative current or zero current, the second end provides a second clamping voltage less than the second bias voltage to the gate of the first N-type transistor.

2. The amplifier circuit according to claim 1, wherein The voltage clamping circuit includes: P-type shielded transistor and N-type shielded transistor; The gate of the P-type shielding transistor and the gate of the N-type shielding transistor are electrically connected to the first bias and the second bias respectively, the drain of the P-type shielding transistor and the drain of the N-type shielding transistor are electrically connected to each other, the source of the P-type shielding transistor is electrically connected to the first current source, the second current source and the gate of the P-type transistor, and the source of the N-type shielding transistor is electrically connected to the third current source, the fourth current source and the gate of the N-type transistor.

3. The amplifier circuit according to claim 2, wherein: The first clamping voltage is the first bias voltage plus the gate-source voltage of the P-type shielding transistor.

4. The amplifier circuit according to claim 2, wherein: The second clamping voltage is the second bias voltage minus the gate-source voltage of the N-type shielding transistor.

5. The amplifier circuit according to claim 1, wherein The amplifier circuit further includes: The first bias voltage generator is configured to generate the first bias voltage.

6. The amplifier circuit according to claim 1, wherein: The amplifier circuit further includes: The second bias voltage generator is used to generate the second bias voltage.

7. The amplifier circuit according to claim 1, wherein: The first current source is composed of a first reference current source and a plurality of second N-type transistors, wherein the gates of the plurality of second N-type transistors receive a first input signal and a second input signal, the sources of the plurality of second N-type transistors are electrically connected to the first reference current source, and the drains of the plurality of second N-type transistors are electrically connected to the gates of the first P-type transistors.

8. The amplifier circuit according to claim 1, wherein The third current source is composed of a second reference current source and multiple second P-type transistors, wherein the gates of the multiple second P-type transistors receive the first input signal and the second input signal, the sources of the multiple second P-type transistors are electrically connected to the second reference current source, and the drains of the multiple second P-type transistors are electrically connected to the gates of the first N-type transistors.

9. The amplifier circuit according to claim 7, wherein: The second current source is composed of a plurality of electrically connected third P-type transistors, and the first current source is electrically connected to the gate of the first P-type transistor through one of the third P-type transistors.

10. The amplifier circuit according to claim 8, wherein The fourth current source is composed of a plurality of electrically connected third N-type transistors, and the second current source is electrically connected to the gate of the first N-type transistor through one of the third N-type transistors.

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