Wafer placement stage

Abstract

The present invention provides a wafer stage, and the problem thereof is to prevent breakage caused by thermal stress on the basis of a wafer stage having a refrigerant flow path. The wafer stage (10) is a wafer stage having a refrigerant flow path through which refrigerant flows. The wafer stage (10) includes: an upper substrate (12) having a ceramic substrate (20) with an electrode (26) built therein, and having a wafer placement surface (22a) on the upper surface of the ceramic substrate (20); a lower substrate (80) having a flow path groove (88) on its upper surface that forms the side wall and bottom of the refrigerant flow path; and a sealing member (16) disposed between the upper substrate (12) and the lower substrate (80) to seal between the refrigerant flow path (18) and the outside.

Description

Technical Field

[0001] The present invention relates to a wafer mounting table. Background Art

[0002] Conventionally, a wafer mounting table is known which is obtained by bonding a ceramic substrate such as alumina implanted with an electrostatic electrode and a cooling substrate containing a metal such as aluminum via a resin layer (for example, refer to Patent Document 1). According to this wafer mounting table, the influence of the difference in thermal expansion between the ceramic substrate and the cooling substrate can be alleviated by the resin layer. A wafer mounting table is also known which is obtained by bonding a ceramic substrate and a cooling substrate having a refrigerant flow path inside thereof using a metal bonding layer instead of the resin layer (for example, Patent Documents 2 and 3). Since the metal bonding layer has a higher thermal conductivity than the resin layer, it is possible to achieve the heat dissipation ability required when processing a wafer using high-power plasma. On the other hand, since the metal bonding layer has a larger Young's modulus and lower stress relaxation property than the resin layer, it can hardly alleviate the influence of the difference in thermal expansion between the ceramic substrate and the cooling substrate. Therefore, in Patent Documents 2 and 3, a metal matrix composite (MMC) having a smaller difference in thermal expansion coefficient from the ceramic substrate is used as the material of the cooling substrate.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Laid-Open No. 4-287344

[0006] Patent Document 2: Japanese Patent No. 5666748

[0007] Patent Document 3: Japanese Patent No. 5666749 Summary of the Invention

[0008] However, in the case of using a cooling substrate having a refrigerant flow path inside, due to a large amount of heat input from high-power plasma, the portion above the refrigerant flow path expands thermally, and the wafer mounting table may be damaged starting from the periphery of the boundary between the top surface and the side wall surface of the refrigerant flow path due to the difference in thermal expansion or the like.

[0009] The present invention has been completed to solve the above problems, and its main object is to prevent breakage caused by thermal stress in a wafer mounting table having a refrigerant flow path.

[0010] [1] The wafer mounting table of the present invention has a refrigerant flow path through which a refrigerant flows,

[0011] The wafer mounting table is characterized by comprising:

[0012] An upper substrate, which includes a ceramic substrate with electrodes built therein and has a wafer placement surface on the upper surface of the ceramic substrate;

[0013] A lower substrate, on the upper surface of which flow channels are provided to form side walls and a bottom of the refrigerant flow path; and

[0014] A sealing member, which is disposed between the upper substrate and the lower substrate to seal between the refrigerant flow path and the outside.

[0015] In this wafer placement stage, the upper substrate forming the top surface of the refrigerant flow path and the lower substrate forming the side wall surface of the refrigerant flow path are not integrated, and a sealing member is disposed between them. Therefore, even if a thermal expansion difference occurs between the top surface and the side wall surface of the refrigerant flow path, the sealing member will absorb the influence of this thermal expansion difference. Therefore, based on the wafer placement stage with a refrigerant flow path, it is possible to prevent the wafer placement stage from being damaged due to thermal stress.

[0016] It should be noted that in this specification, the present invention is sometimes described using up and down, left and right, front and back, etc. However, up and down, left and right, front and back are merely relative positional relationships. Therefore, when the orientation of the wafer placement stage is changed, up may become left and right, and left and right may become up and down, and this situation is also included in the technical scope of the present invention.

[0017] [2] The above-mentioned wafer placement stage (the wafer placement stage described in the above [1]) may be: the upper substrate includes: the ceramic substrate; a top substrate, which is joined to the lower surface of the ceramic substrate and forms the top of the refrigerant flow path; and a metal bonding layer, which bonds the ceramic substrate and the top substrate.

[0018] [3] The above-mentioned wafer placement stage (the wafer placement stage described in the above [2]) may be: the absolute value of the linear thermal expansion coefficient difference between 40 °C and 400 °C between the top substrate and the ceramic substrate is 1.5×10 -6 / K or less. Accordingly, since the thermal expansion difference between the ceramic substrate and the top substrate is small, warping and breakage of the upper substrate caused by thermal stress can be suppressed. It should be noted that in this specification, the linear thermal expansion coefficient obtained by measuring the lengths at 40 °C and 400 °C is referred to as the linear thermal expansion coefficient of 40 - 400 °C.

[0019] [4] The above-mentioned wafer placement stage (the wafer placement stage described in the above [2] or [3]) may be: the top substrate is made of a composite material of metal and ceramic. Since the absolute value of the linear thermal expansion coefficient difference between the composite material of metal and ceramic and the ceramic substrate is small, thermal stress is not easily generated in the upper substrate. In addition, since the toughness is higher than that of ceramic materials, even if thermal stress is generated, it is not easily broken.

[0020] [5] The above-mentioned wafer stage (the wafer stage described in [2] or [3] above) may be such that the top substrate is made of a ceramic material having the same main component as the ceramic substrate. Since the absolute value of the difference in linear thermal expansion coefficient between ceramic materials with the same main component is small, the upper substrate is less likely to generate thermal stress. It should be noted that in this specification, the main component refers to a component that occupies 50% by mass or more of the total components included, preferably 70% by mass or more, and more preferably 90% by mass or more.

[0021] [6] The above-mentioned wafer stage (the wafer stage described in [1] above) may be such that the upper substrate is a single layer of the ceramic substrate.

[0022] [7] The above-mentioned wafer stage (the wafer stage described in any one of [1] to [6] above) may be such that the lower substrate is made of a material with easy machinability. If it is a material with easy machinability, the formation of the flow path groove is easy, and thus the processing cost can be reduced.

[0023] [8] The above-mentioned wafer stage (the wafer stage described in any one of [1] to [7] above) may be such that as the sealing member, an outer sealing member is provided in multiple layers so as to surround the outermost edge of the flow path groove. Accordingly, the outer sealing member on the flow path groove side is protected from process gases and plasmas by the outermost peripheral outer sealing member, and thus the corrosion resistance can be improved.

[0024] [9] The above-mentioned wafer stage (the wafer stage described in any one of [1] to [8] above) may be such that a heat sink is disposed between the lower surface of the upper substrate and the upper surface of the lower substrate. Accordingly, heat from the upper substrate is easily conducted downward to the lower substrate quickly through the heat sink. As a result, the efficiency of cooling the wafer is improved.

[0025]

[10] The above-mentioned wafer stage (the wafer stage described in [9] above) may be such that the thermal resistance of the heat sink is 0.5 K·cm 2 / W or less. Accordingly, heat from the upper substrate is conducted downward to the lower substrate more quickly, and thus the efficiency of cooling the wafer is further improved.

[0026]

[11] The above-mentioned wafer stage (the wafer stage described in [9] or

[10] above) may be such that the Young's modulus of the heat sink is 100 MPa or less. Accordingly, the heat sink is firmly bonded to the upper substrate and the lower substrate, and thus heat from the upper substrate is conducted downward to the lower substrate more quickly, and the efficiency of cooling the wafer is further improved.

[0027]

[12] The above-mentioned wafer placement stage (the wafer placement stage described in any one of the above [9] to

[11] ) may be as follows: The heat sink includes: a main body portion disposed on a portion of the upper surface of the lower substrate where the flow path grooves are not provided; and a bridging portion bridging over the flow path grooves. The main body portion quickly conducts the heat of the upper substrate to the lower substrate. The bridging portion maintains the sheet shape of the heat sink and improves the operability of the heat sink. Therefore, in the wafer placement stage having the main body portion and the bridging portion, the efficiency of cooling the wafer and the workability during the assembly of the wafer placement stage can be improved.

[0028]

[13] The above-mentioned wafer placement stage (the wafer placement stage described in any one of the above [1] to

[12] ) may be as follows: The upper substrate and the lower substrate are mechanically joined in a manner of squeezing the sealing member from above and below. Since the sealing member can be fully squeezed from above and below by mechanical joining, the sealing function of the sealing member can be fully exerted. In addition, by mechanical joining, the heat sink is firmly bonded to the upper substrate and the lower substrate, so the heat of the upper substrate is conducted to the lower substrate more quickly, and the efficiency of cooling the wafer is further improved.

[0029]

[14] The above-mentioned wafer placement stage (the wafer placement stage described in any one of the above [1] to

[13] ) may be as follows: The wafer placement stage includes: a through hole penetrating the lower substrate in the vertical direction; a screw hole provided at a position on the lower surface of the upper substrate opposite to the through hole; and a screw member inserted into the through hole from the lower surface of the lower substrate and screwed into the screw hole. In this wafer placement stage, the upper substrate and the lower substrate are mechanically joined by the screw member. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a longitudinal sectional view of the wafer placement stage 10 provided in the chamber 94.

[0031] Figure 2 It is a plan view of the wafer placement stage 10.

[0032] Figure 3 It is a plan view of the lower substrate 80.

[0033] Figure 4 It is a manufacturing process diagram of the wafer placement stage 10 (manufacturing process of the upper substrate 12).

[0034] Figure 5 It is a manufacturing process diagram of the wafer placement stage 10 (manufacturing process of the lower substrate 80).

[0035] Figure 6 It is a manufacturing process diagram of the wafer placement stage 10 (assembly process of the wafer placement stage 10).

[0036] Figure 7 It is a longitudinal sectional view of the wafer stage 210.

[0037] Figure 8 It is a longitudinal sectional view of the wafer stage 310.

[0038] Figure 9 It is an explanatory view showing an example in which the wafer stage 10 is fastened to the mounting plate 96 with bolts 76.

[0039] Figure 10 It is a longitudinal sectional view of the wafer stage 410 provided in the chamber 94.

[0040] Figure 11 It is a sectional view when observing the cross section obtained by cutting the wafer stage 410 in a horizontal plane including the heat sink 417 from above.

[0041] Figure 12 It shows Figure 11 a sectional view of an example in which the heat sink 417 is changed in the sectional view.

[0042] Figure 13 It is a longitudinal sectional view of the wafer stage 510 provided in the chamber 94.

[0043] Symbol Explanation

[0044] 10 Wafer stage, 12 Upper substrate, 16 Sealing member, 16a Outer sealing member, 16b Inner sealing member, 18 Refrigerant flow path, 20 Ceramic substrate, 22 Central portion, 22a Wafer placement surface, 24 Outer peripheral portion, 24a Focus ring placement surface, 26 Wafer adsorption electrode, 27 Hole, 30 Top substrate, 32 Inner peripheral portion, 34 Outer peripheral portion, 40 Metal bonding layer, 42 Insulating film, 52 DC power supply for wafer adsorption, 53 Low-pass filter, 54 Power supply terminal, 55 Insulating tube, 62 RF power supply, 63 High-pass filter, 64 Power supply terminal, 65 Insulating tube, 70 Clamping member, 70a Inner peripheral step surface, 72 Bolt, 76 Bolt, 78 Focus ring, 80 Lower substrate, 88 Flow path groove, 88a Inlet, 88b Outlet, 89 Sealing groove, 89a Outer groove, 89b Inner groove, 94 Chamber, 96 Setting plate, 98 Sprayer, 112 Bonded body, 120 Ceramic sintered body, 130 Circular plate member, 131 Through hole, 180 Machinable circular plate member, 181, 182 Through holes, 210 Wafer stage, 212 Upper substrate, 230 Top substrate, 310 Wafer stage, 312 Upper substrate, 320 Ceramic substrate, 325 Outermost peripheral portion, 328 RF electrode, 410 Wafer stage, 412 Upper substrate, 417 Heat sink, 418 Heat sink, 418a Main body portion, 418b Bridging portion, 430 Top substrate, 437 Screw hole, 472 Screw member, 477 Screw member, 477a Head portion, 477b Foot portion, 487 Through hole, 487a Large diameter portion, 487b Small diameter portion, 488 Screw hole, 510 Wafer stage. Detailed implementation manners

[0045] Hereinafter, with reference to the drawings, preferred implementation manners of the present invention will be described. Figure 1 It is a longitudinal sectional view of the wafer stage 10 provided in the chamber 94 (a sectional view when cut along a plane including the central axis of the wafer stage 10), Figure 2 It is a plan view of the wafer stage 10, Figure 3 It is a plan view of the lower substrate 80. In this specification, "~" indicating a numerical range is used in the sense of including the values described before and after as the lower limit value and the upper limit value.

[0046] The wafer stage 10 is a component used when performing CVD, etching, etc. on a wafer W using plasma, and is fixed to a mounting plate 96 provided inside a chamber 94 for semiconductor processing. The wafer stage 10 includes: an upper substrate 12, a lower substrate 80, and a sealing member 16. The wafer stage 10 has a refrigerant flow path 18 inside through which refrigerant can circulate. The refrigerant flow path 18 is an area between the lower surface of the upper substrate 12 and the upper surface of the lower substrate 80, inside the outer sealing member 16a and outside the inner sealing member 16b. There is a gap between the lower surface of the upper substrate 12 and the upper surface of the lower substrate 80, and in the refrigerant flow path 18, the refrigerant can also flow through this gap.

[0047] The upper substrate 12 includes: a ceramic substrate 20; a top substrate 30 disposed below the ceramic substrate 20 and forming the top of the refrigerant flow path 18; and a metal bonding layer 40 that bonds the ceramic substrate 20 and the top substrate 30. Regarding the thickness of the upper substrate 12, considering strength, it is preferably 8 mm or more, 10 mm or more, and considering cooling efficiency, it is preferably 25 mm or less.

[0048] The ceramic substrate 20 has an outer peripheral portion 24 with an annular focus ring mounting surface 24a on the outer periphery of a central portion 22 having a circular wafer mounting surface 22a. Hereinafter, the focus ring is sometimes simply referred to as "FR". A wafer W is placed on the wafer mounting surface 22a, and a focus ring 78 is placed on the FR mounting surface 24a. The ceramic substrate 20 is formed of a ceramic material represented by alumina, aluminum nitride, etc. The FR mounting surface 24a is one level lower than the wafer mounting surface 22a.

[0049] The central portion 22 of the ceramic substrate 20 has a wafer adsorption electrode 26 built in on the side closer to the wafer mounting surface 22a. The wafer adsorption electrode 26 is formed of a material containing, for example, W, Mo, WC, MoC, etc. The wafer adsorption electrode 26 is a disk-shaped or mesh-shaped monopolar electrostatic electrode. The layer in the ceramic substrate 20 above the wafer adsorption electrode 26 functions as a dielectric layer. A wafer adsorption DC power supply 52 is connected to the wafer adsorption electrode 26 via a power supply terminal 54. The power supply terminal 54 is arranged to pass through an insulating tube 55 disposed in a through hole penetrating the lower substrate 80, the top substrate 30, and the metal bonding layer 40 in the vertical direction, and reach the wafer adsorption electrode 26 from the lower surface of the ceramic substrate 20. A low-pass filter (LPF) 53 is provided between the wafer adsorption DC power supply 52 and the wafer adsorption electrode 26.

[0050] The top substrate 30 is a circular plate member made of a composite material of metal and ceramic (hereinafter also referred to as a metal-ceramic composite material). Examples of the metal-ceramic composite material include: Metal-Matrix Composite (MMC), Ceramic-Matrix Composite (CMC), etc. The outer diameter of the top substrate 30 is larger than the outer diameter of the ceramic substrate 20, and it has: an inner peripheral portion 32 where the ceramic substrate 20 is disposed, and an outer peripheral portion 34 that extends outward from the outer periphery of the ceramic substrate 20. The upper substrate 12 and the lower substrate 80 are clamped together on the outer peripheral side (outer peripheral portion 34) of the top substrate 30 to the setting plate 96. The absolute value of the linear thermal expansion coefficient difference between 40 and 400 °C between the metal-ceramic composite material for the top substrate 30 and the ceramic material for the ceramic substrate 20 is preferably 1.5×10 -6 / K or less, more preferably 1.0×10 -6 / K or less, and further preferably 0.5×10 -6 / K or less. Specific examples of the above metal-ceramic composite material include: materials containing Si, SiC, and Ti, materials obtained by impregnating SiC porous bodies with Al and / or Si, etc. The material containing Si, SiC, and Ti is called SiSiCTi, the material obtained by impregnating SiC porous bodies with Al is called AlSiC, and the material obtained by impregnating SiC porous bodies with Si is called SiSiC. When the ceramic substrate 20 is an alumina substrate, as the metal-ceramic composite material for the top substrate 30, AlSiC, SiSiCTi, etc. are preferred. For the linear thermal expansion coefficient at 40 to 400 °C, alumina is 7.2×10 -6 / K, AlSiC (SiC 75%) is 7.8×10 -6 / K, and SiSiCTi is 7.3×10 -6 / K. When the ceramic substrate 20 is a aluminum nitride substrate, as the metal-ceramic composite material for the top substrate 30, AlSiC, SiSiC, etc. are preferred. For the linear thermal expansion coefficient at 40 to 400 °C, aluminum nitride is 4.6×10 -6 / K, and AlSiC (SiC 85%) is 5.6×10 -6 / K. The thermal conductivity of the material for the top substrate 30 is preferably, for example, 50 W / (m·K) or more, more preferably 70 W / (m·K) or more, and further preferably 80 W / (m·K) or more. The top substrate 30 also functions as a high-frequency (RF) electrode for plasma generation and is connected to the RF power supply 62 via the power supply terminal 64. The power supply terminal 64 is arranged to pass through an insulating tube 65 disposed in a through-hole penetrating the lower substrate 80 in the vertical direction and reach the lower surface of the top substrate 30. The power supply terminal 64 is provided in the chamber 94 and is urged upward by a spring (not shown). Therefore, the upper end of the power supply terminal 64 is in elastic contact with the lower surface of the top substrate 30. A high-pass filter (HPF) 63 is disposed between the top substrate 30 and the RF power supply 62. Regarding the thickness of the top substrate 30, if strength is considered, it is preferably 3 mm or more, 6 mm or more, and if cooling efficiency is considered, it is preferably 20 mm or less.

[0051] The metal bonding layer 40 bonds the lower surface of the ceramic substrate 20 and the upper surface of the top substrate 30. The metal bonding layer 40 can be, for example, a layer formed of solder or metal brazing material. The metal bonding layer 40 is formed by, for example, TCB (Thermalcompression bonding). TCB refers to a well-known method in which a metal bonding material is sandwiched between two components to be bonded and the two components are pressure-bonded at a temperature below the solidus temperature of the metal bonding material.

[0052] The side surface of the outer peripheral portion 24 of the ceramic substrate 20, the outer periphery of the metal bonding layer 40, and the upper surface and side surface of the top substrate 30 are covered with an insulating film 42. Examples of the insulating film 42 include sputtered films of alumina, yttrium oxide, etc.

[0053] The lower substrate 80 is a disc-shaped member made of a material with easy machinability. The outer diameter of the lower substrate 80 is the same as the outer diameter of the top substrate 30. As Figure 3As shown, flow path grooves 88 and seal grooves 89 are provided on the upper surface of the lower substrate 80. The flow path grooves 88 form the side walls and bottom of the refrigerant flow path 18, and are spirally provided from the inlet 88a to the outlet 88b over the entire area where the ceramic substrate 20 is arranged. The inlet 88a and the outlet 88b of the flow path grooves 88 penetrate the lower substrate 80 in the vertical direction and open on the bottom surface of the flow path grooves 88. The inlet 88a and the outlet 88b of the flow path grooves 88 are connected to a refrigerant cooling device (not shown). After the temperature of the refrigerant discharged from the outlet 88b is adjusted by the refrigerant cooling device, it returns to the inlet 88a again and is supplied into the flow path grooves 88 (refrigerant flow path 18). The refrigerant flowing in the refrigerant flow path 18 is preferably a liquid and preferably has electrical insulation. As the electrically insulating liquid, for example, fluorine-based inert liquids can be cited. The seal groove 89 is a groove for arranging the seal member 16. In the seal groove 89, the outer groove 89a is provided in a double layer so as to surround the outermost edge of the flow path groove 88, and the inner groove 89b is provided so as to surround the peripheries of the insulating tubes 55 and 65 respectively. The material for the lower substrate 80 that is easy to process is preferably a material that is easier to process than the top substrate 30 made of a metal-ceramic composite material. As an index of workability, for example, the machinability index given in JIS B 0170 (2020) can be adopted. As the material that is easy to process, a material with a machinability index of 40 or more is preferred, a material of 100 or more is more preferred, and a material of 140 or more is further preferred. As the material that is easy to process, for example, aluminum, aluminum alloy, stainless steel (SUS material), resin (heat-resistant resin), etc. can be cited. From the viewpoint of improving the efficiency of cooling the wafer W, the material for the lower substrate 80 is preferably a material with a high thermal conductivity. The thermal conductivity of the material for the lower substrate 80 is preferably, for example, 80 W / (m·K) or more, more preferably 100 W / (m·K) or more, and further preferably 150 W / (m·K) or more.

[0054] The sealing member 16 is a member that is disposed between the upper base material 12 and the lower base material 80 to seal between the refrigerant flow path 18 and the outside. The sealing member 16 is an elastically deformable annular member, and by being squeezed in the vertical direction, it seals between the refrigerant flow path 18 and the outside to prevent the refrigerant in the refrigerant flow path 18 from leaking to the outside. In the sealing member 16, the outer sealing member 16a is doubly provided so as to surround the outermost edge of the flow path groove 88, and the inner sealing member 16b is provided so as to surround the peripheries of the insulating tubes 55 and 65 respectively. The outer sealing member 16a prevents the refrigerant in the refrigerant flow path 18 from leaking out from the outer periphery of the wafer stage 10, and the inner sealing member 16b prevents the refrigerant in the refrigerant flow path 18 from leaking to the peripheries of the insulating tubes 55 and 65. As the sealing member 16, an O-ring, a gasket, etc. can be used. The sealing member 16 can be made of an insulating material or a conductive material. The sealing member 16 can be made of resin, rubber, or metal. The outer sealing member 16a is disposed in the outer groove 89a, and the inner sealing member 16b is disposed in the inner groove 89b for positioning.

[0055] For the above-mentioned wafer stage 10, in a state where the lower base material 80, the sealing member 16, and the upper base material 12 are sequentially overlapped from the lower side, a clamping member 70 is used to be mounted on a mounting plate 96 provided inside the chamber 94. Accordingly, the upper base material 12 and the lower base material 80 of the wafer stage 10 are mechanically joined by clamping, the sealing member 16 is squeezed in the vertical direction, and the refrigerant flow path 18 and the outside are sealed. The clamping member 70 is an annular member having a substantially inverted L-shaped cross section and has an inner peripheral step surface 70a. The wafer stage 10 and the mounting plate 96 are integrated by the clamping member 70. Specifically, with the inner peripheral step surface 70a of the clamping member 70 placed on the outer peripheral portion 34 of the upper base material 12 (the top base material 30) of the wafer stage 10, a bolt 72 is inserted from the upper surface of the clamping member 70 and screwed into a screw hole provided on the upper surface of the mounting plate 96, whereby the wafer stage 10 and the mounting plate 96 are integrated. The bolts 72 are mounted at a plurality of locations (for example, 8 locations, 12 locations) provided at equal intervals along the circumferential direction of the clamping member 70. The clamping member 70 and the bolts 72 can be made of an insulating material or a conductive material (such as metal). The clamping member 70 is preferably disposed with a clearance between the inner peripheral surface of the clamping member 70 and the outer peripheral surface of at least one of the upper base material 12 and the lower base material 80 so that relative movement in the horizontal direction can be achieved between the upper base material 12 and the lower base material 80.

[0056] Next, Figures 4 - 6 , a manufacturing example of the wafer stage 10 will be described. Figures 4 - 6 is a manufacturing process diagram of the wafer stage 10, Figure 4 showing the manufacturing process of the upper base material 12, Figure 5Represents the manufacturing process of the lower substrate 80. Figure 6 Represents the assembly process of the wafer stage 10.

[0057] For example, the upper substrate 12 is fabricated as follows. First, a ceramic powder compact is hot press sintered to produce a disk-shaped ceramic sintered body 120 that serves as the basis for the ceramic substrate 20( Figure 4 (A)). The ceramic sintered body 120 has a wafer adsorption electrode 26 incorporated therein. Next, a hole 27 is formed from the lower surface of the ceramic sintered body 120 to the wafer adsorption electrode 26( Figure 4 (B)), a power supply terminal 54 is inserted into the hole 27, and the power supply terminal 54 and the wafer adsorption electrode 26 are joined( Figure 4 (C)).

[0058] Meanwhile, a disk-shaped member 130 made of a metal-ceramic composite material is fabricated( Figure 4 (D)), and a through hole 131 penetrating in the vertical direction is formed in the disk-shaped member 130( Figure 4 (E)). When the ceramic sintered body 120 is made of alumina, the disk-shaped member 130 is preferably made of SiSiCTi or AlSiC. This is because the thermal expansion coefficient of alumina is approximately the same as that of SiSiCTi and AlSiC.

[0059] The SiSiCTi-based disk-shaped member can be fabricated, for example, as follows. First, silicon carbide, metallic Si, and metallic Ti are mixed to produce a powder mixture. Next, the obtained powder mixture is uniaxially press molded to form a disk-shaped compact, and the compact is hot press sintered in an inert atmosphere to obtain the SiSiCTi-based disk-shaped member.

[0060] Next, a metal bonding material is disposed on the upper surface of the disk-shaped member 130 made of a metal-ceramic composite material. A through hole communicating with the through hole 131 is provided in advance in the metal bonding material. The power supply terminal 54 of the ceramic sintered body 120 is inserted into the through hole 131 of the disk-shaped member 130, and the ceramic sintered body 120 is placed on the metal bonding material disposed on the upper surface of the disk-shaped member 130. Accordingly, a laminate obtained by laminating the disk-shaped member 130, the metal bonding material, and the ceramic sintered body 120 in this order from the lower side is obtained. The laminate is heated and pressed (TCB) to obtain a joined body 112( Figure 4 (F)). The joined body 112 is obtained by joining the ceramic sintered body 120 to the upper surface of the disk-shaped member 130 that serves as the basis for the top substrate 30 with a metal bonding layer 40.

[0061] The TCB is performed as follows. That is, the laminate is pressed and joined at a temperature below the solidus temperature of the metal bonding material (for example, at a temperature above the temperature obtained by subtracting 20°C from the solidus temperature and below the solidus temperature), and then returned to room temperature. Accordingly, the metal bonding material becomes a metal bonding layer (or a conductive bonding layer). As the metal bonding material at this time, an Al-Mg-based bonding material or an Al-Si-Mg-based bonding material can be used. For example, when performing TCB using an Al-Si-Mg-based bonding material, the laminate is pressed in a state of being heated in a vacuum atmosphere. The metal bonding material is preferably a metal bonding material having a thickness of about 100 μm.

[0062] Next, the outer periphery of the ceramic sintered body 120 is cut to form a step, thereby fabricating a ceramic substrate 20 having a central portion 22 and an outer peripheral portion 24. Additionally, as needed, the outer periphery of the circular plate member 130 is cut, thereby fabricating a top substrate 30. At this time, the outer peripheral portion 34 of the top substrate 30 protrudes with respect to the outer periphery of the ceramic substrate 20. Further, the side surface of the outer peripheral portion 24 of the ceramic substrate 20, the periphery of the metal bonding layer 40, the upper surface, and the side surface of the top substrate 30 are sprayed with ceramic powder, thereby forming an insulating film 42( Figure 4 (G)). Accordingly, the upper substrate 12 is obtained.

[0063] For example, the lower substrate 80 is fabricated as follows. First, a machinable circular plate member 180( Figure 5 (A)) that is circular plate-shaped and made of a machinable material and serves as the basis of the lower substrate 80 is prepared. The machinable circular plate member 180 is preferably made of aluminum, aluminum alloy, stainless steel, or resin. Next, a flow path groove 88 and a seal groove 89 (two outer grooves 89a and two inner grooves 89b) are formed on the upper surface of the machinable circular plate member 180, and an inlet 88a and an outlet 88b that penetrate in the vertical direction from the lower surface of the machinable circular plate member 180 to the bottom surface of the flow path groove 88 are formed. Additionally, through holes 181 and 182 that penetrate in the vertical direction are formed in the machinable circular plate member 180( Figure 5 (B)). Accordingly, the lower substrate 80 is obtained.

[0064] For the wafer stage 10, for example, the upper substrate 12, the lower substrate 80, and the seal member 16 fabricated as described above are assembled as follows. First, the outer seal member 16a is disposed in the outer groove 89a of the lower substrate 80, and the inner seal member 16b is disposed in the inner groove 89b. Next, the power supply terminal 54 of the upper substrate 12 is inserted into the through hole 181, and the upper substrate 12 is placed on the seal member 16 disposed on the upper surface of the lower substrate 80( Figure 6(A)). Then, insulating tubes 55 through which the power supply terminals 54 are inserted are arranged in the through holes 131 and 181, and an insulating tube 65 through which the power supply terminal 64 is inserted is arranged in the through hole 182. Figure 6 (B)). Accordingly, the wafer stage 10 is obtained by sequentially overlapping the lower substrate 80, the sealing member 16, and the upper substrate 12 from the lower side. The obtained wafer stage 10 clamps and uses the upper substrate 12 and the lower substrate 80 in a manner of squeezing the sealing member 16 from above and below.

[0065] Next, Figure 1 is used to describe a usage example of the wafer stage 10. As described above, the wafer stage 10 is fixed to the mounting plate 96 of the chamber 94 by the clamping member 70. A shower head 98 for releasing process gas from a plurality of gas ejection holes into the interior of the chamber 94 is arranged on the top surface of the chamber 94.

[0066] A focus ring 78 is placed on the FR placement surface 24a of the wafer stage 10, and a disk-shaped wafer W is placed on the wafer placement surface 22a. The focus ring 78 has a step along the inner circumference of the upper end to prevent interference with the wafer W. In this state, a DC voltage of the wafer adsorption DC power supply 52 is applied to the wafer adsorption electrode 26 to adsorb the wafer W to the wafer placement surface 22a. Then, the interior of the chamber 94 is set to a prescribed vacuum atmosphere (or reduced pressure atmosphere), and while supplying process gas from the shower head 98, an RF voltage from the RF power supply 62 is applied to the top substrate 30. As a result, plasma is generated between the wafer W and the shower head 98. Then, using this plasma, CVD film formation or etching is performed on the wafer W. It should be noted that as the wafer W is subjected to plasma processing, the focus ring 78 is also consumed. However, since the focus ring 78 is thicker than the wafer W, the focus ring 78 is replaced after processing a plurality of wafers W.

[0067] In the wafer stage 10 described above, a cooling base material having a refrigerant flow path inside is not used. Instead, a refrigerant flow path 18 is formed by the lower surface of the upper base material 12, the upper surface of the lower base material 80 having flow path grooves 88 formed on the upper surface, and the sealing member 16 disposed therebetween. In this wafer stage 10, the upper base material 12 forming the top surface of the refrigerant flow path 18 and the lower base material 80 forming the side wall surface of the refrigerant flow path 18 are not integrated, and the sealing member 16 is disposed therebetween. Therefore, even if a thermal expansion difference occurs between the top surface and the side wall surface of the refrigerant flow path 18, the sealing member 16 absorbs the influence thereof. Therefore, based on the wafer stage having a refrigerant flow path, it is possible to prevent the wafer stage from being damaged due to thermal stress. In addition, the sealing member 16 alleviates the influence of the thermal expansion difference that sometimes occurs between the top surface and the side wall surface of the refrigerant flow path 18. Therefore, it is not necessary to make the thermal expansion coefficients of the top base material 30 forming the top surface and the lower base material 80 forming the side wall surface the same, and the degree of freedom in selecting the materials of the top base material 30 and the lower base material 80 is relatively high.

[0068] In addition, a top base material 30 made of a metal-ceramic composite material having a higher toughness than that of a ceramic material is disposed on the portion of the lower surface side of the upper base material 12 where thermal stress is likely to occur. Therefore, even if thermal stress occurs, it is not easily damaged. In addition, the ceramic base material 20 and the top base material 30 are joined by a metal bonding layer 40. Therefore, the heat dissipation ability is higher than that in the case of being joined by a resin layer. In addition, since the top base material 30 is made of a metal-ceramic composite material, the absolute value of the difference in linear thermal expansion coefficient from the ceramic base material 20 is small. Therefore, the upper base material 12 is not easily subjected to thermal stress, and warping and breakage of the upper base material 12 due to thermal stress are not likely to occur. In addition, since the metal-ceramic composite material has electrical conductivity, the top base material 30 can also be used as an RF electrode, and there is no need to separately prepare an RF electrode. Here, the absolute value of the difference in linear thermal expansion coefficient between the top base material 30 and the ceramic base material 20 in the range of 40 to 400 °C is preferably 1.5×10 -6 / K or less. Accordingly, since the thermal expansion difference between the ceramic base material 20 and the top base material 30 is small, the upper base material 12 is not easily subjected to thermal stress. When the ceramic base material 20 is an alumina base material, as the metal-ceramic composite material of the top base material 30, AlSiC or SiSiCTi is preferably used, for example. Since the absolute value of the difference in linear thermal expansion coefficient between AlSiC or SiSiCTi forming the top base material 30 and alumina forming the ceramic base material 20 is small, the upper base material 12 is not easily subjected to thermal stress. It should be noted that the metal bonding layer 40 or the lower base material 80 can be used as the RF electrode to replace using the top base material 30 as the RF electrode.

[0069] In addition, the lower substrate 80 is made of a material with easy processability. Therefore, the formation of the flow path grooves 88 and the sealing grooves 89 is easy, and the processing cost can be reduced. In addition, since the sealing groove 89 is provided on the upper surface of the lower substrate 80, the positioning of the sealing member 16 is easy.

[0070] Furthermore, since the outer sealing members 16a are provided in multiple layers, the outer sealing members 16a on the flow path groove 88 side are protected from process gases and plasmas by the outermost peripheral outer sealing member 16a, and the corrosion resistance can be improved. At this time, if the outermost peripheral outer sealing member 16a is made of a material with higher corrosion resistance than the outer sealing member 16a on the flow path groove 88 side, the corrosion resistance can be further improved. For example, the outermost peripheral outer sealing member 16a can be made of metal, and the outer sealing member 16a on the flow path groove 88 side can be made of resin.

[0071] Moreover, the upper substrate 12 and the lower substrate 80 are clamped by the clamping member 70. If it is a mechanical joining such as clamping, the sealing member 16 can be sufficiently pressed from above and below, and thus the sealing function of the sealing member 16 can be fully exerted. It should be noted that, as mechanical joining, in addition to clamping, bolt fastening, rivet fastening, etc. can also be cited.

[0072] It should be noted that the present invention is not limited by any of the above-described embodiments. Of course, as long as it belongs to the technical scope of the present invention, it can be implemented in various ways.

[0073] For example, in the wafer mounting stage 10 of the above-described embodiment, holes penetrating the wafer mounting stage 10 can be provided so as to reach the wafer mounting surface 22a from the lower surface of the lower substrate 80. Examples of such holes include: a gas supply hole for supplying a heat conduction gas (e.g., He gas) to the back surface of the wafer W, and a lift pin hole through which a lift pin for moving the wafer W up and down relative to the wafer mounting surface 22a is inserted. The heat conduction gas is supplied to the space formed by a plurality of small protrusions (not shown) provided on the wafer mounting surface 22a (for supporting the wafer W) and the wafer W. The lift pin holes are provided at three locations when the wafer W is supported by, for example, three lift pins. When the above-described through holes are provided, in the space between the lower surface of the upper substrate 12 and the upper surface of the lower substrate 80, sealing members 16 (inner sealing members 16b) are also arranged around the gas supply holes and the lift pin holes, similarly to the periphery of the insulating tubes 55 and 65.

[0074] In the wafer stage 10 of the above-described embodiment, the top substrate 30 made of a metal-ceramic composite material is used. However, instead, a metal top substrate may be used. In this case, similar to the top substrate 30 made of a metal-ceramic composite material, the metal top substrate is preferably made of a metal material having high toughness and conductivity. In addition, the absolute value of the linear thermal expansion coefficient difference between 40 and 400 °C between the metal top substrate and the ceramic substrate 20 is preferably 1.5×10 -6 / K or less. For the metal top substrate, for example, when the ceramic substrate 20 is an aluminum nitride substrate, a molybdenum substrate may be used. For the linear thermal expansion coefficient between 40 and 400 °C, aluminum nitride is 4.6×10 -6 / K, and molybdenum is 5.6×10 -6 / K.

[0075] In the wafer stage 10 of the above-described embodiment, the top substrate 30 made of a metal-ceramic composite material is used. However, it is possible to use a top substrate 230 made of a ceramic material having the same main component as the ceramic substrate 20, as in the Figure 7 wafer stage 210. Figure 7 FIG. is a longitudinal sectional view of the wafer stage 210 including the top substrate 230. Figure 7In the following, the same reference numerals are assigned to the same components as those in the above-described embodiments. In the wafer mounting stage 210, the upper base material 212 includes: a ceramic base material 20; a top base material 230 that is disposed on the lower side of the ceramic base material 20 and forms the top of the refrigerant flow path 18; and a metal bonding layer 40 that bonds the ceramic base material 20 and the top base material 230. The top base material 230 is made of a ceramic material having the same main component as the ceramic base material 20. The main component means a component that occupies 50% by mass or more, preferably 70% by mass or more, and more preferably 90% by mass or more of the entire components contained. Since the absolute value of the difference in linear thermal expansion coefficient between ceramic materials having the same main component is small, in the upper base material 212 including the top base material 230 described above, the thermal expansion difference between the top base material 230 and the ceramic base material 20 is small, and warping and breakage of the upper base material 212 due to thermal stress are less likely to occur. The top base material 230 may be made of a material having a lower purity than the purity of the ceramic base material 20. For example, for the ceramic base material 20, from the viewpoint of improving the electrical characteristics as a dielectric layer, alumina with a higher purity (for example, 99% or more alumina) is used. For the top base material 230, from the viewpoint of improving mechanical characteristics (toughness, strength) and reducing costs, alumina with a lower purity (for example, less than 99% alumina) may be used. A material with a lower purity may contain a large amount of glassy substances such as SiO2 compared with a material with a higher purity. Since the ceramic material-made top base material 230 does not have conductivity, it cannot be used as an RF electrode. Therefore, in the wafer mounting stage 210, the metal bonding layer 40 can be connected to an RF power supply via a power supply terminal 64 and has a function as an RF electrode. The power supply terminal 64 is arranged to pass through the insulating tube 65 and reach the metal bonding layer 40 from the lower surface of the top base material 230. In the wafer mounting stage 210 described above, the toughness of the top base material 230 is lower than that of the top base material 30 made of a metal-ceramic composite material, and the top base material 230 cannot function as an RF electrode. However, other than this, the same effects as those of the wafer mounting stage 10 are obtained. In addition, the wafer mounting stage 210 has the advantage that the preparation cost can be suppressed to be lower compared with the case of using a metal-ceramic composite material that easily matches the thermal expansion coefficients of the ceramic base material 20 and the top base material 230. It should be noted that in the wafer mounting stage 210, the top base material 230 is made of a ceramic material having the same main component as the ceramic base material 20, but it may be made of a ceramic material having a different main component from the ceramic base material 20. In this case, the absolute value of the difference in linear thermal expansion coefficient between 40 and 400 °C between the ceramic material-made top base material and the ceramic base material 20 is also preferably 1.5×10 -6 / K or less. In addition, the lower substrate 80 may be used as an RF electrode instead of using the metal bonding layer 40 as an RF electrode. In addition, the ceramic substrate 20 and the top substrate 230 are bonded by the metal bonding layer 40. However, when the ceramic substrate 20 and the top substrate 230 are manufactured, the two may be sintered as one body, and the metal bonding layer 40 may be omitted.

[0076] In the wafer stage 10 of the above embodiment, the upper substrate 12 includes the ceramic substrate 20, the top substrate 30 and the metal bonding layer 40. Figure 8 Like the wafer placing table 310 , the upper substrate 312 may be a single layer of the ceramic substrate 320 . Figure 8 1 is a longitudinal cross-sectional view of a wafer stage 310 including an upper substrate 312 having a single-layer ceramic substrate 320 . Figure 8 , the same reference numerals are given to the same components as those in the above-mentioned embodiment. In the wafer placing table 310, the upper substrate 312 is a single layer of a ceramic substrate 320. The material of the ceramic substrate 320 is the same as that of the ceramic substrate 20. The ceramic substrate 320 has an outermost peripheral portion 325 at the outer periphery of the outer peripheral portion 24 having the focus ring placing surface 24a. The upper surface of the outermost peripheral portion 325 is lowered by one step relative to the focus ring placing surface 24a. The outer diameter of the outermost peripheral portion 325 is the same as the outer diameter of the lower substrate 80. The upper substrate 312 is clamped to the setting plate 96 together with the lower substrate 80 at the outermost peripheral portion 325. The central portion 22 of the ceramic substrate 320 has an RF electrode 328 built in between the wafer adsorption electrode 26 and the lower surface of the ceramic substrate 320. The RF electrode 328 is formed of a material containing, for example, W, Mo, WC, MoC, etc. An RF power source is connected to the RF electrode 328 via the power supply terminal 64. The power supply terminal 64 is provided so as to pass through the insulating tube 65 disposed in the through hole penetrating the lower substrate 80 in the vertical direction and reach the RF electrode 328 from the lower surface of the ceramic substrate 320. In the wafer stage 310 described above, the effect of the top substrate 30 protecting the ceramic substrate 20 cannot be obtained, but other than this, the same effect as the wafer stage 10 can be obtained. In addition, the wafer stage 310 has the advantage that it is not necessary to bond the ceramic substrate 320 to other components (such as the top substrate 30), and the TCB can be omitted. It should be noted that in the wafer stage 310, the ceramic substrate 320 has the RF electrode 328 built therein, but the RF electrode 328 may also be provided on the lower surface. Alternatively, the lower substrate 80 may be used as the RF electrode.

[0077] In the wafer stage 10 of the above embodiment, the outer diameter of the ceramic substrate 20 is smaller than the outer diameters of the top substrate 30 and the lower substrate 80. However, the outer diameter of the ceramic substrate 20 may be the same as the outer diameters of the top substrate 30 and the lower substrate 80. In this case, the ceramic substrate 20 may be Figure 8Unlike the ceramic substrate 320 of the wafer stage 310, the outermost periphery of the outer periphery 24 has an outermost periphery that is one level lower than the focus ring mounting surface 24a. In this case, the wafer stage 10 and the setting plate 96 are integrated with the inner peripheral step surface 70a of the clamping member 70 provided at the outermost periphery of the ceramic substrate 320. Accordingly, the upper substrate 12 and the lower substrate 80 of the wafer stage 10 are clamped, and the sealing member 16 is pressed in the vertical direction to seal between the refrigerant flow path 18 and the outside. At this time, in the upper substrate 12, the rigidity of the portion of the outer periphery 34 of the top substrate 30 that is reinforced and clamped by the outermost periphery of the ceramic substrate 20 is increased. Therefore, the sealing member 16 is firmly pressed in the vertical direction by clamping, and can be sealed more reliably.

[0078] In the above embodiment, the wafer stage 10 is mounted on the setting plate 96 by using the clamping member 70. However, as shown in Figure 9 , it can be mounted on the setting plate 96 by using bolts 76. Accordingly, the upper substrate 12 and the lower substrate 80 of the wafer stage 10 are mechanically joined. The bolts 76 are preferably arranged with a clearance between the outer peripheral surface of the bolts 76 and the inner peripheral surface of the mounting holes of at least one of the upper substrate 12 and the lower substrate 80, so that relative movement in the horizontal direction can be achieved between the upper substrate 12 and the lower substrate 80. It should be noted that the upper substrate 12 and the lower substrate 80 can be mechanically joined (clamped, bolted, etc.) and separately mounted on the setting plate 96. In addition, bolt tightening can be performed from below instead of from above. In this case, the upper substrate 12 and the lower substrate 80 can be mechanically joined on the inner peripheral side instead of the outer peripheral side.

[0079] In the above embodiment, the wafer adsorption electrode 26 is provided inside the central portion 22 of the ceramic substrate 20. However, an RF electrode for plasma generation can be provided instead of the wafer adsorption electrode 26, or in addition to the wafer adsorption electrode 26, an RF electrode for plasma generation can also be provided. In this case, the high-frequency power supply is connected to the RF electrode instead of the top substrate 30. In addition, a focus ring (FR) adsorption electrode can be provided inside the outer periphery 24 of the ceramic substrate 20. In this case, the DC power supply is connected to the FR adsorption electrode. In addition, a heater electrode (resistance heating element) can be provided inside the ceramic substrate 20. In this case, the heater power supply is connected to the heater electrode. In this way, the ceramic substrate 20 can have one layer of electrodes or two or more layers of electrodes. The same applies to the ceramic substrate 320.

[0080] In the above embodiment, the sealing groove 89 for arranging the sealing member 16 is provided on the upper surface of the lower substrate 80. However, the sealing groove 89 can be omitted, or the sealing groove can be provided on the lower surface of the upper substrate 12.

[0081] In the above-described embodiment, the outer sealing member 16a is double, but it may be single or triple or more. Further, the inner sealing member 16b is single, but it may be double or more. Further, instead of the outer sealing member 16a and the inner sealing member 16b, a parallel sealing member configured to surround the flow path groove 88 may be disposed along the flow path groove 88, or in addition to the outer sealing member 16a and the inner sealing member 16b, a parallel sealing member configured to surround the flow path groove 88 may be disposed along the flow path groove 88. When the parallel sealing member is employed, the flow of the refrigerant through the gap between the lower surface of the upper substrate 12 and the upper surface of the lower substrate 80 is suppressed. It should be noted that even without the parallel sealing member, the flow of the refrigerant through the gap between the lower surface of the upper substrate 12 and the upper surface of the lower substrate 80 is not so much, and thus the flow of the refrigerant through the gap has little influence on the heat uniformity. Further, when there is no parallel sealing member, the manufacturing is easy.

[0082] In the above-described embodiment, the flow path groove 88 is formed in a spiral shape from the inlet 88a to the outlet 88b, but the shape of the flow path groove 88 is not particularly limited. Further, a plurality of flow path grooves 88 may be provided.

[0083] The insulating tube 65 may be omitted in the above-described embodiment.

[0084] In the above-described embodiment, Figure 4 The ceramic sintered body 120 of A is manufactured by hot press sintering a molded body of ceramic powder. However, the molded body at this time may be manufactured by laminating a plurality of tape cast molded bodies, may be manufactured by a die casting method, or may be manufactured by pressing ceramic powder.

[0085] In the above-described embodiment, the lower substrate 80 is made of an easily machinable material, but the lower substrate 80 may be made of a composite material of metal and ceramic, or may be made of a low thermal expansion metal such as molybdenum. Accordingly, since the difference in the coefficient of thermal expansion between the lower substrate 80 and the upper substrate 12 is small, warping and breakage of the upper substrate 12 or the lower substrate 80 due to thermal stress can be further suppressed.

[0086] In the wafer mounting stage 10 of the above-described embodiment, there is a gap between the lower surface of the upper substrate 12 and the upper surface of the lower substrate 80. However, for example Figure 10 , 11 As shown in the wafer mounting stage 410, a heat sink 417 may be disposed between the lower surface of the upper substrate 412 and the upper surface of the lower substrate 480. Figure 10 It is a longitudinal sectional view of the wafer mounting stage 410 including the heat sink 417. Figure 11This is a cross-sectional view obtained by cutting the wafer stage 410 along a horizontal plane including the heat sink 417 when viewed from above. Figure 10 , 11 In the figure, the same reference numerals are assigned to the same components as those in the above-described embodiment. In this wafer stage 410, the upper substrate 412 and the lower substrate 480 are fastened with screw members 477 (e.g., bolts). In addition, the wafer stage 410 is fastened to a mounting plate 96 provided inside the chamber 94 with screw members 472 (e.g., bolts). The screw members 472 are inserted from the lower surface of the mounting plate 96 and screwed into screw holes 488 that are open on the lower surface of the lower substrate 480. In addition, the power supply terminal 64 is connected to the lower substrate 480, rather than to the top substrate 430. It should be noted that, in addition to the wafer stage 10, the wafer stages 210 and 310 may also be appropriately configured in the same manner as the wafer stage 410.

[0087] The upper substrate 412 includes a top substrate 430 having a plurality of screw holes 437 provided on the lower surface, and is otherwise configured in the same manner as the upper substrate 12. In addition, the top substrate 430 has a plurality of screw holes 437 provided on the lower surface, and is otherwise configured in the same manner as the top substrate 30. Here, one screw hole 437 is provided at the center of the top substrate 430, six screw holes are provided at equal intervals along the circumferential direction of the top substrate 430 closer to the outer periphery than the center, and six screw holes are provided at equal intervals along the circumferential direction of the top substrate 430 further from the center, but it is not limited thereto. In addition, here, the screw holes 437 are formed by providing cylindrical holes on the lower surface of the top substrate 430 and directly cutting thread grooves in the cylindrical holes (illustrations are omitted), but it is not particularly limited thereto. For example, the screw holes 437 can be formed by inserting spiral thread inserts into the cylindrical holes, or by inserting terminals with internal threads (e.g., cap nuts, etc.) into the cylindrical holes and brazing them. The depth of the screw holes 437 is not particularly limited, and can be 2 times or less of the nominal diameter of the screw members 477, or 1.5 times or less. Accordingly, the thickness of the upper substrate 412 and the top substrate 430 can be made thinner. From the viewpoint of sufficiently generating the axial force of the screw members 477, the depth of the screw holes 437 is preferably 1 time or more of the nominal diameter of the screw members 477. The center-to-center spacing between two adjacent screw holes 437 is not particularly limited, and is preferably 100 mm or less, for example. Accordingly, the top substrate 430 and the lower substrate 480 can be tightly fastened by the screw members 477, and further, the thermal conductivity of the heat sink 417 can be improved. The center-to-center spacing between two adjacent screw holes 437 can be 50 mm or more, for example. The screw holes 437 are preferably arranged on the lower surface of the top substrate 430 at a ratio of 150 per m 2 or more, and more preferably at a ratio of 200 per m 2configured in the above ratio. Accordingly, the top substrate 430 and the lower substrate 480 can be fastened more tightly by the screw member 477, and further, the thermal conductivity of the heat sink 417 is improved. It should be noted that the screw hole 437 may be provided on the lower surface of the top substrate 430, and it may be Figure 10 the blind hole shown, or it may be a through hole that penetrates from the lower surface to the upper surface of the top substrate 430. Figure 8 In the wafer mounting stage 310 of Figure 8 , there is no component corresponding to the top substrate 430 in the upper substrate 312. However, screw holes similar to the screw hole 437 may be provided on the lower surface of the upper substrate 312 formed of the ceramic substrate 320. In this case, the screw hole is preferably a blind hole that does not reach the wafer adsorption electrode 26.

[0088] The lower substrate 480 has a plurality of through holes 487 and screw holes 488 on the lower surface, and is otherwise configured in the same manner as the lower substrate 80. The through holes 487 are provided at positions opposed to the screw holes 437 and penetrate the lower substrate 480 in the vertical direction. The through holes 487 are stepped holes with a large diameter on the lower side and a small diameter on the upper side. The through holes 487 have a large diameter portion 487a for accommodating the head 477a of the screw member 477 and a small diameter portion 487b through which the leg portion 477b of the screw member 477 passes and the head 477a cannot pass.

[0089] The heat sink 417 is disposed between the lower surface of the upper substrate 412 and the portion of the upper surface of the lower substrate 480 where the flow path groove 88 and the sealing member 16 are not provided. The heat sink 417 is sandwiched between the upper substrate 412 and the lower substrate 480 and is compressed in the vertical direction. Accordingly, the heat sink 417 is firmly adhered to the lower surface of the upper substrate 412 and the upper surface of the lower substrate 480, and thus, the heat of the upper substrate 412 is quickly conducted to the lower substrate 480. The thermal resistance of the heat sink 417 is preferably 0.5 K·cm 2 / W or less, more preferably 0.35 K·cm 2 / W or less, and further preferably 0.1 K·cm 2Below 1 W. Accordingly, the efficiency of cooling the wafer W can be further improved. In addition, the thermal conductivity of the heat sink 417 is preferably 2 W / (m·K) or more, more preferably 3 W / (m·K) or more, and further preferably 10 W / (m·K) or more. Accordingly, the efficiency of cooling the wafer W can be further improved. The thermal resistance and thermal conductivity of the heat sink 417 are the thermal resistance and thermal conductivity in the vertical direction in the state where the heat sink 417 is assembled (that is, the state where the heat sink 417 is compressed in the vertical direction under a specified pressure), and can be measured according to ASTM-D5470. The Young's modulus of the heat sink 417 is preferably 100 MPa or less, more preferably 20 MPa or less, and further preferably 5 MPa or less. The smaller the Young's modulus of the heat sink 417, the more uniform the transmission of the fastening force of the screw member 477 over the entire surface of the heat sink 417. Therefore, the heat sink 417 is firmly bonded to the upper substrate 412 and the lower substrate 480 over its entire surface. Therefore, the wafer W can be cooled more uniformly. The Poisson's ratio of the heat sink 417 is preferably 0.4 or less, more preferably 0.3 or less, and further preferably 0.2 or less. The smaller the Poisson's ratio of the heat sink 417, the more uniform the transmission of the fastening force of the screw member 477 over the entire surface of the heat sink 417, and the less likely it is to escape laterally. Therefore, the heat sink 417 is firmly bonded to the upper substrate 412 and the lower substrate 480 over its entire surface. Therefore, the wafer W can be cooled more uniformly. The Shore hardness (Shore OO) of the heat sink 417 can be 50 or more and 80 or less. The thickness of the heat sink 417 is preferably, for example, 0.05 mm or more and 1 mm or less, and more preferably 0.1 mm or more and 0.3 mm or less.

[0090] Specifically, the heat sink 417 is preferably a sheet material containing carbon and resin. Examples of carbon include graphite, carbon fiber, carbon nanotubes, etc., and examples of resin include silicone resin, etc. When the carbon is graphite, it is preferably arranged such that the plane direction of the graphene constituting the graphite is along the vertical direction, and when the carbon is carbon fiber or carbon nanotube, it is preferably arranged such that the axial direction is along the vertical direction. As the material of the heat sink 417, for example, a thermal interface material (TIM) can be used. Specific examples of the heat sink 417 include the EX20000C9 series, the EX20000C4S series (both manufactured by Dexerials Corporation), GraphitePAD, GraphiteTIM (registered trademark) (both manufactured by Panasonic Corporation), etc.

[0091] The screw member 477 has a large-diameter head 477a and a small-diameter foot 477b. The screw member 477 is inserted into the through-hole 487 from the lower surface of the lower substrate 480 and screwed into the screw hole 437 of the top substrate 430. The head 477a of the screw member 477 is received in the large-diameter portion 487a in such a manner that it does not protrude below the lower surface of the lower substrate 480. By screwing the screw member 477 into the screw hole 437, the upper substrate 412 and the lower substrate 480 are fastened in a state sandwiching the heat sink 417 and the sealing member 16. Accordingly, the heat sink 417 and the sealing member 16 are compressed in the vertical direction. The material of the screw member 477 is preferably a material having good electrical conductivity and thermal conductivity, for example, stainless steel is preferred. The nominal diameter of the screw member 477 can be, for example, 3 mm or more and 10 mm or less, can be 4 mm or more and 8 mm or less, and can be 6 mm or more and 8 mm or less.

[0092] In this wafer stage 410, heat of the upper substrate 412 is easily conducted downward to the lower substrate 480 quickly through the heat sink 417. Therefore, the effect of cooling the wafer W is improved. In addition, the upper substrate 412 and the lower substrate 480 are fastened with the screw member 477. Accordingly, the heat sink 417 is firmly adhered to the upper substrate 412 and the lower substrate 480, and thus, heat of the upper substrate 412 is conducted downward to the lower substrate 480 more quickly. As a result, the effect of cooling the wafer is further improved. It should be noted that in the case where there is no heat sink 417, the refrigerant enters to replace the heat sink 417. However, the refrigerant entering the gap between the upper substrate 412 and the lower substrate 480 does not easily flow and stays in place in many cases. Therefore, it is difficult to transfer heat of the upper substrate 412 to the lower substrate 480 using the gap. Therefore, it is preferable to dispose a heat sink 417 having a low thermal resistance (good thermal conductivity) in the gap like the wafer stage 410.

[0093] In addition, the thermal resistance of the heat sink 417 is preferably 0.50 K·cm 2 / W or less. Accordingly, the heat of the upper substrate 412 is conducted downward to the lower substrate 480 more quickly, and thus the efficiency of cooling the wafer W is further improved. When achieving this thermal resistance, it is preferable to set the pressure for compressing the heat sink 417 in the vertical direction to, for example, 0.05 MPa or more and 0.2 MPa or more. Accordingly, since the heat sink 417 is firmly adhered to the upper substrate 412 and the lower substrate 480, the thermal resistance of the heat sink 417 can be reduced. From the viewpoint of suppressing breakage of the heat sink 417, the pressure for compressing the heat sink 417 in the vertical direction is preferably 0.6 MPa or less and 0.55 MPa or less. However, the pressure for compressing the heat sink 417 in the vertical direction tends to be smaller as the distance from the screw member 477 is farther, and there is an amplitude in the in-plane direction. The value obtained by dividing the amplitude [MPa] of this pressure by the surface pressure [MPa] applied to the heat sink 417 when the axial force of the screw member 477 is evenly applied to the heat sink 417 is set as the pressure deviation [-] for evaluation. At this time, the pressure deviation is preferably 2.0 or less, more preferably 1.7 or less, and further preferably 1.0 or less. The smaller the Young's modulus of the heat sink 417, the smaller the pressure deviation; the smaller the center-to-center interval of the screw holes 437, the smaller the pressure deviation. On the other hand, if the center-to-center interval of the screw holes 437 is made smaller in order to reduce the pressure deviation, a large number of screw holes 437 are required, and sometimes the arrangement of the screw holes 437 becomes difficult. According to simulation, when the Young's modulus of the heat sink 417 is 80 MPa or less, if the center-to-center distance of the screw holes 437 is 70 mm or less, the pressure deviation is 2.0 or less, and if the center-to-center distance of the screw holes is 55 mm or less, the pressure deviation is 1.0 or less. In addition, when the Young's modulus of the heat sink 417 is 10 MPa or less, even if the center-to-center distance of the screw holes 437 is 100 mm, the pressure deviation is about 1. Thus, from the viewpoint of not reducing the center-to-center distance of the screw holes 437 too small to reduce the pressure deviation, the Young's modulus of the heat sink 417 is preferably 80 MPa or less, and more preferably 10 MPa or less. The number and arrangement of the screw holes 437 are preferably set in consideration of the pressure deviation based on the pressure required to compress the heat sink 417 and the sealing member 16 and the pressure required to withstand the pressure of the refrigerant flowing through the refrigerant flow path 18.

[0094] Moreover, the heat sink 417 has conductivity. Accordingly, the lower substrate 480 has the same potential as the top substrate 430 and the metal bonding layer 40. Therefore, if a power supply terminal 64 is connected to the lower substrate 480, the top substrate 430 and the metal bonding layer 40 can be used as RF electrodes, and it is easy to generate plasma above the wafer W. It should be noted that a conductive screw member 477 can be used to make the lower substrate 480 and the top substrate 430 have the same potential by means of the screw member 477.

[0095] It should be noted that in the wafer stage 410, the heat sink 418 shown in Figure 12 may be used instead of the heat sink 417. The heat sink 418 includes a main body portion 418a having the same shape as the heat sink 417 and a bridging portion 418b provided over the flow path groove 88. Through the main body portion 418a, the heat of the upper substrate 412 can be quickly conducted downward to the lower substrate 480. Through the bridging portion 418b, the sheet shape of the heat sink 418 can be maintained, and the operability of the heat sink 418 can be improved. It should be noted that from the viewpoint of improving the efficiency of cooling the wafer W, it is preferable that the area ratio of the heat sink existing over the flow path groove 88 is low. Therefore, the area of the bridging portion 418b is preferably 1 / 5 or less, more preferably 1 / 10 or less, of the area of the flow path groove 88, for example.

[0096] In the above-described wafer stage 410, the sealing member 16 and the heat sink 417 are used simultaneously. However, the heat sink 417 may have the function of the sealing member.

[0097] Figure 10 In, the wafer stage 410 in which the upper substrate 412 and the lower substrate 480 are fastened with the screw member 477 is provided on the setting plate 96 of the chamber 94, but it is not particularly limited thereto. For example, like the Figure 13 wafer stage 510 shown, the lower substrate 480 may be used as the setting plate 96 of the chamber 94. It should be noted that Figure 13 in, the same reference numerals are given to the same components as those in the above-described embodiments and the like.

Claims

1. A wafer placement table, which has a refrigerant flow path for refrigerant to flow through. The wafer placement table is characterized by comprising: An upper substrate, which has a ceramic substrate with electrodes built therein, and has a wafer placement surface on the upper surface of the ceramic substrate; A lower substrate, on the upper surface of which there are flow channels for forming side walls and a bottom of the refrigerant flow path; and A sealing member, which is disposed between the upper substrate and the lower substrate to seal between the refrigerant flow path and the outside, The upper substrate comprises: the ceramic substrate; a top substrate, which is joined to the lower surface of the ceramic substrate and forms the top of the refrigerant flow path; and a metal bonding layer, which bonds the ceramic substrate and the top substrate, A heat sink is disposed between the lower surface of the upper substrate and the upper surface of the lower substrate, The heat sink comprises: a main body portion, which is disposed on a portion of the upper surface of the lower substrate where no flow channels are provided; and a bridging portion, which is bridged over the flow channels.

2. The wafer placement table according to claim 1, wherein The absolute value of the difference in linear thermal expansion coefficient between 40 and 400 °C between the top substrate and the ceramic substrate is 1.5×10 -6 / K or less.

3. The wafer placement table according to claim 1 or 2, wherein The top substrate is made of a composite material of metal and ceramic.

4. The wafer placement table according to claim 1 or 2, wherein The top substrate is made of a ceramic material having the same main component as the ceramic substrate.

5. The wafer placement table according to claim 1, wherein The upper substrate is a single layer of the ceramic substrate.

6. The wafer placement table according to any one of claims 1, 2, and 5, wherein The lower substrate is made of a material with easy machinability.

7. The wafer placement table according to any one of claims 1, 2, and 5, wherein As the sealing member, an outer sealing member is provided which is multiply arranged so as to surround the outermost edge of the flow path groove.

8. The wafer placement table according to claim 1, wherein The thermal resistance of the heat sink is below 0.5 K·cm 2 / W.

9. The wafer placement table according to claim 1, wherein The Young's modulus of the heat sink is 100 MPa or less.

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