Memory system

Abstract

The present invention relates to a memory system comprising: a plurality of first memory devices each coupled to a first channel and comprising a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and comprising a plurality of second memory blocks; a first access controller adapted to control access to the first memory blocks; a second access controller adapted to control access to the second memory blocks; and a bad block controller adapted to: select one between the first access controller and the second access controller by comparing a bad physical address corresponding to a bad block comprised in each of the first memory devices and the second memory devices with a first physical address and a second physical address respectively corresponding to the first memory blocks and the second memory blocks, and transmit one of the first physical address and the second physical address and a replacement physical address in place of the bad physical address.

Description

[0001] This application is a divisional application of a patent application with application number 201711201655.5, filed on November 27, 2017, and with the title of "Memory System".

[0002] Cross Reference to Related Applications

[0003] This application claims priority to Korean Patent Application No. 10-2017-0033544, filed on March 17, 2017, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0004] Exemplary embodiments of the present invention relate to a memory system including a plurality of memory devices. BACKGROUND

[0005] A computer environment paradigm has changed into a ubiquitous computing system that can be used at any time and at any place. Due to this fact, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having one or more memory devices to store data. The memory system can be used as a main memory device or an auxiliary memory device of the portable electronic devices.

[0006] Since the memory system has no moving parts, they provide excellent stability, durability, high information access speed, and low power consumption. Examples of the memory system having such advantages include a universal serial bus (USB) memory device, a memory card having various interfaces, and a solid state drive (SSD). SUMMARY

[0007] Various embodiments of the present invention relate to a memory system capable of efficiently managing bad memory blocks.

[0008] According to an embodiment of the present invention, a memory system can include a plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks, a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks, a first access controller adapted to control access to the first memory blocks, a second access controller adapted to control access to the second memory blocks, and a bad block controller adapted to select one between the first access controller and the second access controller by comparing a bad physical address corresponding to a bad block included in each of the first memory devices and the second memory devices with first and second physical addresses respectively corresponding to the first memory blocks and the second memory blocks, and to transfer one of the first and second physical addresses and a replacement physical address replacing the bad physical address.

[0009] The bad block controller can include a first bad block table including mapping relationship information between partial entries of bad physical addresses and first replacement physical addresses corresponding to the first storage block, a second bad block table including mapping relationship information between remaining partial entries of bad physical addresses and second replacement physical addresses corresponding to the second storage block, and a path control element adapted to select the first access controller and transmit the first replacement physical address when the first and second physical addresses are identical to the partial entries of bad physical addresses, select the second access controller and transmit the second replacement physical addresses when the first and second physical addresses are identical to the remaining partial entries of bad physical addresses, and select the first access controller and transmit the first physical address or select the second access controller and transmit the second physical address when the first and second physical addresses are not identical to the bad physical addresses.

[0010] The path control element can include a first specific path control element adapted to select the first access controller and transmit the first replacement physical address when the first physical address is identical to the partial entries of bad physical addresses, select the second access controller and transmit the second replacement physical addresses when the first physical address is identical to the remaining partial entries of bad physical addresses, and select the first access controller and transmit the first physical address when the first physical address is not identical to the bad physical addresses, and a second specific path control element adapted to select the second access controller and transmit the second replacement physical address when the second physical address is identical to the remaining partial entries of bad physical addresses, select the first access controller and transmit the first replacement physical address when the second physical address is identical to the partial entries of bad physical addresses, and select the second access controller and transmit the second physical address when the second physical address is not identical to the bad physical addresses.

[0011] The bad block controller can further include a bad information loading element adapted to load information of bad physical addresses and replacement physical addresses from the first memory device and the second memory device, determine which replacement physical addresses are to be mapped to the bad physical addresses based on the number of loaded bad physical addresses, and generate the first bad block table and the second bad block table.

[0012] The bad information loading element can generate the first bad block table and the second bad block table by checking the total number of bad physical addresses stored in the first memory device and the second memory device, and allocating the bad physical addresses in such a manner that the number of partial entries of bad physical addresses and the number of remaining partial entries of bad physical addresses do not exceed a predetermined difference.

[0013] According to another embodiment of the present application, a memory system can include: a plurality of first memory devices each coupled to a first lane of a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second lane of the first channel and including a plurality of second memory blocks; a plurality of third memory devices each coupled to a first lane of a second channel and including a plurality of third memory blocks; a plurality of fourth memory devices each coupled to a second lane of the second channel and including a plurality of fourth memory blocks; a first access controller adapted to control access to the first memory blocks; a second access controller adapted to control access to the second memory blocks; a third access controller adapted to control access to the third memory blocks; a fourth access controller adapted to control access to the fourth memory blocks; a first channel controller adapted to control access to the first access controller and the second access controller; a second channel controller adapted to control access to the third access controller and the fourth access controller; a first bad block controller adapted to select one between the first access controller and the second access controller by comparing a first channel bad physical address corresponding to a bad block included in each of the first memory devices and the second memory devices with a first physical address and a second physical address respectively corresponding to the first memory blocks and the second memory blocks, and transfer one of the first physical address and the second physical address and a replacement physical address instead of the first channel bad physical address; and a second bad block controller adapted to select one between the third access controller and the fourth access controller by comparing a second channel bad physical address corresponding to a bad block included in each of the third memory devices and the fourth memory devices with a third physical address and a fourth physical address respectively corresponding to the third memory blocks and the fourth memory blocks, and transfer one of the third physical address and the fourth physical address and a replacement physical address instead of the second channel bad physical address.

[0014] The first bad block controller can include: a first bad block table including mapping relationship information between partial entries of the first channel bad physical address and first replacement physical addresses corresponding to the first memory blocks; a second bad block table including mapping relationship information between partial entries of the second channel bad physical address and second replacement physical addresses corresponding to the second memory blocks; and a first path control element adapted to: when the first physical address and the second physical address are identical to the first channel bad physical address, select the first channel controller and the first access controller and transfer the first replacement physical address, when the first physical address and the second physical address are identical to the second channel bad physical address, select the first channel controller and the second access controller and transfer the second replacement physical address, and when the first physical address and the second physical address are not identical to the first channel bad physical address, select the first channel controller and the first access controller and transfer the first physical address, or select the first channel controller and the second access controller and transfer the second physical address.

[0015] The second bad block controller can include a third bad block table including mapping relationship information between part of entries of third bad physical addresses and third replacement physical addresses corresponding to the third storage block, a fourth bad block table including mapping relationship information between part of entries of fourth bad physical addresses and fourth replacement physical addresses corresponding to the fourth storage block, and a second path control element adapted to select the second channel controller and the third access controller and transmit the third replacement physical address when the third physical address and the fourth physical address are the same as the third bad physical address, select the second channel controller and the fourth access controller and transmit the fourth replacement physical address when the third physical address and the fourth physical address are the same as the fourth bad physical address, and select the second channel controller and the third access controller and transmit the third physical address or select the second channel controller and the fourth access controller and transmit the fourth physical address when the third physical address and the fourth physical address are not the same as the second channel bad physical address.

[0016] The first path control element can include a first specific path control element adapted to select the first channel controller and the first access controller and transmit the first replacement physical address when the first physical address is the same as the first bad physical address, select the first channel controller and the second access controller and transmit the second replacement physical address when the first physical address is the same as the second bad physical address, and select the first channel controller and the first access controller and transmit the first physical address when the first physical address is not the same as the first channel bad physical address, and a second specific path control element adapted to select the first channel controller and the first access controller and transmit the first replacement physical address when the second physical address is the same as the first bad physical address, select the first channel controller and the second access controller and transmit the second replacement physical address when the second physical address is the same as the second bad physical address, and select the first channel controller and the second access controller and transmit the second physical address when the second physical address is not the same as the first channel bad physical address.

[0017] The second path control element can include a third specific path control element adapted to select the second channel controller and the third access controller and transmit the third replacement physical address when the third physical address is identical to the third bad physical address, select the second channel controller and the fourth access controller and transmit the fourth replacement physical address when the third physical address is identical to the fourth bad physical address, and select the second channel controller and the third access controller and transmit the third physical address when the third physical address is not identical to the second channel bad physical address, and a fourth specific path control element adapted to select the second channel controller and the third access controller and transmit the third replacement physical address when the fourth physical address is identical to the third bad physical address, select the second channel controller and the fourth access controller and transmit the fourth replacement physical address when the fourth physical address is identical to the fourth bad physical address, and select the second channel controller and the fourth access controller and transmit the fourth physical address when the fourth physical address is not identical to the second channel bad physical address.

[0018] The first bad block controller can further include a first bad information loading element adapted to load information of the first channel bad physical addresses and the first and second replacement physical addresses from the first and second memory devices, determine which of the first and second replacement physical addresses are to be mapped to the first channel bad physical addresses based on the number of the loaded first channel bad physical addresses, and generate the first and second bad block tables.

[0019] The first bad information loading element can generate the first and second bad block tables by checking the total number of the first channel bad physical addresses stored in the first and second memory devices, and allocating the first channel bad physical addresses in such a manner that the number of the first bad physical addresses and the number of the second bad physical addresses do not exceed a predetermined difference.

[0020] The second bad block controller can further include a second bad information loading element adapted to load information of the second channel bad physical addresses and the third and fourth replacement physical addresses stored in the third and fourth memory devices, determine which of the third and fourth replacement physical addresses are to be mapped to the second channel bad physical addresses based on the number of the loaded second channel bad physical addresses, and generate the third and fourth bad block tables.

[0021] The second bad information loading element can generate the third and fourth bad block tables by checking the total number of the second channel bad physical addresses stored in the third and fourth memory devices, and allocating the second channel bad physical addresses in such a manner that the number of the third bad physical addresses and the number of the fourth bad physical addresses do not exceed a predetermined difference.

[0022] According to another embodiment of the present application, a memory system can include: a plurality of first memory devices each coupled to a first lane of a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second lane of the first channel and including a plurality of second memory blocks; a plurality of third memory devices each coupled to a first lane of a second channel and including a plurality of third memory blocks; a plurality of fourth memory devices each coupled to a second lane of the second channel and including a plurality of fourth memory blocks; a first access controller adapted to control access to the first memory blocks; a second access controller adapted to control access to the second memory blocks; a third access controller adapted to control access to the third memory blocks; a fourth access controller adapted to control access to the fourth memory blocks; a first channel controller adapted to control access to the first and second access controllers; a second channel controller adapted to control access to the third and fourth access controllers; a bad block controller adapted to select one of the first and second channel controllers, then select one of the first to fourth lane controllers associated with the selected one of the first and second channel controllers by comparing first to fourth physical addresses with bad physical addresses corresponding to bad blocks included in each of the first to fourth memory devices, and transfer one of the first to fourth physical addresses and a replacement physical address in place of the bad physical addresses.

[0023] The bad block controller can include: a first bad block table including mapping relationship information between part of entries of first bad physical addresses and first replacement physical addresses corresponding to a first storage block; a second bad block table including mapping relationship information between part of entries of second bad physical addresses and second replacement physical addresses corresponding to a second storage block; a third bad block table including mapping relationship information between part of entries of third bad physical addresses and third replacement physical addresses corresponding to a third storage block; a fourth bad block table including mapping relationship information between part of entries of fourth bad physical addresses and fourth replacement physical addresses corresponding to a fourth storage block; and a path control element adapted to: select the first channel controller and the first access controller and transmit the first replacement physical address when the first physical address to the fourth physical address is the same as the first bad physical address; select the first channel controller and the second access controller and transmit the second replacement physical address when the first physical address to the fourth physical address is the same as the second bad physical address; select the second channel controller and the third access controller and transmit the third replacement physical address when the first physical address to the fourth physical address is the same as the third bad physical address; select the second channel controller and the fourth access controller and transmit the fourth replacement physical address when the first physical address to the fourth physical address is the same as the fourth bad physical address; and select the first channel controller and the first access controller and transmit the first physical address, or select the first channel controller and the second access controller and transmit the second physical address, or select the second channel controller and the third access controller and transmit the third physical address, or select the second channel controller and the fourth access controller and transmit the fourth physical address when the first physical address to the fourth physical address is not the same as the bad physical address.

[0024] The path control elements can comprise: a first specific path control element adapted to select the first channel controller and the first access controller and transmit the first alternative physical address when the first physical address is identical to the first bad physical address, to select the first channel controller and the second access controller and transmit the second alternative physical address when the first physical address is identical to the second bad physical address, to select the second channel controller and the third access controller and transmit the third alternative physical address when the first physical address is identical to the third bad physical address, to select the second channel controller and the fourth access controller and transmit the fourth alternative physical address when the first physical address is identical to the fourth bad physical address, and to select the first channel controller and the first access controller and transmit the first physical address when the first physical address is not identical to the bad physical address; a second specific path control element adapted to select the first channel controller and the first access controller and transmit the first alternative physical address when the second physical address is identical to the first bad physical address, to select the first channel controller and the second access controller and transmit the second alternative physical address when the second physical address is identical to the second bad physical address, to select the second channel controller and the third access controller and transmit the third alternative physical address when the second physical address is identical to the third bad physical address, to select the second channel controller and the fourth access controller and transmit the fourth alternative physical address when the second physical address is identical to the fourth bad physical address, and to select the first channel controller and the second access controller and transmit the second physical address when the second physical address is not identical to the bad physical address; a third specific path control element adapted to select the first channel controller and the first access controller and transmit the first alternative physical address when the third physical address is identical to the first bad physical address, to select the first channel controller and the second access controller and transmit the second alternative physical address when the third physical address is identical to the second bad physical address, to select the second channel controller and the third access controller and transmit the third alternative physical address when the third physical address is identical to the third bad physical address, to select the second channel controller and the fourth access controller and transmit the fourth alternative physical address when the third physical address is identical to the fourth bad physical address, and to select the second channel controller and the third access controller and transmit the third physical address when the third physical address is not identical to the bad physical address.and a fourth specific path control element adapted to select the first channel controller and the first access controller and transmit the first alternative physical address when the fourth physical address is identical to the first bad physical address, select the first channel controller and the second access controller and transmit the second alternative physical address when the fourth physical address is identical to the second bad physical address, select the second channel controller and the third access controller and transmit the third alternative physical address when the fourth physical address is identical to the third bad physical address, select the second channel controller and the fourth access controller and transmit the fourth alternative physical address when the fourth physical address is identical to the fourth bad physical address, and select the second channel controller and the fourth access controller and transmit the fourth physical address when the fourth physical address is not identical to the bad physical addresses.

[0025] The bad block controller can further include a bad information loading element adapted to load information of the bad physical addresses and the first to fourth alternative physical addresses from the first to fourth memory devices, determine which of the first to fourth alternative physical addresses are to be mapped to the bad physical addresses based on the number of the loaded bad physical addresses, and generate the first to fourth bad block tables.

[0026] The bad information loading element can generate the first to fourth bad block tables by checking the total number of the bad physical addresses stored in the first to fourth memory devices, and allocating the bad physical addresses in such a manner that the number of the first bad physical addresses, the number of the second bad physical addresses, the number of the third bad physical addresses, and the number of the fourth bad physical addresses do not exceed a predetermined difference. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a block diagram illustrating a data processing system including a memory system according to an embodiment of the present application.

[0028] Figure 2 is a block diagram illustrating Figure 1 is a schematic diagram illustrating an exemplary configuration of a memory device employed in the memory system shown.

[0029] Figure 3 is a block diagram illustrating Figure 2 is a circuit diagram illustrating an exemplary configuration of a memory cell array of a memory block in the memory device shown.

[0030] Figure 4 is a block diagram illustrating Figure 2 is a schematic diagram illustrating an exemplary three-dimensional structure of the memory device shown.

[0031] Figure 5 is a block diagram illustrating a memory system according to a first embodiment of the present application.

[0032] Figure 6 is a block diagram illustratingFigure 5 a block diagram of an exemplary configuration of the NFC shown.

[0033] Figure 7 is a block diagram showing a memory system according to a second embodiment of the present application.

[0034] Figure 8 is a block diagram showing Figure 7 a block diagram of an exemplary configuration of the NFC shown.

[0035] Figure 9 is a block diagram showing a memory system according to a third embodiment of the present application.

[0036] Figure 10 is a block diagram showing Figure 9 a block diagram of an exemplary configuration of the NFC shown.

[0037] Figures 11 to 19 is a diagram schematically showing Figure 1 an application example of a data processing system. DETAILED DESCRIPTION

[0038] Various embodiments of the present application will be described in greater detail below, with reference to the accompanying drawings. It should be noted, however, that the present application can be practiced in various embodiments, forms and variations thereof, and is not to be construed as being limited to the embodiments set forth herein. Rather, the described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. Throughout the disclosure, like reference numerals are used to designate like elements throughout the various embodiments and examples of the present application.

[0039] It will be understood that, although the terms "first", "second", "third", and the like can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element or a third element without departing from the spirit and scope of the present application.

[0040] The accompanying drawings are not necessarily drawn to scale, and in some instances, the dimensions of the various elements can have been exaggerated for the sake of clarity and explanation.

[0041] It will be further understood that, when an element is referred to as being "connected to" or "coupled to" another element, it can be directly on, connected to, or coupled to, the other element, or one or more intervening elements can be present. In addition, it will be further understood that, when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements can also be present.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, "including," "having," "includes," "has," "contain," "containing," "characterized by," "characterized" and "characterized as" are open-ended terms that are intended to mean that the respective elements listed are present, but not excluding the presence of one or more additional elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] Unless otherwise defined, all terms used in disclosing elements of the application, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art in the field of the application based on the disclosure provided herein. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0044] In the following description, numerous specific details are described to provide a thorough understanding of the application. The application can be practiced without some or all of these specific details. In other instances, well known process structures and / or processes have not been described in detail in order to avoid unnecessarily obscuring the application.

[0045] It should also be noted that, as will be apparent from the following description, modifications and / or substitutions for described features or elements can be made by those skilled in the relevant art(s) without departing from the spirit of the application as described by the claims.

[0046] Hereinafter, various embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0047] Figure 1 is a block diagram illustrating a data processing system 100 including a memory system 110 according to an embodiment of the present application.

[0048] Referring to Figure 1 , the data processing system 100 can include a host 102 operably coupled to the memory system 110.

[0049] The host 102 can include a portable electronic device such as a mobile phone, an MP3 player, and a laptop computer, or a non-portable electronic device such as a desktop computer, a game machine, a TV, and a projector.

[0050] The host 102 can include at least one OS (operating system), and the OS can manage and control the overall functions and operations of the host 102 and provide operations between the host 102 and a user using the data processing system 100 or the memory system 110. The OS can support functions and operations corresponding to the use purpose and use of the user. For example, the OS can be classified into a general OS and a mobile OS according to the mobility of the host 102. The general OS can be classified into a personal OS and an enterprise OS according to the environment of the user. For example, the personal OS configured to support functions of providing services to general users can include Windows and Chrome, and the enterprise OS configured to protect and support high performance can include Windows Server, Linux, and Unix. In addition, the mobile OS configured to support mobile service functions and system power saving functions to provide services to the user can include Android, iOS, and Windows Mobile. The host 102 can include a plurality of OSs, and the OSs can be executed to perform operations corresponding to the request of the user on the memory system 110.

[0051] The memory system 110 can store data for the host 102 in response to a request of the host 102. Non-limiting examples of the memory system 110 can include a solid state drive (SSD), a multimedia card (MMC), a secure digital (SD) card, a universal storage bus (USB) device, a universal flash (UFS) device, a compact flash (CF) card, a smart media card (SMC), a personal computer memory card international association (PCMCIA) card, and a memory stick. The MMC can include an embedded MMC (eMMC), a reduced size MMC (RS-MMC), and a micro-MMC. The SD card can include a mini-SD card and a micro-SD card.

[0052] The memory system 110 can include various types of storage devices. Examples of non-limiting storage devices included in the memory system 110 can include volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM), and non-volatile memory devices such as read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), and flash memory. In an embodiment, the memory system can employ one or more flash memories having a three-dimensional (3D) stacked structure.

[0053] The memory system 110 can include a memory device 150 and a controller 130. The memory device 150 can store data for the host 120, and the controller 130 can control data storage into the memory device 150.

[0054] The controller 130 and the memory device 150 can be integrated into a single semiconductor device, which can be included in various types of memory systems as exemplified above. For example, the controller 130 and the memory device 150 can be integrated as one semiconductor device to constitute an SSD. When the memory system 110 is used as an SSD, the operation speed of the host 102 connected to the memory system 110 can be improved. In another example, the controller 130 and the memory device 150 can be integrated as one semiconductor device to constitute a memory card. For example, the controller 130 and the memory device 150 can constitute a memory card such as a PCMCIA (Personal Computer Memory Card International Association) card, a CF card, an SMC (Smart Media Card), a memory stick, an MMC including RS-MMC and micro-MMC, an SD card including mini-SD, micro-SD, and SDHC, or a UFS device.

[0055] Non-limiting application examples of the memory system 110 can include a computer, an ultra-mobile personal computer (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless phone, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a memory constituting a data center, a device capable of transmitting / receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, or one of various components constituting a computing system.

[0056] The memory device 150 can be a non-volatile memory device and can retain data stored therein even if power is not supplied. The memory device 150 can store data provided from the host 102 through a write operation and provide data stored therein to the host 102 through a read operation. In an embodiment, the memory device 150 can include a plurality of memory dies (not shown), each of which can include a plurality of planes (not shown), each of which can include a plurality of memory blocks 152 to 156, each of the memory blocks 152 to 156 can include a plurality of pages, and each page can include a plurality of memory cells coupled to a word line. In an embodiment, the memory device 150 can be a flash memory having a three-dimensional (3D) stacked structure.

[0057] The controller 130 can control the memory device 150 in response to a request from the host 102. More specifically, the controller can control read operations, write operations (also referred to as program operations), and erase operations of the memory device 150. For example, the controller 130 can provide data read from the memory device 150 to the host 102, and store data provided by the host 102 into the memory device 150.

[0058] The controller 130 can include a host interface (I / F) unit 132, a processor 134, an error correction code (ECC) unit 138, a power management unit (PMU) 140, a NAND flash controller (NFC) 142, and a memory 144, all of which are operably coupled by an internal bus.

[0059] The host interface unit 132 can be configured to process commands and data of the host 102, and can communicate with the host 102 through one or more of various interface protocols such as universal serial bus (USB), multimedia card (MMC), peripheral component interconnect express (PCI-E), small computer system interface (SCSI), serial attached SCSI (SAS), serial advanced technology attachment (SATA), parallel advanced technology attachment (PATA), enhanced small disk interface (ESDI), and electronic integrated drive (IDE).

[0060] The ECC unit 138 can detect and correct errors included in data read from the memory device 150. In other words, the ECC unit 138 can perform an error correction decoding process on data read from the memory device 150 by using an ECC code used during an ECC encoding process. According to a result of the error correction decoding process, the ECC unit 138 can output a signal, for example, an error correction success / failure signal. When the number of error bits is greater than a threshold value of correctable error bits, the ECC unit 138 does not correct the error bits, and can output an error correction failure signal.

[0061] The ECC unit 138 can perform error correction by encoding modulation such as low density parity check (LDPC) code, Bose-Chaudhuri-Hocquenghem (BCH) code, turbo code, Reed-Solomon (RS) code, convolutional code, recursive systematic code (RSC), trellis coded modulation (TCM), and block coded modulation (BCM). However, the ECC unit 138 is not limited thereto. The ECC unit 138 can include all circuits, modules, systems, or devices for error correction.

[0062] The PMU 140 can provide and manage power of the controller 130.

[0063] The NFC 142 can function as a memory / storage interface for interfacing the controller 130 and the memory device 150 such that the controller 130 controls the memory device 150 in response to a request from the host 102. When the memory device 150 is a flash memory or specifically a NAND flash memory, the NFC 142 can generate control signals for the memory device 150 and process data to be provided to the memory device 150 under the control of the processor 134. The NFC 142 can function as an interface (e.g., a NAND flash interface) that processes commands and data between the controller 130 and the memory device 150. Specifically, the NFC 142 can support data transmission between the controller 130 and the memory device 150.

[0064] The memory 144 can function as a working memory of the memory system 110 and the controller 130 and store data for driving the memory system 110 and the controller 130. The controller 130 can control the memory device 150 to perform a read operation, a write operation, a program operation, and an erase operation in response to a request from the host 102. The controller 130 can provide data read from the memory device 150 to the host 102 and can store data provided from the host 102 into the memory device 150. The memory 144 can store data required for the controller 130 and the memory device 150 to perform these operations.

[0065] The memory 144 can be implemented by a volatile memory. For example, the memory 144 can be implemented by a static random access memory (SRAM) or a dynamic random access memory (DRAM). The memory 144 can be disposed inside or outside the controller 130. Figure 1 The memory 144 disposed inside the controller 130 is illustrated. In an embodiment, the memory 144 can be implemented by an external volatile memory having a memory interface that transmits data between the memory 144 and the controller 130.

[0066] The processor 134 can control overall operations of the memory system 110. The processor 134 can drive firmware to control overall operations of the memory system 110. The firmware can be referred to as a flash translation layer (FTL).

[0067] The processor 134 of the controller 130 can include a management unit (not shown) for performing a bad block management operation of the memory device 150. The management unit can perform a bad block management operation of checking bad blocks in which a program failure occurs during a program operation due to a characteristic of a NAND flash memory among a plurality of memory blocks 152 to 156 included in the memory device 150. The management unit can write program failure data of the bad blocks to a new memory block. In the memory device 150 having a 3D stacked structure, the bad block management operation can reduce the use efficiency of the memory device 150 and the reliability of the memory system 110. Accordingly, there is a need for more reliably performing a bad block management operation.

[0068] Figure 2 is a schematic diagram illustrating the memory device 150.

[0069] Referring to Figure 2 The memory device 150 can include a plurality of memory blocks 0 to N-1, and each of the blocks 0 to N-1 can include a plurality of pages, for example, 2 M The number of pages can vary according to circuit design. The memory cells included in each of the memory blocks 0 to N-1 can be single layer cells (SLC) storing 1-bit data and / or multi layer cells (MLC) storing 2-bit or more data. Accordingly, the memory device 150 can include SLC memory blocks or MLC memory blocks according to the number of bits that can be represented or stored in each of the memory cells in the memory blocks. The SLC memory blocks can include a plurality of pages implemented by memory cells each storing 1-bit data, and can generally have high data calculation performance and high durability. The MLC memory blocks can include a plurality of pages implemented by memory cells each storing a plurality of bits (e.g., 2-bit or more) of data, and can generally have a larger data storage space, i.e., a higher integration density, than the SLC memory blocks. In an embodiment, the memory device 150 can include a plurality of triple layer cell (TLC) memory blocks. In another embodiment, the memory device 150 can include a plurality of quad layer cell (QLC) memory blocks. The TLC memory blocks can include a plurality of pages implemented by memory cells each storing 3-bit data, and the QLC memory blocks can include a plurality of pages implemented by memory cells each storing 4-bit data.

[0070] Figure 3 is a circuit diagram illustrating an exemplary configuration of a memory cell array of a memory block in the memory device 150.

[0071] Referring to Figure 3A memory block 330, which can correspond to any one of a plurality of memory blocks 152 to 156 included in the memory device 150 of the memory system 110, can include a plurality of cell strings 340 coupled to a plurality of respective bit lines BL0 to BLm-1. The cell strings 340 of each column can include one or more drain select transistors DST and one or more source select transistors SST. A plurality of memory cells MC0 to MCn-1 can be coupled in series between the drain select transistor DST and the source select transistor SST. In an embodiment, each of the memory cell transistors MC0 to MCn-1 can be implemented by an MLC capable of storing data information of a plurality of bits. Each of the cell strings 340 can be electrically coupled to a respective bit line of the plurality of bit lines BL0 to BLm-1. For example, as shown in FIG. 3, a first cell string is coupled to a first bit line BL0 and a last cell string is coupled to a last bit line BLm-1. Figure 3

[0072] Although Figure 3 NAND flash memory cells are shown, the present application is not limited thereto. It is noted that the memory cells can be NOR flash memory cells or hybrid flash memory cells including two or more kinds of memory cells combined therein. In addition, it is noted that the memory device 150 can be a flash memory device including a conductive floating gate as a charge storage layer, or a charge-trapping flash (CTF) memory device including an insulating layer as a charge storage layer.

[0073] The memory device 150 can further include a voltage supply unit 310 that provides word line voltages including a program voltage, a read voltage, and a pass voltage to be supplied to word lines according to an operation mode. The voltage generation operation of the voltage supply unit 310 can be controlled by a control circuit (not shown). Under the control of the control circuit, the voltage supply unit 310 can select one of memory blocks (or sectors) of a memory cell array, select one of word lines of the selected memory block, and provide the word line voltage to the selected word line and the unselected word line as necessary.

[0074] ​The memory device 150 can include a read / write circuit 320 controlled by the control circuit. During a verify / normal read operation, the read / write circuit 320 can function as a sense amplifier for reading data from the memory cell array. During a program operation, the read / write circuit 320 can function as a write driver for driving a bit line in accordance with data to be stored in the memory cell array. During the program operation, the read / write circuit 320 can receive data to be stored in the memory cell array from a buffer (not shown) and drive a bit line in accordance with the received data. The read / write circuit 320 can include a plurality of page buffers 322 through 326 corresponding to columns (or bit lines) or column pairs (or bit line pairs), respectively, and each of the page buffers 322 through 326 can include a plurality of latches (not shown).

[0075] The memory device 150 can be implemented by a 2D or 3D memory device. Figure 4 is a schematic diagram illustrating an exemplary 3D structure of the memory device 150.

[0076] Specifically, as Figure 4 illustrated, the memory device 150 can be implemented by a non-volatile memory device having a 3D stacked structure. When the memory device 150 has a 3D structure, the memory device 150 can include a plurality of memory blocks BLK0 through BLKN-1 each having a 3D structure (or a vertical structure).

[0077] Figure 5 is a block diagram illustrating a memory system according to a first embodiment of the present application.

[0078] Figure 6 is a block diagram illustrating Figure 5 a NAND flash control unit (NFC) 142 illustrated in FIG. 1.

[0079] Referring to Figure 5 , the memory system 110 can include a first memory device NAND1<1:4> and a second memory device NAND2<1:4> corresponding to the memory device 150 of Figure 1 .

[0080] The first memory device NAND1<1:4> can be coupled to a first channel CH1 and include a plurality of first memory blocks (not shown), and the second memory device NAND2<1:4> can be coupled to a second channel CH2 and include a plurality of second memory blocks (not shown). For convenience of description, in the first embodiment of the present application, the memory blocks included in the first memory device NAND1<1:4> can be referred to as first memory blocks, and the memory blocks included in the second memory device NAND2<1:4> can be referred to as second memory blocks.

[0081] AsFigure 5 As shown, the controller 130 can include a processor 134, a memory unit 144, and a NAND flash control unit 142.

[0082] Here, the processor 134 can control the general operation of the memory system 110 as described above. Figure 1 Specifically, as shown in Figure 5 and Figure 6 , the processor 134 can include an address converter 1342 that converts a logical address LA of a first storage block included in each of the first memory devices NAND1<1:4> to a first physical address and outputs the first physical address PA1, and converts a logical address LA of a second storage block included in each of the second memory devices NAND2<1:4> to a second physical address and outputs the second physical address PA2.

[0083] Further, the NAND flash control unit 142 can be a constituent element for controlling the operation of the memory devices NAND1<1:4> and NAND2<1:4>, and the NAND flash control unit 142 is also described in Figure 1 Specifically, as shown in Figure 5 , the NFC 142 can include a first channel controller 1421 for controlling access to the first memory devices NAND1<1:4>, a second channel controller 1422 for controlling access to the second memory devices NAND2<1:4>, and a bad block controller 500 for integrating and managing bad storage blocks included in the first memory devices NAND1<1:4> and the second memory devices NAND2<1:4>.

[0084] Further, as described with reference to Figure 1 , the memory unit 144 is a constituent element for storing data required for the operation of the memory system 110. Specifically, the memory unit 144 is used to buffer data (i.e., temporarily store data) in the operation of the processor 134 and the NFC 142.

[0085] Here, it is shown in Figure 5 that the host interface (I / F) unit 132, the error correction code (ECC) unit 138, and the power management unit 140 are not included in the controller 130, and in Figure 1 , the host interface unit 132, the ECC unit 138, and the power management unit 140 are shown as being included in the controller 130. However, this is for ease of description, and in fact, Figure 5 the host interface unit 132, the ECC unit 138, and the power management unit 140 of the memory system 110 can be included in the controller 130.

[0086] With reference to Figure 6According to an exemplary embodiment, a bad block controller 500 included in the NAND flash control unit 142 is detailed.

[0087] The bad block controller 500 can select one between the first channel controller 1421 and the second channel controller 1422 based on a comparison result obtained by comparing the bad physical address BAD_PA1 and the bad physical address BAD_PA2 corresponding to the bad blocks included in the first memory device NAND1<1:4> and the second memory device NAND2<1:4> with the first physical address PA1 and the second physical address PA2 output from the address converter 1342. The bad block controller 500 can transfer the first physical address PA1 and the second physical address PA2 to one of the replacement physical address SUB_PA1 and the replacement physical address SUB_PA2 to the selected channel controller. The replacement physical address SUB_PA1 and the replacement physical address SUB_PA2 can correspond to the bad physical address BAD_PA1 and the bad physical address BAD_PA2, respectively.

[0088] The bad block controller 500 can include a first bad block table 501, a second bad block table 502, and a path control element 520.

[0089] The first bad block table 501 can include a mapping relationship between the bad physical address BAD_PA1 and the first replacement physical address SUB_PA1. The second bad block table 502 can include a mapping relationship between the bad physical address BAD_PA2 and the second replacement physical address SUB_PA2. The first replacement physical address SUB_PA1 and the second replacement physical address SUB_PA2 can correspond to the storage blocks of the first channel CH1 and the second channel CH2, respectively. That is, the first replacement physical address SUB_PA1 can correspond to the first storage block, and the second replacement physical address SUB_PA2 can correspond to the second storage block. However, the bad physical address BAD_PA1 can correspond to the first storage block or the second storage block, and the bad physical address BAD_PA2 can correspond to the first storage block or the second storage block.

[0090] When the first physical address PA1 and the second physical address PA2 are the same as the bad physical address BAD_PA1, the path control element 520 can output the first replacement physical address SUB_PA1 to the first channel controller 1421. When the first physical address PA1 and the second physical address PA2 are the same as the bad physical address BAD_PA2, the path control element 520 can output the second replacement physical address SUB_PA2 to the second channel controller 1422.

[0091] When the first physical address PA1 is different from the bad physical address BAD_PA1 and the bad physical address BAD_PA2, the path control element 520 can output the first physical address PA1 to the first channel controller 1421. When the second physical address PA2 is different from the bad physical address BAD_PA1 and the bad physical address BAD_PA2, the path control element 520 can output the second physical address PA2 to the second channel controller 1422.

[0092] Here, the path control element 520 can include a first specific path control element 521 and a second specific path control element 522.

[0093] When the first physical address PA1 is the same as any bad physical address BAD_PA1, the first specific path control element 521 can output the first substitute physical address SUB_PA1 to the first channel controller 1421. When the first physical address PA1 is different from any bad physical address BAD_PA1 and the bad physical address BAD_PA2, the first specific path control element 521 can output the first physical address PA1 to the first channel controller 1421. When the first physical address PA1 is the same as any bad physical address BAD_PA2, the first specific path control element 521 can output the second substitute physical address SUB_PA2 to the second channel controller 1422.

[0094] When the second physical address PA2 is the same as any bad physical address BAD_PA2, the second specific path control element 522 can output the second substitute physical address SUB_PA2 to the second channel controller 1422. When the second physical address PA2 is different from the bad physical address BAD_PA1 and the bad physical address BAD_PA2, the second specific path control element 522 can output the second physical address PA2 to the second channel controller 1422. When the second physical address PA2 is the same as any bad physical address BAD_PA1, the second specific path control element 522 can output the first substitute physical address SUB_PA1 to the first channel controller 1421.

[0095] The bad block controller 500 can further include a bad information loading element 540. The bad information loading element 540 can receive loading information of first and second bad block physical addresses CH_BPA1 and CH_BPA2 and substitute physical addresses SUB_PA1 and SUB_PA2 from the first memory device NAND1<1:4> and the second memory device NAND2<1:4>. The first and second bad block physical addresses CH_BPA1 and CH_BPA2 can correspond to the first and second memory blocks, respectively. The bad information loading element 540 can generate first and second bad block tables 501 and 502 for the first and second substitute physical addresses SUB_PA1 and SUB_PA2. The first bad block table 501 can correspond to the first substitute physical address SUB_PA1, and the second bad block table 502 can correspond to the second substitute physical address SUB_PA2. However, the first and second bad block physical addresses CH_BPA1 and CH_BPA2 need not correspond to the first and second bad block tables 501 and 502, respectively. The bad information loading element 540 can select bad physical addresses BAD_PA1 and BAD_PA2 from the first and second bad block physical addresses CH_BPA1 and CH_BPA2 such that the bad physical addresses BAD_PA1 and BAD_PA2 correspond to the first and second bad block tables 501 and 502, respectively. The bad information loading element 540 can select the bad physical addresses BAD_PA1 and BAD_PA2 from the first and second bad block physical addresses CH_BPA1 and CH_BPA2 according to the number of the first and second substitute physical addresses SUB_PA1 and SUB_PA2.

[0096] Meanwhile, the address converter 1342 can perform a logical-to-physical address conversion operation in response to a logical address LA applied from the host 102, and output first and second physical addresses PA1 and PA2. Here, the address converter 1342 can convert the logical address LA into the first and second physical addresses PA1 and PA2 by referring to logical-to-physical mapping information (not shown) stored in the memory unit 144. It is assumed that the first and second physical addresses PA1 and PA2 indicate the first and second memory blocks, respectively.

[0097] The first and second bad block tables 501 and 502 included in the bad block controller 500 can be stored in a specific storage space of the bad block controller 500, as shown in Figure 6 or in the memory unit 144 included in the controller 130. If the first and second bad block tables 501 and 502 included in the bad block controller 500 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controller 130, and it is assumed that the first and second bad block tables 501 and 502 are stored in the memory unit 144 included in the controllerFigure 6 The different configurations shown, then, each time the first bad block table 501 and the second bad block table 502 are accessed, the bad block controller 500 can read and use the values from the memory unit 144.

[0098] The first bad block physical addresses CH_BPA1 and the second bad block physical addresses CH_BPA2 can be obtained through testing performed during manufacturing of the first memory device NAND1<1:4> and the second memory device NAND2<1:4> or during operation of the first memory device NAND1<1:4> and the second memory device NAND2<1:4>.

[0099] In embodiments, an integrated bad block table including both the first bad block table 501 and the second bad block table 502 can be employed instead of separate first bad block table 501 and second bad block table 502.

[0100] The selection of the first substitute memory block and the second substitute memory block corresponding to the first substitute physical address SUB_PA1 and the second substitute physical address SUB_PA2, respectively, can vary according to circuit design.

[0101] Figure 6 Exemplarily shown are six physical address values 1<1>_700, 1<4>_800, 1<3>_900, 1<2>_400, 1<1>_950, and 1<2>_750 corresponding to the first bad block physical addresses CH_BPA1 of bad blocks included in the first memory device NAND1<1:4>, and two physical address values 2<1>_350 and 2<2>_550 corresponding to the second bad block physical addresses CH_BPA2 of bad blocks included in the second memory device NAND2<1:4>. Further, Figure 6 Exemplarily shown are four physical address values 1<1>_900, 1<2>_830, 1<3>_520, and 1<3>_620 corresponding to the first substitute physical addresses SUB_PA1 of substitute memory blocks included in the first memory device NAND1<1:4>, and four physical address values 2<1>_700, 2<2>_530, 2<3>_820, and 2<4>_480 corresponding to the second substitute physical addresses SUB_PA2 of substitute memory blocks included in the second memory device NAND2<1:4>.

[0102] The bad information loading element 540 can select 4 physical address values of the first bad block physical address CH_BPA1 as the bad physical address BAD_PA1 according to 4 values corresponding to the first substitute physical address SUB_PA1 of the first bad block table 501. The bad information loading element 540 can select the remaining 2 physical address values of the first bad block physical address CH_BPA1 and 2 physical address values of the second bad block physical address CH_BPA2 as the bad physical address BAD_PA2 according to 4 values corresponding to the second substitute physical address SUB_PA2 of the second bad block table 502.

[0103] For example, when the first physical address PA1 has a value of "1<2>_400", the first specific path control element 521 can compare the value "1<2>_400" of the first physical address PA1 with values of the bad physical address BAD_PA1 of the first bad block table 501 and the bad physical address BAD_PA2 of the second bad block table 502.

[0104] When the value "1<2>_400" of the first physical address PA1 is the same as the value "1<2>_400" of the bad physical address BAD_PA1 of the first bad block table 501, the first specific path control element 521 can output the value "1<3>_620" of the first substitute physical address SUB_PA1 mapped to the value "1<2>_400" of the bad physical address BAD_PA1 in the first bad block table 501 to the first channel controller 1421. In this way, when the value of the first physical address PA1 indicates one among the bad blocks included in the first storage block, one among the substitute storage blocks included in the first storage block can be used.

[0105] For another example, when the first physical address PA1 has a value of "1<2>_750", the first specific path control element 521 can compare the value "1<2>_750" of the first physical address PA1 with values of the bad physical address BAD_PA1 of the first bad block table 501 and the bad physical address BAD_PA2 of the second bad block table 502.

[0106] When the value "1<2>_750" of the first physical address PA1 is the same as the value "1<2>_750" of the bad physical address BAD_PA2 of the second bad block table 502, the first specific path control element 521 can output the value "2<2>_530" of the second substitute physical address SUB_PA2 mapped to the value "1<2>_750" of the bad physical address BAD_PA2 in the second bad block table 502 to the second channel controller 1422.

[0107] For another example, when the first physical address PA1 has a value of "1<1>_600", because the value of the first physical address PA1 is different from any one of the bad physical addresses BAD_PA1 of the first bad block table 501 and the bad physical addresses BAD_PA2 of the second bad block table 502, the first specific path control element 521 can output the value "1<1>_600" of the first physical address PA1 to the first channel controller 1421.

[0108] According to the first embodiment of the present application described above, the memory system including a plurality of memory devices is coupled to different channels, and even if the memory devices are coupled to different channels, the bad memory blocks included in each of the memory devices can be integrated and managed together.

[0109] In some embodiments, each channel can be divided into a plurality of lanes. In this case, similar schemes can be applied to the plurality of lanes as described with reference to Figure 5 and Figure 6 . That is, in each channel, the plurality of lanes can be considered as a channel as described with reference to Figure 5 and Figure 6 .

[0110] The plurality of lane controllers can respectively control the plurality of lanes included in each channel. The channel controller can distribute an address signal to the plurality of lane controllers of each channel.

[0111] In the following embodiments of the present application, the memory system can use, for a bad memory block, a replacement memory block coupled to a lane different from the lane coupled to the bad memory block. However, in the following embodiments of the present application, the memory system can not use, for a bad memory block, a replacement memory block coupled to a channel different from the channel coupled to the bad memory block. That is, the memory system can use, for a bad memory block, a replacement memory block in the same channel.

[0112] Figure 7 is a block diagram illustrating a memory system according to a second embodiment of the present application.

[0113] Figure 8 is a block diagram illustrating an exemplary configuration of a NAND flash control unit (NFC) 142 shown in Figure 7 .

[0114] Referring to Figure 7 , the memory system 110 can include a plurality of memory devices NAND1<1:4> to NAND4<1:4> respectively corresponding to Figure 1 the memory devices 150.

[0115] The memory devices NAND1<1:4> to NAND4<1:4> can include a plurality of first memory devices NAND1<1:4> coupled to a first way WAY1 of the first channel CH1 and including a plurality of first memory blocks (not shown), a plurality of second memory devices NAND2<1:4> coupled to a second way WAY2 of the first channel CH1 and including a plurality of second memory blocks (not shown), a plurality of third memory devices NAND3<1:4> coupled to a first way WAY3 of the second channel CH2 and including a plurality of third memory blocks (not shown), and a plurality of fourth memory devices NAND4<1:4> coupled to a second way WAY4 of the second channel CH2 and including a plurality of fourth memory blocks (not shown).

[0116] Here, Figure 7 The first memory device NAND1<1:4> coupled to the first way WAY1 of the first channel CH1, the second memory device NAND2<1:4> coupled to the second way WAY2 of the first channel CH1, the third memory device NAND3<1:4> coupled to the first way WAY3 of the second channel CH2, and the fourth memory device NAND4<1:4> coupled to the second way WAY4 of the second channel CH2 are shown as the memory devices NAND1<1:4> to NAND4<1:4>. However, this is merely an exemplary embodiment of the present application, and actually more ways, more channels, and more memory devices coupled to the ways of the channels, respectively, can be adapted to the memory devices. Further, in the drawings, the first memory device NAND1<1:4> includes four memory devices NAND1<1:4>, the second memory device NAND2<1:4> includes four memory devices NAND2<1:4>, the third memory device NAND3<1:4> includes four memory devices NAND3<1:4>, and the fourth memory device NAND4<1:4> includes four memory devices NAND4<1:4>. This is merely proposed for convenience of explanation, and the first memory device NAND1<1:4> can include more or less than four memory devices, and the second memory device NAND2<1:4> can also include more or less than four memory devices. Further, the third memory device NAND3<1:4> can include more or less than four memory devices, and the fourth memory device NAND4<1:4> can also include more or less than four memory devices. Further, although not directly shown in FIG. 1, as Figure 7 Figure 1 ​As shown, each of the first memory device NAND1<1:4>, the second memory device NAND2<1:4>, the third memory device NAND3<1:4>, and the fourth memory device NAND4<1:4> can include a plurality of memory blocks. For ease of description, in the second embodiment of the present application, the memory blocks included in each of the first memory device NAND1<1:4> can be referred to as first memory blocks, the memory blocks included in each of the second memory device NAND2<1:4> can be referred to as second memory blocks, the memory blocks included in each of the third memory device NAND3<1:4> can be referred to as third memory blocks, and the memory blocks included in each of the fourth memory device NAND4<1:4> can be referred to as fourth memory blocks.

[0117] As shown in FIG. 1, the processor 134 can include an address converter 1342 that converts the logical address LA of the first memory blocks into physical addresses and outputs first physical addresses PA1, converts the logical address LA of the second memory blocks into physical addresses and outputs second physical addresses PA2, converts the logical address LA of the third memory blocks included in each of the third memory device NAND3<1:4> into physical addresses and outputs third physical addresses PA3, and converts the logical address LA of the fourth memory blocks included in each of the fourth memory device NAND4<1:4> into physical addresses and outputs fourth physical addresses PA4. Figure 7 Figure 8 As shown in FIG. 1, the processor 134 can include an address converter 1342 that converts the logical address LA of the first memory blocks into physical addresses and outputs first physical addresses PA1, converts the logical address LA of the second memory blocks into physical addresses and outputs second physical addresses PA2, converts the logical address LA of the third memory blocks included in each of the third memory device NAND3<1:4> into physical addresses and outputs third physical addresses PA3, and converts the logical address LA of the fourth memory blocks included in each of the fourth memory device NAND4<1:4> into physical addresses and outputs fourth physical addresses PA4.

[0118] As shown in FIG. 1, the processor 134 can include an address converter 1342 that converts the logical address LA of the first memory blocks into physical addresses and outputs first physical addresses PA1, converts the logical address LA of the second memory blocks into physical addresses and outputs second physical addresses PA2, converts the logical address LA of the third memory blocks included in each of the third memory device NAND3<1:4> into physical addresses and outputs third physical addresses PA3, and converts the logical address LA of the fourth memory blocks included in each of the fourth memory device NAND4<1:4> into physical addresses and outputs fourth physical addresses PA4. Figure 7 As shown in FIG. 1, the NFC 142 can include a first lane controller 1426 to a fourth lane controller 1429, a first channel controller 1421 and a second channel controller 1422, a first bad block controller 700, and a second bad block controller 800.

[0119] The first lane controller 1426 can control access to the first memory device NAND1<1:4>. The second lane controller 1427 can control access to the second memory device NAND2<1:4>. The third lane controller 1428 can control access to the third memory device NAND3<1:4>. The fourth lane controller 1429 can control access to the fourth memory device NAND4<1:4>.

[0120] The first channel controller 1421 can control access to the first lane controller 1426 and the second lane controller 1427. The second channel controller 1422 can control access to the third lane controller 1428 and the fourth lane controller 1429.

[0121] ​The first bad block controller 700 can integrate and manage bad memory blocks included in the first memory device NAND1<1:4> and the second memory device NAND2<1:4>. The second bad block controller 800 can integrate and manage bad memory blocks included in the third memory device NAND3<1:4> and the fourth memory device NAND4<1:4>.

[0122] The memory unit 144 can buffer data during operation of the processor 134 and the NFC 142.

[0123] Here, in Figure 7 the host interface (I / F) unit 132, the error correction code (ECC) unit 138, and the power management unit 140 are not included in the controller 130, whereas in Figure 1 the host interface unit 132, the ECC unit 138, and the power management unit 140 are shown as being included in the controller 130. However, this is for ease of description, and in fact, Figure 7 the host interface unit 132, the ECC unit 138, and the power management unit 140 of the controller 130 can be included in the controller 130.

[0124] Referring to Figure 8 , the first bad block controller 700 and the second bad block controller 800 are shown in detail.

[0125] The first bad block controller 700 can select the first channel controller 1421 and select one between the first lane controller 1426 and the second lane controller 1427 by comparing the first channel bad physical addresses WBAD_PA1 and WBAD_PA2 corresponding to bad blocks included in the first memory device NAND1<1:4> and the second memory device NAND2<1:4> with the first physical address PA1 and the second physical address PA2 output from the address converter 1342, and transmit the first physical address PA1 and the second physical address PA2 to the selected one lane controller 1426 or 1427 among the replacement physical addresses WSUB_PA1 and WSUB_PA2 corresponding to the first channel bad physical addresses WBAD_PA1 and WBAD_PA2.

[0126] Further, the second bad block controller 800 can select one between the third path controller 1428 and the fourth path controller 1429 by comparing the second channel bad physical addresses WBAD_PA3 and WBAD_PA4 corresponding to the bad blocks included in the third memory device NAND3<1:4> and the fourth memory device NAND4<1:4> with the third physical address PA3 and the fourth physical address PA4 output from the address converter 1342, and transfer the third physical address PA3 and the fourth physical address PA4 to the selected one path controller 1428 or 1429 with one of the substitute physical addresses WSUB_PA3 and WSUB_PA4 corresponding to the second channel bad physical addresses WBAD_PA3 and WBAD_PA4.

[0127] The first bad block controller 700 can include a first bad block table 701, a second bad block table 702, and a first path control element 720.

[0128] The first bad block table 701 can map a predetermined first bad physical address WBAD_PA1 to a first substitute physical address WSUB_PA1 corresponding to a first storage block.

[0129] The second bad block table 702 can map a predetermined second bad physical address WBAD_PA2 to a second substitute physical address WSUB_PA2 corresponding to a second storage block.

[0130] The first path control element 720 can select the first channel controller 1421 and the first path controller 1426 and transfer the first substitute physical address WSUB_PA1 when the first physical address PA1 and the second physical address PA2 are included in the first bad physical address WBAD_PA1, select the first channel controller 1421 and the second path controller 1427 and transfer the second substitute physical address WSUB_PA2 when the first physical address PA1 and the second physical address PA2 are included in the remaining second bad physical address WBAD_PA2, and select the first channel controller 1421 and the first path controller 1426 and transfer the first physical address PA1 or select the first channel controller 1421 and the second path controller 1427 and transfer the second physical address PA2 when the first physical address PA1 and the second physical address PA2 are not included in the bad physical addresses WBAD_PA1 and WBAD_PA2 of the first channel.

[0131] Further, the second bad block controller 800 can include a third bad block table 803, a fourth bad block table 804, and a second path control element 820.

[0132] The third bad block table 803 can map a predetermined third bad physical address WBAD_PA3 to a third substitute physical address WSUB_PA3 corresponding to a third storage block.

[0133] The fourth bad block table 804 can map a predetermined fourth bad physical address WBAD_PA4 to a fourth substitute physical address WSUB_PA4 corresponding to a fourth storage block.

[0134] The second path control element 820 can select the second channel controller 1422 and the third path controller 1428 and transfer the third substitute physical address WSUB_PA3 when the third physical address PA3 and the fourth physical address PA4 are included in the third bad physical address WBAD_PA3, select the second channel controller 1422 and the fourth path controller 1429 and transfer the fourth substitute physical address WSUB_PA4 when the third physical address PA3 and the fourth physical address PA4 are included in the fourth bad physical address WBAD_PA4, and select the second channel controller 1422 and the third path controller 1428 and transfer the third physical address PA3 or select the second channel controller 1422 and the fourth path controller 1429 and transfer the fourth physical address PA4 when the third physical address PA3 and the fourth physical address PA4 are not included in the bad physical addresses WBAD_PA3 and WBAD_PA4 of the second channel.

[0135] Here, the first path control element 720 can include a first specific path control element 721 and a second specific path control element 722.

[0136] The first specific path control element 721 can select the first channel controller 1421 and the first path controller 1426 and transfer the first substitute physical address WSUB_PA1 when the first physical address PA1 is included in the first bad physical address WBAD_PA1, select the first channel controller 1421 and the second path controller 1427 and transfer the second substitute physical address WSUB_PA2 when the first physical address PA1 is included in the second bad physical address WBAD_PA2, and select the first channel controller 1421 and the first path controller 1426 and transfer the first physical address PA1 when the first physical address PA1 is not included in the bad physical addresses WBAD_PA1 and WBAD_PA2 of the first channel.

[0137] The second specific path control element 722 can select the first channel controller 1421 and the second path controller 1427 and transmit the second substitute physical address WSUB_PA2 when the second physical address PA2 is included in the second bad physical addresses WBAD_PA2, select the first channel controller 1421 and the first path controller 1426 and transmit the first substitute physical address WSUB_PA1 when the second physical address PA2 is included in the first bad physical addresses WBAD_PA1, and select the first channel controller 1421 and the second path controller 1427 and transmit the second physical address PA2 when the second physical address PA2 is not included in the bad physical addresses WBAD_PA1 and WBAD_PA2 of the first channel.

[0138] Further, the second path control element 820 can include a third specific path control element 821 and a fourth specific path control element 822.

[0139] The third specific path control element 821 can select the second channel controller 1422 and the third path controller 1428 and transmit the third substitute physical address WSUB_PA3 when the third physical address PA3 is included in the third bad physical addresses WBAD_PA3, select the second channel controller 1422 and the fourth path controller 1429 and transmit the fourth substitute physical address WSUB_PA4 when the third physical address PA3 is included in the fourth bad physical addresses WBAD_PA4, and select the second channel controller 1422 and the third path controller 1428 and transmit the third physical address PA3 when the third physical address PA3 is not included in the bad physical addresses WBAD_PA3 and WBAD_PA4 of the second channel.

[0140] The fourth specific path control element 822 can select the second channel controller 1422 and the fourth path controller 1429 and transmit the fourth substitute physical address WSUB_PA4 when the fourth physical address PA4 is included in the fourth bad physical addresses WBAD_PA4, select the second channel controller 1422 and the third path controller 1428 and transmit the third substitute physical address WSUB_PA3 when the fourth physical address PA4 is included in the third bad physical addresses WBAD_PA3, and select the second channel controller 1422 and the fourth path controller 1429 and transmit the fourth physical address PA4 when the fourth physical address PA4 is not included in the bad physical addresses WBAD_PA3 and WBAD_PA4 of the second channel.

[0141] The first bad block controller 700 can further include a first bad information loading element 740 that can load information of the bad block physical addresses WBPA<1:2> stored in the first memory device NAND1<1:4> and the second memory device NAND2<1:4> and the first substitute physical addresses WSUB_PA1 and the second substitute physical addresses WSUB_PA2, decide which of the first substitute physical addresses WSUB_PA1 and the second substitute physical addresses WSUB_PA2 are to be mapped to the bad block physical addresses WBPA<1:2> based on the number of the loaded bad block physical addresses WBPA<1:2>, and generate the first bad block table 701 and the second bad block table 702.

[0142] Here, the first bad information loading element 740 can generate the first bad block table 701 including the first bad physical addresses WBAD_PA1 and the second bad block table 702 including the second bad physical addresses WBAD_PA2 by checking the total number of the bad block physical addresses WBPA<1:2> stored in the first memory device NAND1<1:4> and the second memory device NAND2<1:4> and allocating the bad block physical addresses WBPA<1:2> in such a manner that the number of the first bad physical addresses WBAD_PA1 and the number of the second bad physical addresses WBAD_PA2 do not exceed a predetermined difference.

[0143] The second bad block controller 800 can further include a second bad information loading element 840 that can load information of the bad block physical addresses WBPA<3:4> stored in the third memory device NAND3<1:4> and the fourth memory device NAND4<1:4> and the third substitute physical addresses WSUB_PA3 and the fourth substitute physical addresses WSUB_PA4, decide which of the third substitute physical addresses WSUB_PA3 and the fourth substitute physical addresses WSUB_PA4 are to be mapped to the bad block physical addresses WBPA<3:4> based on the number of the loaded bad block physical addresses WBPA<3:4>, and generate the third bad block table 803 and the fourth bad block table 804.

[0144] Here, the second bad information loading element 840 can generate the third bad block table 803 including the third bad physical addresses WBAD_PA3 and the fourth bad block table 804 including the fourth bad physical addresses WBAD_PA4 by checking the total number of the bad block physical addresses WBPA<3:4> stored in the third memory device NAND3<1:4> and the fourth memory device NAND4<1:4> and allocating the bad block physical addresses WBPA<3:4> in such a manner that the number of the third bad physical addresses WBAD_PA3 and the number of the fourth bad physical addresses WBAD_PA4 do not exceed a predetermined difference.

[0145] Meanwhile, the address converter 1342 can perform a logical-to-physical address conversion operation in response to a logical address LA applied from the host 102, and output physical addresses PA1 to PA4. Here, the address converter 1342 can convert the logical address LA into the physical addresses PA1 to PA4 by referring to logical-to-physical mapping information (not shown) stored in the memory unit 144. Since the logical-to-physical address conversion is a known technique, it will not be described here again. Also, generally, a physical address capable of indicating a page unit is output through the logical-to-physical address conversion. However, since the embodiment of the present application does not describe a structure using a physical address indicating a page unit, it is assumed that the physical addresses PA1 to PA4 output through the address converter 1342 are physical addresses indicating a storage block. In other words, a first physical address PA1 among the physical addresses PA1 to PA4 output from the address converter 1342 can be information indicating a first storage block (not shown), and a second physical address PA2 can be information indicating a second storage block (not shown). A third physical address PA3 among the physical addresses PA1 to PA4 output from the address converter 1342 can be information indicating a third storage block (not shown) included in each of the third memory devices NAND3<1:4>, and a fourth physical address PA4 can be information indicating a fourth storage block (not shown) included in each of the fourth memory devices NAND4<1:4>.

[0146] The first bad block table 701 and the second bad block table 702 included in the first bad block controller 700 and the third bad block table 803 and the fourth bad block table 804 included in the second bad block controller 800 can be stored in a specific storage space of the first bad block controller 700 and the second bad block controller 800 as shown in Figure 8 If the first bad block table 701 and the second bad block table 702 included in the first bad block controller 700 and the third bad block table 803 and the fourth bad block table 804 included in the second bad block controller 800 are stored in the memory unit 144 included in the controller 130, they are different from Figure 8 as shown in FIG. 7, the first bad block controller 700 and the second bad block controller 800 can read and use values from the memory unit 144 whenever the first bad block table 701, the second bad block table 702, the third bad block table 803, and the fourth bad block table 804 are accessed.

[0147] The bad block physical addresses WBPA<1:4> stored in the first to fourth memory devices NAND1<1:4> to NAND4<1:4> can have predetermined values by tests performed in the process of generating the first to fourth memory devices NAND1<1:4> to NAND4<1:4>. Further, internal bad memory blocks can be detected during the operation of the first to fourth memory devices NAND1<1:4> to NAND4<1:4>, and the values of the bad block physical addresses WBPA<1:4> are decided.

[0148] A first substitute memory block can be selected among the first memory blocks included in the first memory device NAND1<1:4>. Here, there can be some first memory blocks among the first memory blocks whose use is decided as the first substitute memory block. Further, some arbitrary memory blocks among the first memory blocks in an idle state can be selected as the first substitute memory block. Similarly, a second substitute memory block can be selected among the second memory blocks included in the second memory device NAND2<1:4>. Here, there can be some second memory blocks among the second memory blocks whose use is decided as the second substitute memory block. Further, some arbitrary memory blocks among the second memory blocks in an idle state can be selected as the second substitute memory block. A third substitute memory block can be selected among the third memory blocks included in the third memory device NAND3<1:4>. Here, there can be some third memory blocks among the third memory blocks whose use is decided as the third substitute memory block. Further, some arbitrary memory blocks among the third memory blocks in an idle state can be selected as the third substitute memory block. Similarly, a fourth substitute memory block can be selected among the fourth memory blocks included in the fourth memory device NAND4<1:4>. Here, there can be some fourth memory blocks among the fourth memory blocks whose use is decided as the fourth substitute memory block. Further, some arbitrary memory blocks among the fourth memory blocks in an idle state can be selected as the fourth substitute memory block. The method of selecting the first to fourth substitute memory blocks can be selected by the designer, and the physical address value corresponding to the selected first substitute memory block, the physical address value corresponding to the selected second substitute memory block, the physical address value corresponding to the selected third substitute memory block, and the physical address value corresponding to the selected fourth substitute memory block can be used as the first to fourth substitute physical addresses WSUB_PA1, WSUB_PA2, WSUB_PA3, and WSUB_PA4 in the first and second bad information loading elements 740 and 840.

[0149] When the value of the first physical address PA1 indicates one of the bad blocks included in the first storage block, the first bad block controller 700 can allow the use of one of the replacement storage blocks included in the first storage block, or allow the use of one of the replacement storage blocks included in the second storage block. Similarly, when the value of the second physical address PA2 indicates one of the bad blocks included in the second storage block, the first bad block controller 700 can allow the use of one of the replacement storage blocks included in the second storage block, or allow the use of one of the replacement storage blocks included in the first storage block.

[0150] When the value of the third physical address PA3 indicates one of the bad blocks included in the third storage block, the second bad block controller 800 can allow the use of one of the replacement storage blocks included in the third storage block, or allow the use of one of the replacement storage blocks included in the fourth storage block. Similarly, when the value of the fourth physical address PA4 indicates one of the bad blocks included in the fourth storage block, the second bad block controller 800 can allow the use of one of the replacement storage blocks included in the fourth storage block, or allow the use of one of the replacement storage blocks included in the third storage block.

[0151] As described above, it can be seen that the operation of the first bad block controller 700 described above is similar to the operation of the bad block controller 500 described with reference to Figure 6 In addition, it can be seen that the operation of the second bad block controller 800 described above is similar to the operation of the bad block controller 500 described with reference to Figure 6 In short, the bad block controller 500 described with reference to Figure 6 has a structure in which bad storage blocks included in the first and second memory devices NAND1<1:4> and NAND2<1:4> coupled to different channels CH1 and CH2 are integrated and managed together. Here, it can be seen that the structure of the bad block controller 500 described above is similar to the structure of the first bad block controller 700 described with reference to Figure 6 In short, the bad block controller 500 described with reference to Figure 8 has a structure in which bad storage blocks included in the first and second memory devices NAND1<1:4> and NAND2<1:4> coupled to different ways WAY1 and WAY2 are integrated and managed together. Similarly, Figure 6 In short, the bad block controller 500 described with reference to Figure 8 has a structure in which bad storage blocks included in the third and fourth memory devices NAND3<1:4> and NAND4<1:4> coupled to different ways WAY3 and WAY4 are integrated and managed together.

[0152] As described above, according to the second embodiment of the present application, the management of bad memory blocks included in the memory device coupled to different ways can be incorporated in a memory system including a plurality of memory devices coupled to different ways.

[0153] Figure 9 is a block diagram illustrating a memory system according to a third embodiment of the present application.

[0154] Figure 10 is a block diagram illustrating Figure 9 is a block diagram illustrating an exemplary configuration of a NAND flash control unit (NFC) 142.

[0155] Referring to Figure 9 , the memory system 110 can include a plurality of memory devices NAND1<1:4> to NAND4<1:4> respectively corresponding to Figure 1

[0156] The memory devices NAND1<1:4> to NAND4<1:4> can include a plurality of first memory devices NAND1<1:4> coupled to a first way WAY1 of a first channel CH1 and including a plurality of first memory blocks (not shown); a plurality of second memory devices NAND2<1:4> coupled to a second way WAY2 of the first channel CH1 and including a plurality of second memory blocks (not shown); a plurality of third memory devices NAND3<1:4> coupled to a first way WAY3 of a second channel CH2 and including a plurality of third memory blocks (not shown); and a plurality of fourth memory devices NAND4<1:4> coupled to a second way WAY4 of the second channel CH2 and including a plurality of fourth memory blocks (not shown).

[0157] Here, Figure 9 ​The first memory device NAND1<1:4> coupled to the first lane CH1 of the first way WAY1, the second memory device NAND2<1:4> coupled to the second lane CH1 of the first way WAY2, the third memory device NAND3<1:4> coupled to the first lane CH2 of the second way WAY3, and the fourth memory device NAND4<1:4> coupled to the second lane CH2 of the second way WAY4 are shown as the memory devices NAND1<1:4> to NAND4<1:4>. For ease of description, in the second embodiment of the present application, the memory blocks included in each of the first memory devices NAND1<1:4> can be referred to as first memory blocks, the memory blocks included in each of the second memory devices NAND2<1:4> can be referred to as second memory blocks, the memory blocks included in each of the third memory devices NAND3<1:4> can be referred to as third memory blocks, and the memory blocks included in each of the fourth memory devices NAND4<1:4> can be referred to as fourth memory blocks.

[0158] As shown in FIG. 1A, the processor 134 can include an address converter 1342 that converts the logical addresses LA of the first memory blocks to physical addresses and outputs first physical addresses PA1, converts the logical addresses LA of the second memory blocks to physical addresses and outputs second physical addresses PA2, converts the logical addresses LA of the third memory blocks included in each of the third memory devices NAND3<1:4> to physical addresses, and outputs third physical addresses PA3, and converts the logical addresses LA of the fourth memory blocks included in each of the fourth memory devices NAND4<1:4> to physical addresses, and outputs fourth physical addresses PA4. Figure 9 Figure 10 As shown in FIG. 1A, the processor 134 can include an address converter 1342 that converts the logical addresses LA of the first memory blocks to physical addresses and outputs first physical addresses PA1, converts the logical addresses LA of the second memory blocks to physical addresses and outputs second physical addresses PA2, converts the logical addresses LA of the third memory blocks included in each of the third memory devices NAND3<1:4> to physical addresses, and outputs third physical addresses PA3, and converts the logical addresses LA of the fourth memory blocks included in each of the fourth memory devices NAND4<1:4> to physical addresses, and outputs fourth physical addresses PA4.

[0159] As shown in FIG. 1A, the processor 134 can include an address converter 1342 that converts the logical addresses LA of the first memory blocks to physical addresses and outputs first physical addresses PA1, converts the logical addresses LA of the second memory blocks to physical addresses and outputs second physical addresses PA2, converts the logical addresses LA of the third memory blocks included in each of the third memory devices NAND3<1:4> to physical addresses, and outputs third physical addresses PA3, and converts the logical addresses LA of the fourth memory blocks included in each of the fourth memory devices NAND4<1:4> to physical addresses, and outputs fourth physical addresses PA4. Figure 9 As shown in FIG. 1A, the processor 134 can include an address converter 1342 that converts the logical addresses LA of the first memory blocks to physical addresses and outputs first physical addresses PA1, converts the logical addresses LA of the second memory blocks to physical addresses and outputs second physical addresses PA2, converts the logical addresses LA of the third memory blocks included in each of the third memory devices NAND3<1:4> to physical addresses, and outputs third physical addresses PA3, and converts the logical addresses LA of the fourth memory blocks included in each of the fourth memory devices NAND4<1:4> to physical addresses, and outputs fourth physical addresses PA4.

[0160]

[0161] ​​The first channel controller 1421 can control access to the first lane controller 1426 and the second lane controller 1427, and the second channel controller 1422 can control access to the third lane controller 1428 and the fourth lane controller 1429.

[0162] The bad block controller 900 can integrate and manage bad memory blocks included in the first to fourth memory devices NAND1<1:4> to NAND4<1:4>.

[0163] The memory unit 144 can buffer data during operation of the processor 134 and the NFC 142.

[0164] Here, the host interface (I / F) unit 132, the error correction code (ECC) unit 138, and the power management unit 140 are not included in the controller 130, as shown in Figure 9 Figure 1 Here, the host interface unit 132, the ECC unit 138, and the power management unit 140 are shown as being included in the controller 130. However, this is for convenience of description, and in fact, Figure 9 The host interface unit 132, the ECC unit 138, and the power management unit 140 of the controller 130 can be included in the controller 130.

[0165] Referring to Figure 10 , an exemplary configuration of the bad block controller 900 is shown in detail.

[0166] The bad block controller 900 can select one between the first channel controller 1421 and the second channel controller 1422, and then select one of the first to fourth lane controllers 1426 to 1429 related to the selected one between the first channel controller 1421 and the second channel controller 1422 by comparing the bad physical addresses WBAD_PA1, WBAD_PA2, WBAD_PA3, and WBAD_PA4 corresponding to bad blocks included in the first to fourth memory devices NAND1<1:4> to NAND4<1:4> with the first to fourth physical addresses PA1 to PA4 output from the address converter 1342, and transfer the first to fourth physical addresses PA1 to PA4 to one lane controller 1426 or 1427 or 1428 or 1429 among the selected one.

[0167] ​The bad block controller 900 can include first to fourth bad block tables 901, 902, 903, and 904, and a path control element 920.

[0168] The first bad block table 901 can map a predetermined first bad physical address WBAD_PA1 to a first substitute physical address WSUB_PA1 corresponding to a first storage block.

[0169] The second bad block table 902 can map a predetermined second bad physical address WBAD_PA2 to a second substitute physical address WSUB_PA2 corresponding to a second storage block.

[0170] The third bad block table 903 can map a predetermined third bad physical address WBAD_PA3 to a third substitute physical address WSUB_PA3 corresponding to a third storage block.

[0171] The fourth bad block table 904 can map a predetermined fourth bad physical address WBAD_PA4 to a fourth substitute physical address WSUB_PA4 corresponding to a fourth storage block.

[0172] The path control element 920 can select the first channel controller 1421 and the first path controller 1426 and transfer the first substitute physical address WSUB_PA1 when the first to fourth physical addresses PA1 to PA4 are included in the first bad physical address WBAD_PA1, select the first channel controller 1421 and the second path controller 1427 and transfer the second substitute physical address WSUB_PA2 when the first to fourth physical addresses PA1 to PA4 are included in the second bad physical address WBAD_PA2, select the second channel controller 1422 and the third path controller 1428 and transfer the third substitute physical address WSUB_PA3 when the first to fourth physical addresses PA1 to PA4 are included in the third bad physical address WBAD_PA3, select the second channel controller 1422 and the fourth path controller 1429 and transfer the fourth substitute physical address WSUB_PA4 when the first to fourth physical addresses PA1 to PA4 are included in the fourth bad physical address WBAD_PA4, and select the first channel controller 1421 and the first path controller 1426 and transfer the first physical address PA1, or select the first channel controller 1421 and the second path controller 1427 and transfer the second physical address PA2, or select the second channel controller 1422 and the third path controller 1428 and transfer the third physical address PA3, or select the second channel controller 1422 and the fourth path controller 1429 and transfer the fourth physical address PA4 when the first to fourth physical addresses PA1 to PA4 are not included in the bad physical addresses WBAD_PA1, WBAD_PA2, WBAD_PA3, and WBAD_PA4.

[0173] Here, the path control element 920 can include first to fourth specific path control elements 921, 922, 923, and 924.

[0174] The first specific path control element 921 can select the first channel controller 1421 and the first way controller 1426 and transmit the first substitute physical address WSUB_PA1 when the first physical address PA1 is included in the first bad physical address WBAD_PA1, select the first channel controller 1421 and the second way controller 1427 and transmit the second substitute physical address WSUB_PA2 when the first physical address PA1 is included in the second bad physical address WBAD_PA2, select the second channel controller 1422 and the third way controller 1428 and transmit the third substitute physical address WSUB_PA3 when the first physical address PA1 is included in the third bad physical address WBAD_PA3, select the second channel controller 1422 and the fourth way controller 1429 and transmit the fourth substitute physical address WSUB_PA4 when the first physical address PA1 is included in the fourth bad physical address WBAD_PA4, and select the first channel controller 1421 and the first way controller 1426 and transmit the first physical address PA1 when the first physical address PA1 is not included in the bad physical addresses WBAD_PA1, WBAD_PA2, WBAD_PA3, and WBAD_PA4.

[0175] The second specific path control element 922 can select the first channel controller 1421 and the first way controller 1426 and transmit the first substitute physical address WSUB_PA1 when the second physical address PA2 is included in the first bad physical address WBAD_PA1, select the first channel controller 1421 and the second way controller 1427 and transmit the second substitute physical address WSUB_PA2 when the second physical address PA2 is included in the second bad physical address WBAD_PA2, select the second channel controller 1422 and the third way controller 1428 and transmit the third substitute physical address WSUB_PA3 when the second physical address PA2 is included in the third bad physical address WBAD_PA3, select the second channel controller 1422 and the fourth way controller 1429 and transmit the fourth substitute physical address WSUB_PA4 when the second physical address PA2 is included in the fourth bad physical address WBAD_PA4, and select the first channel controller 1421 and the second way controller 1427 and transmit the second physical address PA2 when the second physical address PA2 is not included in the bad physical addresses WBAD_PA1, WBAD_PA2, WBAD_PA3, and WBAD_PA4.

[0176] The third specific path control element 923 can select the first channel controller 1421 and the first lane controller 1426 and transmit the first substitute physical address WSUB_PA1 when the third physical address PA3 is included in the first bad physical address WBAD_PA1, select the first channel controller 1421 and the second lane controller 1427 and transmit the second substitute physical address WSUB_PA2 when the third physical address PA3 is included in the second bad physical address WBAD_PA2, select the second channel controller 1422 and the third lane controller 1428 and transmit the third substitute physical address WSUB_PA3 when the third physical address PA3 is included in the third bad physical address WBAD_PA3, select the second channel controller 1422 and the fourth lane controller 1429 and transmit the fourth substitute physical address WSUB_PA4 when the third physical address PA3 is included in the fourth bad physical address WBAD_PA4, and select the second channel controller 1422 and the third lane controller 1428 and transmit the third physical address PA3 when the third physical address PA3 is not included in the bad physical addresses WBAD_PA1, WBAD_PA2, WBAD_PA3, and WBAD_PA4.

[0177] The fourth specific path control element 924 can select the first channel controller 1421 and the first lane controller 1426 and transmit the first substitute physical address WSUB_PA1 when the fourth physical address PA4 is included in the first bad physical address WBAD_PA1, select the first channel controller 1421 and the second lane controller 1427 and transmit the second substitute physical address WSUB_PA2 when the fourth physical address PA4 is included in the second bad physical address WBAD_PA2, select the second channel controller 1422 and the third lane controller 1428 and transmit the third substitute physical address WSUB_PA3 when the fourth physical address PA4 is included in the third bad physical address WBAD_PA3, select the second channel controller 1422 and the fourth lane controller 1429 and transmit the fourth substitute physical address WSUB_PA4 when the fourth physical address PA4 is included in the fourth bad physical address WBAD_PA4, and select the second channel controller 1422 and the fourth lane controller 1429 and transmit the fourth physical address PA4 when the fourth physical address PA4 is not included in the bad physical addresses WBAD_PA1, WBAD_PA2, WBAD_PA3, and WBAD_PA4.

[0178] The bad block controller 900 can further include a bad information loading element 940 which can load information of the bad block physical addresses WBPA<1:2> and WBPA<3:4> and the first to fourth substitute physical addresses WSUB_PA<1:2> and WSUB_PA<3:4> stored in the first to fourth memory devices NAND1<1:4> to NAND4<1:4>, decide which of the first to fourth substitute physical addresses WSUB_PA<1:2> and WSUB_PA<3:4> are to be mapped to the bad block physical addresses WBPA<1:2> and WBPA<3:4> based on the number of the loaded bad block physical addresses WBPA<1:2> and WBPA<3:4>, and generate the first to fourth bad block tables 901 to 904.

[0179] Here, the bad information loading element 940 can generate the first bad block table 901 including the first bad physical address WBAD_PA1, the second bad block table 902 including the second bad physical address WBAD_PA2, the third bad block table 903 including the third bad physical address WBAD_PA3, and the fourth bad block table 904 including the fourth bad physical address WBAD_PA4 by checking the total number of the bad block physical addresses WBPA<1:2> and WBPA<3:4> stored in the first to fourth memory devices NAND1<1:4> to NAND4<1:4>, and allocating the bad block physical addresses WBPA<1:4> in such a way that the number of the first bad physical addresses WBAD_PA1, the number of the second bad physical addresses WBAD_PA2, the number of the third bad physical addresses WBAD_PA3, and the number of the fourth bad physical addresses WBAD_PA4 do not exceed a predetermined difference number.

[0180] Meanwhile, the address converter 1342 can perform a logical-to-physical address conversion operation in response to a logical address LA applied from the host 102, and output physical addresses PA1 to PA4. Here, the address converter 1342 can convert the logical address LA into the physical addresses PA1 to PA4 by referring to logical-to-physical mapping information (not shown) stored in the memory unit 144. Since the logical-to-physical address conversion is a known technology, it will not be described here again. Also, generally, a physical address capable of indicating a page unit is output through the logical-to-physical address conversion. However, since the embodiment of the present application does not describe a structure using a physical address indicating a page unit, it is assumed that the physical addresses PA1 to PA4 output through the address converter 1342 are physical addresses indicating a storage block. In other words, a first physical address PA1 among the physical addresses PA1 to PA4 output from the address converter 1342 can be information indicating a first storage block (not shown), a second physical address PA2 can be information indicating a second storage block (not shown), and a third physical address PA3 among the physical addresses PA1 to PA4 output from the address converter 1342 can be information indicating a third storage block (not shown) included in each of the third memory devices NAND3<1:4>, and a fourth physical address PA4 can be information indicating a fourth storage block (not shown) included in each of the fourth memory devices NAND4<1:4>.

[0181] The first to fourth bad block tables 901 to 904 included in the bad block controller 900 can be stored in a specific storage space of the bad block controller 900 as shown in Figure 10 or in the memory unit 144 included in the controller 130. If the first to fourth bad block tables 901 to 904 included in the bad block controller 900 are stored in the memory unit 144 included in the controller 130, they are different from Figure 10 the bad block controller 900 can read and use values from the memory unit 144 every time the first to fourth bad block tables 901 to 904 are accessed.

[0182] The bad block physical addresses WBPA<1:4> stored in the first to fourth memory devices NAND1<1:4> to NAND4<1:4> can have predetermined values through testing in the process of generating the first to fourth memory devices NAND1<1:4> to NAND4<1:4>. Also, an internal bad storage block can be detected in the process of operating the first to fourth memory devices NAND1<1:4> to NAND4<1:4>, and the value of the bad block physical address WBPA<1:4> is decided.

[0183] The first substitute memory block can be selected among the first memory blocks included in the first memory device NAND1<1:4>. Here, there can be some first memory blocks among the first memory blocks whose use is decided as the first substitute memory block. Further, some arbitrary memory blocks among the first memory blocks in an idle state can be selected as the first substitute memory block. Similarly, the second substitute memory block can be selected among the second memory blocks included in the second memory device NAND2<1:4>. Here, there can be some second memory blocks among the second memory blocks whose use is decided as the second substitute memory block. Further, some arbitrary memory blocks among the second memory blocks in an idle state can be selected as the second substitute memory block. The third substitute memory block can be selected among the third memory blocks included in the third memory device NAND3<1:4>. Here, there can be some third memory blocks among the third memory blocks whose use is decided as the third substitute memory block. Further, some arbitrary memory blocks among the third memory blocks in an idle state can be selected as the third substitute memory block. Similarly, the fourth substitute memory block can be selected among the fourth memory blocks included in the fourth memory device NAND4<1:4>. Here, there can be some fourth memory blocks among the fourth memory blocks whose use is decided as the fourth substitute memory block. Further, some arbitrary memory blocks among the fourth memory blocks in an idle state can be selected as the fourth substitute memory block. The method of selecting the first substitute memory block, the second substitute memory block, the third substitute memory block, and the fourth substitute memory block can be selected by the designer, and the physical address value corresponding to the selected first substitute memory block, the physical address value corresponding to the selected second substitute memory block, the physical address value corresponding to the selected third substitute memory block, and the physical address value corresponding to the selected fourth substitute memory block can be used as the first substitute physical address WSUB_PA1, the second substitute physical address WSUB_PA2, the third substitute physical address WSUB_PA3, and the fourth substitute physical address WSUB_PA4 in the bad information loading element 940.

[0184] When the value of the first physical address PA1 indicates one of the bad blocks included in the first storage block, the bad block controller 900 can allow use of one of the replacement storage blocks included in the first storage block, or allow use of one of the replacement storage blocks included in the second storage block, or allow use of one of the replacement storage blocks included in the third storage block, or allow use of one of the replacement storage blocks included in the fourth storage block. Similarly, when the value of the second physical address PA2 indicates one of the bad blocks included in the second storage block, the bad block controller 900 can allow use of one of the replacement storage blocks included in the first storage block, or allow use of one of the replacement storage blocks included in the second storage block, or allow use of one of the replacement storage blocks included in the third storage block, or allow use of one of the replacement storage blocks included in the fourth storage block.

[0185] Similarly, when the value of the third physical address PA3 indicates one of the bad blocks included in the third storage block, the bad block controller 900 can allow use of one of the replacement storage blocks included in the first storage block, or allow use of one of the replacement storage blocks included in the second storage block, or allow use of one of the replacement storage blocks included in the third storage block, or allow use of one of the replacement storage blocks included in the fourth storage block.

[0186] Similarly, when the value of the fourth physical address PA4 indicates one of the bad blocks included in the fourth storage block, the bad block controller 900 can allow use of one of the replacement storage blocks included in the first storage block, or allow use of one of the replacement storage blocks included in the second storage block, or allow use of one of the replacement storage blocks included in the third storage block, or allow use of one of the replacement storage blocks included in the fourth storage block.

[0187] In summary, it can be seen that the operation of the above-described bad block controller 900 is similar to the operation of the bad block controller 500 described with reference to Figure 6 Briefly, the bad block controller 500 described with reference to Figure 6 has a structure that integrates and manages bad storage blocks included in the first memory device NAND1<1:4> and the second memory device NAND2<1:4> coupled to different channels CH1 and CH2. Here, it can be seen that the structure of the bad block controller 500 of Figure 6 is similar to the structure of the bad block controller 500 described with reference to Figure 10The described bad block controller 900 is structured such that bad memory blocks in the first memory device NAND1<1:4> to the fourth memory device NAND4<1:4> connected to different channels CH1 and CH2 and different paths WAY1, WAY2, WAY3 and WAY4 are integrated and managed together.

[0188] As described above, according to a third embodiment of the present invention, the management of bad memory blocks included in memory devices connected to different paths can be integrated into a memory system including multiple memory devices connected to different paths.

[0189] Figures 11 to 19 It is shown schematically. Figure 1 A simplified diagram illustrating an application example of a data processing system.

[0190] Figure 11 This is a schematic diagram illustrating another example of a data processing system including a memory system according to this embodiment. Figure 11 A memory card system using the memory system according to this embodiment is illustrated schematically.

[0191] Reference Figure 11 The memory card system 6100 may include a memory controller 6120, a memory device 6130, and a connector 6110.

[0192] More specifically, the memory controller 6120 may be connected to a memory device 6130 implemented using non-volatile memory and configured to access the memory device 6130. For example, the memory controller 6120 may be configured to control read operations, write operations, erase operations, and background operations of the memory device 6130. The memory controller 6120 may be configured to provide an interface between the memory device 6130 and the host and drive firmware for controlling the memory device 6130. That is, the memory controller 6120 may correspond to reference... Figures 1 to 10 The described memory system 110 includes a controller 130, and the memory device 6130 may correspond to the referenced... Figures 1 to 10 The memory device 150 of the memory system 110 described herein.

[0193] Therefore, the memory controller 6120 may include RAM, a processing unit, a host interface, a memory interface, and an error correction unit. The memory controller 6120 may further include... Figure 5 , Figure 7 or Figure 9 The components shown.

[0194] The memory controller 6120 can be connected to, for example, via connector 6110. Figure 1 The host 102 communicates with external devices. For example, as shown in reference... Figure 1The memory controller 6120 can be configured to communicate with external devices through one or more of various communication protocols such as Universal Serial Bus (USB), Multi-Media Card (MMC), embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Express PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Storage (UFS), WI-FI, Bluetooth, and the like. Accordingly, the memory system and the data processing system according to the present embodiment can be applied to wired / wireless electronic devices, or particularly to mobile electronic devices.

[0195] The memory device 6130 can be implemented by a non-volatile memory. For example, the memory device 6130 can be implemented by various non-volatile memory devices such as Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, Phase-Change RAM (PRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and Spin Transfer Torque Magnetic RAM (STT-MRAM). The memory device 6130 can include a plurality of dies as in the memory device 150 of Figure 5 , Figure 7 or Figure 9 .

[0196] The memory controller 6120 and the memory device 6130 can be integrated into a single semiconductor device. For example, the memory controller 6120 and the memory device 6130 can construct a Solid State Disk (SSD) by being integrated into a single semiconductor device. Further, the memory controller 6120 and the memory device 6130 can constitute a memory card such as a PC card (PCMCIA: Personal Computer Memory Card International Association), a Compact Flash (CF) card, a smart media card (e.g., SM and SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, micro- MMC, and eMMC), an SD card (e.g., SD, mini-SD, micro-SD, and SDHC), and Universal Flash Storage (UFS).

[0197] Figure 12 is a diagram schematically showing another example of a data processing system including a memory system according to the present embodiment.

[0198] Referring to Figure 12 , the data processing system 6200 can include a memory device 6230 having one or more non-volatile memories and a memory controller 6220 for controlling the memory device 6230. As shown in Figure 12 , the data processing system 6200 can be applied to a mobile electronic device as in the data processing system 6100 of FIG. 11.Figure 1 The described storage medium includes, for example, a memory card (CF, SD, micro-SD, etc.) or a USB device. The memory device 6230 may correspond to... Figure 1 and Figure 5 The memory device 150 in the illustrated memory system 110, and the memory controller 6220 may correspond to Figure 1 and Figure 5 The controller 130 in the memory system 110 shown.

[0199] The memory controller 6220 can control read, write, or erase operations on the memory device 6230 in response to a request from the host 6210, and the memory controller 6220 may include one or more CPUs 6221, a buffer memory such as RAM 6222, ECC circuitry 6223, a host interface 6224, and a memory interface such as an NVM interface 6225.

[0200] The CPU 6221 controls all operations on the memory device 6230, such as read operations, write operations, file system management, and bad page management. The RAM 6222 operates under the control of the CPU 6221 and can be used as working memory, buffer memory, or cache memory. When used as working memory, data processed by the CPU 6221 can be temporarily stored in the RAM 6222. When used as buffer memory, the RAM 6222 can buffer data transferred from the host 6210 to the memory device 6230 or vice versa. When used as cache memory, the RAM 6222 can assist the low-speed memory device 6230 in operating at high speed.

[0201] ECC circuit 6223 can correspond to Figure 1 The controller 130 shown has an ECC unit 138. (See reference...) Figure 1 The ECC circuit 6223 can generate ECC (Error Correction Code) for correcting faulty or invalid bits in data provided from the memory device 6230. The ECC circuit 6223 can perform error correction encoding on the data provided to the memory device 6230, thereby forming data with parity bits. The parity bits can be stored in the memory device 6230. The ECC circuit 6223 can also perform error correction decoding on the data output from the memory device 6230. In this case, the ECC circuit 6223 can use the parity bits to correct errors. For example, as shown in the reference... Figure 1 The ECC circuit 6223 can use LDPC codes, BCH codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, RSC, or coding modulation such as TCM or BCM to correct errors.

[0202] The memory controller 6220 can transmit / receive data to / from the host 6210 through a host interface 6224 and transmit / receive data to / from the memory device 6230 through an NVM interface 6225. The host interface 6224 can be connected to the host 6210 through a PATA bus, a SATA bus, SCSI, USB, PCIe, or a NAND interface. The memory controller 6220 can have a wireless communication function using a mobile communication protocol such as WiFi or Long Term Evolution (LTE). The memory controller 6220 can be connected to an external device, for example, the host 6210 or another external device, and then transmit / receive data to / from the external device. In particular, since the memory controller 6220 is configured to communicate with an external device through one or more of various communication protocols, the memory system and the data processing system according to the present embodiment can be applied to a wired / wireless electronic device or particularly a mobile electronic device.

[0203] Figure 13 is a diagram schematically showing another example of a data processing system including a memory system according to the present embodiment. Figure 13 An SSD to which the memory system according to the present embodiment is applied is schematically shown.

[0204] Referring to Figure 13 , the SSD 6300 can include a controller 6320 and a memory device 6340 including a plurality of nonvolatile memories. The controller 6320 can correspond to the controller 130 in the memory system 110 of Figures 1 to 10 , and the memory device 6340 can correspond to the memory device 150 in the memory system of Figures 1 to 10 .

[0205] More specifically, the controller 6320 can be connected to the memory device 6340 through a plurality of channels CH1 to CHi. The controller 6320 can include one or more processors 6321, a buffer memory 6325, an ECC circuit 6322, a host interface 6324, and a memory interface such as a nonvolatile memory interface 6326.

[0206] The buffer memory 6325 can temporarily store data provided from the host 6310 or data provided from a plurality of flash memories NVM included in the memory device 6340, or temporarily store metadata of the plurality of flash memories NVM, for example, mapping data including a mapping table. The buffer memory 6325 can be implemented by a volatile memory such as a DRAM, a SDRAM, a DDR SDRAM, a LPDDR SDRAM, and a GRAM, or a non-volatile memory such as an FRAM, a ReRAM, an STT-MRAM, and a PRAM. For convenience of description, Figure 12 It is illustrated that the buffer memory 6325 is present inside the controller 6320. However, the buffer memory 6325 can be present outside the controller 6320.

[0207] The ECC circuit 6322 can calculate an ECC value of data to be programmed to the memory device 6340 during a programming operation, perform an error correction operation on data read from the memory device 6340 based on the ECC value during a read operation, and perform an error correction operation on data recovered from the memory device 6340 during a failed data recovery operation.

[0208] The host interface 6324 can provide an interface function with an external device such as the host 6310, and the non-volatile memory interface 6326 can provide an interface function with the memory device 6340 connected through a plurality of channels.

[0209] In addition, a plurality of SSDs 6300 of the memory system 110 to which Figures 1 to 10 a plurality of RAID levels, that is, RAID level information of a read command provided from the host 6310 among the SSDs 6300, and provide data read from the selected SSD 6300 to the host 6310.

[0210] Figure 14is a diagram schematically showing another example of a data processing system including a memory system according to the present embodiment. Figure 14 is a diagram schematically showing an embedded Multi Media Card (eMMC) to which a memory system according to the present embodiment is applied.

[0211] Referring to Figure 14 , the eMMC 6400 can include a controller 6430 and a memory device 6440 implemented by one or more NAND flash memories. The controller 6430 can correspond to the controller 130 in the memory system 110 of Figures 1 to 10 , and the memory device 6440 can correspond to the memory device 150 in the memory system 110 of Figures 1 to 10 .

[0212] More specifically, the controller 6430 can be connected to the memory device 6440 through a plurality of channels. The controller 6430 can include one or more cores 6432, a host interface 6431, and a memory interface such as a NAND interface 6433.

[0213] The core 6432 can control overall operations of the eMMC 6400, the host interface 6431 can provide an interface function between the controller 6430 and the host 6410, and the NAND interface 6433 can provide an interface function between the memory device 6440 and the controller 6430. For example, the host interface 6431 can serve as a parallel interface such as the MMC interface described with reference to Figure 1 . Also, the host interface 6431 can serve as a serial interface such as a UHS ((Ultra High Speed)-I / UHS-II) interface.

[0214] Figures 15 to 18 is a diagram schematically showing another example of a data processing system including a memory system according to the present embodiment. Figures 15 to 18 is a diagram schematically showing a UFS (Universal Flash Storage) system to which a memory system according to the present embodiment is applied.

[0215] Referring to Figures 15 to 18 , the UFS systems 6500, 6600, 6700, and 6800 can include hosts 6510, 6610, 6710, and 6810, UFS devices 6520, 6620, 6720, and 6820, and UFS cards 6530, 6630, 6730, and 6830, respectively. The hosts 6510, 6610, 6710, and 6810 can serve as application processors of wired / wireless electronic devices or particularly mobile electronic devices, the UFS devices 6520, 6620, 6720, and 6820 can serve as embedded UFS devices, and the UFS cards 6530, 6630, 6730, and 6830 can serve as external embedded UFS devices or removable UFS cards.

[0216] The host 6510, 6610, 6710, and 6810, the UFS device 6520, 6620, 6720, and 6820, and the UFS card 6530, 6630, 6730, and 6830 in each of the UFS systems 6500, 6600, 6700, and 6800 can communicate with an external device such as a wired / wireless electronic device or particularly a mobile electronic device through a UFS protocol, and the UFS device 6520, 6620, 6720, and 6820 and the UFS card 6530, 6630, 6730, and 6830 can communicate with the host 6510, 6610, 6710, and 6810 through a UFS interface such as MIPI (Mobile Industry Processor Interface) in the UFS systems 6500, 6600, 6700, and 6800. Figures 1 to 10 The memory system 110 illustrated is implemented. For example, in the UFS systems 6500, 6600, 6700, and 6800, the UFS device 6520, 6620, 6720, and 6820 can be implemented in the form of the data processing system 6200, the SSD 6300, or the eMMC 6400 described with reference to Figures 12 to 14 The UFS card 6530, 6630, 6730, and 6830 can be implemented in the form of the memory card system 6100 described with reference to Figure 7 The UFS card 6530, 6630, 6730, and 6830 can be implemented in the form of the memory card system 6100 described with reference to

[0217] Also, in the UFS systems 6500, 6600, 6700, and 6800, the host 6510, 6610, 6710, and 6810, the UFS device 6520, 6620, 6720, and 6820, and the UFS card 6530, 6630, 6730, and 6830 can communicate with each other through a UFS interface such as MIPI (Mobile Industry Processor Interface) in the UFS systems 6500, 6600, 6700, and 6800. In addition, the UFS device 6520, 6620, 6720, and 6820 and the UFS card 6530, 6630, 6730, and 6830 can communicate with each other through various protocols other than the UFS protocol, such as UFD, MMC, SD, mini-SD, and micro-SD.

[0218] In Figure 15In the illustrated UFS system 6500, each of the host 6510, the UFS device 6520, and the UFS card 6530 can include UniPro. The host 6510 can perform switching operations in order to communicate with the UFS device 6520 and the UFS card 6530. In particular, the host 6510 can communicate with the UFS device 6520 or the UFS card 6530 through link layer switching such as L3 switching at UniPro. At this time, the UFS device 6520 and the UFS card 6530 can communicate with each other through link layer switching at UniPro of the host 6510. In the present embodiment, a configuration in which one UFS device 6520 and one UFS card 6530 are connected to the host 6510 has been exemplified for convenience of description. However, a plurality of UFS devices and UFS cards can be connected in parallel or in a star type to the host 6410, and a plurality of UFS cards can be connected in parallel or in a star type to the UFS device 6520, or connected in series or in a chain type to the UFS device 6520.

[0219] In Figure 16 In the illustrated UFS system 6600, each of the host 6610, the UFS device 6620, and the UFS card 6630 can include UniPro, and the host 6610 can communicate with the UFS device 6620 or the UFS card 6630 through a switching module 6640 that performs switching operations, for example, a switching module 6640 that performs link layer switching such as L3 switching at UniPro. The UFS device 6620 and the UFS card 6630 can communicate with each other through link layer switching at the switching module 6640 at UniPro. In the present embodiment, a configuration in which one UFS device 6620 and one UFS card 6630 are connected to the switching module 6640 has been exemplified for convenience of description. However, a plurality of UFS devices and UFS cards can be connected in parallel or in a star type to the switching module 6640, and a plurality of UFS cards can be connected in series or in a chain type to the UFS device 6620.

[0220] In Figure 17In the illustrated UFS system 6700, each of the host 6710, the UFS device 6720, and the UFS card 6730 can include UniPro, and the host 6710 can communicate with the UFS device 6720 or the UFS card 6730 through a switch module 6740 that performs a switching operation, for example, a switch module 6740 that performs a link layer switching (e.g., L3 switching) at UniPro. At this time, the UFS device 6720 and the UFS card 6730 can communicate with each other through the link layer switching of the switch module 6740 at UniPro, and the switch module 6740 can be integrated as one module inside or outside the UFS device 6720 with the UFS device 6720. In the present embodiment, a configuration in which one UFS device 6720 and one UFS card 6730 are connected to the switch module 6740 has been exemplified for convenience of description. However, a plurality of modules each including the switch module 6740 and the UFS device 6720 can be connected in parallel or in a star type to the host 6710, or connected in series or in a chain type to each other. In addition, a plurality of UFS cards can be connected in parallel or in a star type to the UFS device 6720.

[0221] In Figure 18 In the illustrated UFS system 6800, each of the host 6810, the UFS device 6820, and the UFS card 6830 can include M-PHY and UniPro. The UFS device 6820 can perform a switching operation in order to communicate with the host 6810 and the UFS card 6830. In particular, the UFS device 6820 can communicate with the host 6810 or the UFS card 6830 through a switching operation between M-PHY and UniPro modules for communication with the host 6810 and a switching operation between M-PHY and UniPro modules for communication with the UFS card 6830, for example, a target ID (identifier) switching operation. At this time, the host 6810 and the UFS card 6830 can communicate with each other through the target ID switching among the M-PHY and UniPro modules of the UFS device 6820. In the present embodiment, a configuration in which one UFS device 6820 is connected to the host 6810 and one UFS card 6830 is connected to the UFS device 6820 has been exemplified for convenience of description. However, a plurality of UFS devices can be connected in parallel or in a star type to the host 6810 or connected in series or in a chain type to the host 6810, and a plurality of UFS cards can be connected in parallel or in a star type to the UFS device 6820 or connected in series or in a chain type to the UFS device 6820.

[0222] Figure 19 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment. Figure 19 is a diagram schematically illustrating a user system to which a memory system according to the present embodiment is applied.

[0223] Referring to Figure 19 The user system 6900 can include an application processor 6930, a memory module 6920, a network module 6940, a storage module 6950, and a user interface 6910.

[0224] More specifically, the application processor 6930 can drive components such as an OS included in the user system 6900, and include a controller, an interface, and a graphic engine that control the components included in the user system 6900. The application processor 6930 can be provided as a system on chip (SoC).

[0225] The memory module 6920 can serve as a main memory, a working memory, a buffer memory, or a cache memory of the user system 6900. The memory module 6920 can include a volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR3 SDRAM, or LPDDR3 SDRAM, or a non-volatile RAM such as PRAM, ReRAM, MRAM, or FRAM. For example, the application processor 6930 and the memory module 6920 can be packaged and mounted based on a POP (Package on Package).

[0226] The network module 6940 can communicate with external devices. For example, the network module 6940 can support not only wired communication but also various wireless communication protocols such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), worldwide interoperability for microwave access (WiMAX), wireless local area network (WLAN), ultra wideband (UWB), Bluetooth, wireless display (WI-DI), etc., and thus communicate with wired / wireless electronic devices or particularly mobile electronic devices. Accordingly, the memory system and the data processing system according to an embodiment of the present application can be applied to wired / wireless electronic devices. The network module 6940 can be included in the application processor 6930.

[0227] The storage module 6950 can store data, for example, received from the application processor 6930, and then can transfer the stored data to the application processor 6930. The storage module 6950 can be implemented by a non-volatile semiconductor memory device such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), NAND flash, NOR flash, and 3D NAND flash, and can be provided as a removable storage medium such as a memory card or an external drive of the user system 6900. The storage module 6950 can correspond to the storage module 6950 of FIG. 6. Figures 1 to 10The memory system 110 is described. Furthermore, the memory module 6950 can be implemented as described above. Figures 13 to 18 The aforementioned SSD, eMMC, and UFS.

[0228] User interface 6910 may include interfaces for inputting data or commands to application processor 6930 or for outputting data to external devices. For example, user interface 6910 may include user input interfaces such as keyboards, keypads, buttons, touch panels, touch screens, touchpads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements, as well as user output interfaces such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) display devices, active-matrix OLED (AMOLED) display devices, LEDs, speakers, and motors.

[0229] In addition, when Figures 1 to 10 When the memory system 110 is applied to the mobile electronic device of the user system 6900, the application processor 6930 can control all operations of the mobile electronic device, and the network module 6940 can be used as a communication module for controlling wired / wireless communication with external devices. The user interface 6910 can display data processed by the processor 6930 on the display / touch module of the mobile electronic device, or support the function of receiving data from the touch panel.

[0230] According to embodiments of the present invention, a memory system is provided comprising multiple memory devices connected to different channels or different paths, and even if the memory devices are connected to different channels or different paths, bad memory blocks of the memory devices can be managed by an integrated method. Therefore, bad memory blocks can be managed effectively.

[0231] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A memory system comprising: a plurality of first memory devices each coupled to a first channel and comprising a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and comprising a plurality of second memory blocks; a first access controller adapted to control access to the first memory blocks; a second access controller adapted to control access to the second memory blocks; a first bad block table comprising mapping relationship information between a part of entries of bad physical addresses corresponding to bad blocks included in each of the first memory devices and the second memory devices and first replacement physical addresses corresponding to the first memory blocks; a second bad block table comprising mapping relationship information between remaining entries of the bad physical addresses and second replacement physical addresses corresponding to the second memory blocks; a path control element adapted to: select the first access controller and transmit the first replacement physical address when first and second physical addresses respectively corresponding to the first memory blocks and the second memory blocks are identical to the part of the bad physical addresses; select the second access controller and transmit the second replacement physical address when the first and second physical addresses are identical to the remaining part of the bad physical addresses; and select the first access controller and transmit the first physical address or select the second access controller and transmit the second physical address when the first and second physical addresses are not identical to bad physical addresses corresponding to bad blocks included in each of the first memory devices and the second memory devices; and a bad information loading element adapted to: load information of bad physical addresses and replacement physical addresses from the first memory devices and the second memory devices, decide which replacement physical addresses are to be mapped to the bad physical addresses based on a number of loaded bad physical addresses, and generate the first and second bad block tables.

2. The memory system according to claim 1, wherein the path control element comprises: a first specific path control element adapted to: select the first access controller and transmit the first replacement physical address when the first physical address is identical to the part of the bad physical addresses, select the second access controller and transmit the second replacement physical address when the first physical address is identical to the remaining part of the bad physical addresses, and select the first access controller and transmit the first physical address when the first physical address is not identical to the bad physical addresses; and a second specific path control element adapted to: select the second access controller and transmit the second replacement physical address when the second physical address is identical to the remaining part of the bad physical addresses, select the first access controller and transmit the first replacement physical address when the second physical address is identical to the part of the bad physical addresses, and when the second physical address is different from the bad physical address, selecting the second access controller and transferring the second physical address.

3. The memory system according to claim 1, wherein the bad information loading element generates the first bad block table and the second bad block table by checking a total number of the bad physical addresses stored in the first memory device and the second memory device, and allocating the bad physical addresses in a manner that a number of the partial entries of the bad physical addresses and a number of the remaining partial entries of the bad physical addresses do not exceed a predetermined difference number.

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