Display module, integrated circuit and display device

Abstract

The present application discloses a display module, an integrated circuit, and a display device. The display module includes: a display panel, including a data line and a power line; a first capacitor, electrically connected to the power line, and the first capacitor is used to at least partially offset the change in the power voltage on the power line caused by the data voltage on the data line. The display module, integrated circuit, and display device provided according to the embodiments of the present application are conducive to improving the stability of the power voltage, thereby improving the display effect.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display module, an integrated circuit and a display device. Background Art

[0002] With the continuous development of display technology, users have higher and higher requirements for display effects. Display panels usually include data lines and power lines. However, there is a coupling capacitor between the data lines and the power lines. When the data voltage on the data line jumps, the power voltage on the power line is affected by the coupling capacitor and fluctuates synchronously, resulting in signal crosstalk and affecting the display effect. Summary of the invention

[0003] The embodiments of the present application provide a display module, an integrated circuit and a display device, which are beneficial to improving the stability of the power supply voltage, thereby improving the display effect.

[0004] In a first aspect, an embodiment of the present application provides a display module, the display module comprising: a display panel, comprising a data line and a power line; a first capacitor, electrically connected to the power line, the first capacitor being used to at least partially offset the change in the power voltage on the power line caused by the data voltage on the data line.

[0005] Based on the same inventive concept, in the second aspect, an embodiment of the present application provides an integrated circuit for providing a signal to a display panel, the display panel includes a data line and a power line, the integrated circuit includes a first capacitor, the first capacitor is electrically connected to the power line, and the first capacitor is used to at least partially offset the change in the power voltage on the power line caused by the data voltage on the data line.

[0006] Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a display device, comprising the display module as described in the embodiment of the first aspect.

[0007] According to the display module, integrated circuit and display device provided in the embodiments of the present application, by setting the first capacitor, the change of the power voltage on the power line caused by the first capacitor can at least partially offset the change of the power voltage on the power line caused by the data voltage on the data line, thereby being beneficial to improving the stability of the power voltage on the power line, and further improving the problem of bright lines or dark lines that appear at the junction of the dark state and the bright state of the display panel, so as to improve the display effect and improve the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0009] Figure 1A schematic diagram showing a structure of a display panel in the related art;

[0010] Figure 2 A schematic diagram showing a display scene of a display panel is shown;

[0011] Figure 3 A voltage variation diagram of a display panel is shown;

[0012] Figure 4 A schematic diagram showing a structure of a display module provided in an embodiment of the present application is shown;

[0013] Figure 5 Another voltage variation diagram of a display panel is shown;

[0014] Figure 6 Another structural schematic diagram of a display module provided in an embodiment of the present application is shown;

[0015] Figure 7 Another structural schematic diagram of a display module provided in an embodiment of the present application is shown;

[0016] Figure 8 Another structural schematic diagram of a display module provided in an embodiment of the present application is shown;

[0017] Fig. 9 Another structural schematic diagram of a display module provided in an embodiment of the present application is shown;

[0018] Fig.10 Another structural schematic diagram of a display module provided in an embodiment of the present application is shown;

[0019] Fig.11 Another structural schematic diagram of a display module provided in an embodiment of the present application is shown;

[0020] Fig.12 Show Fig.11 A schematic diagram of a cross-sectional structure in the AA direction;

[0021] Fig.13 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0023] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0024] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0025] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0026] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0027] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0028] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0029] like Figure 1 As shown, data lines 1 and power lines 2 may be provided in the display panel 100. The data lines 1 may extend in the longitudinal direction, and the power lines 2 may include transversely extending lines and longitudinally extending lines, thereby forming a grid-shaped power line 2. The data lines 1 are used to transmit the data voltage Vdata. The voltage value of the data voltage Vdata is related to the grayscale image to be displayed. For example, the larger the grayscale value of the grayscale image to be displayed, the smaller the voltage value of the data voltage Vdata may be, and the smaller the grayscale value of the grayscale image to be displayed, the larger the voltage value of the data voltage Vdata may be. The power lines 2 are used to transmit a fixed power supply voltage PVDD. For example, the power lines 2 are used to transmit a positive polarity power supply voltage. In order to clearly distinguish between the data lines and the power lines, Figure 1 In the figure, a data line 1 is indicated by a solid line, and a power line 2 is indicated by a dotted line.

[0030] There is a coupling capacitor between the data line 1 and the power line 2. When the data voltage Vdata of the data line 1 changes, the power voltage of the power line 2 will be affected by the coupling capacitor and will fluctuate synchronously. Figure 2 As shown, it is taken as an example that a part of the display panel displays a black image and a part of the display panel displays a 127 grayscale image. Figure 3 As shown, at position ①, the data voltage Vdata on data line 1 jumps from the voltage corresponding to 127 grayscale to the black state voltage, and the data voltage Vdata jumps upward. Due to the coupling effect, the power supply voltage of power line 2 at position ① will also jump upward, resulting in a bright line at position ①. At position ②, the data voltage Vdata on data line 1 jumps from the black state voltage to the voltage corresponding to 127 grayscale, and the data voltage Vdata jumps downward. Due to the coupling effect, the power supply voltage of power line 2 at position ② will also jump downward, resulting in a dark line at position ②. Therefore, visible bright lines or dark lines will appear at the junction of the dark state picture and the bright state picture. This phenomenon can also be called horizontal line crosstalk, which affects the display effect and thus affects the user experience.

[0031] In order to solve the above problems, the embodiments of the present application provide a display module, an integrated circuit and a display device. The embodiments of the display module, the integrated circuit and the display device will be described below in conjunction with the accompanying drawings.

[0032] like Figure 4 As shown, the display module 200 may include a display panel 20 and a first capacitor C1. The display panel C1 may be an organic light emitting diode (OLED) display panel or other types of display panels.

[0033] The display panel 20 includes a data line 21 and a power line 22. The data line 21 and the power line 22 are both electrically connected to a pixel circuit (not shown) of the display panel 20. The data line 21 is used to transmit a data voltage Vdata to the pixel circuit, and the power line 22 is used to transmit a power voltage PVDD to the pixel circuit. The power line 22 can transmit a positive polarity power voltage PVDD.

[0034] The data lines 21 may extend along a column direction Y, and a plurality of data lines 21 may be arranged in a row direction X.

[0035] To reduce voltage drop, the power line 22 may be in a grid structure. Specifically, the power line 22 may include a portion extending along the row direction X and a portion extending along the column direction Y, and the portion extending along the row direction X and the portion extending along the column direction Y are connected to each other.

[0036] Similarly, in order to clearly distinguish between data lines and power lines, Figure 4 The data line 21 is indicated by a solid line, and the power line 22 is indicated by a dotted line.

[0037] The first capacitor C1 is electrically connected to the power line 22 . The change in the power voltage on the power line 22 caused by the first capacitor C1 can at least partially offset the change in the power voltage on the power line 22 caused by the data voltage on the data line 21 .

[0038] As described above, there is a coupling capacitor between the data line 21 and the power line 22. Therefore, when the data voltage on the data line 21 jumps, the power voltage of the power line 22 will be affected by the coupling capacitor and will fluctuate synchronously. For example, when the data voltage on the data line 21 jumps upward, the power voltage of the power line 22 will also jump upward under the influence of the coupling capacitor; for another example, when the data voltage on the data line 21 jumps downward, the power voltage of the power line 22 will also jump downward under the influence of the coupling capacitor. Among them, the upward jump can be understood as the voltage changing from small to large, and the downward jump can be understood as the voltage changing from large to small.

[0039] Exemplarily, one end of the first capacitor C1 may be electrically connected to the power line 22, and the other end of the first capacitor C1 may be used to receive a jump voltage, and the jump direction of the jump voltage received by the other end of the first capacitor C1 is opposite to the jump direction of the data voltage. For example, when the data voltage on the data line 21 jumps upward, the jump voltage received by the other end of the first capacitor C1 may jump downward; when the data voltage on the data line 21 jumps downward, the jump voltage received by the other end of the first capacitor C1 may jump upward.

[0040] In the embodiment of the present application, by setting the first capacitor C1, the change in the power voltage on the power line 22 caused by the first capacitor C1 can at least partially offset the change in the power voltage on the power line 22 caused by the data voltage on the data line 21. For example, the direction in which the power voltage on the power line 22 is changed by the first capacitor C1 can be opposite to the direction in which the power voltage on the power line 22 is changed by the data voltage on the data line 21. This can help improve the stability of the power voltage on the power line 22, and further improve the problem of bright lines or dark lines that appear at the junction of the dark state and the bright state of the display panel, so as to improve the display effect and the user experience.

[0041] Optionally, the first capacitor C1 may be disposed in the display area of ​​the display panel 20, for example, the first capacitor C1 may be disposed adjacent to the power line 22. There may be a plurality of first capacitors C1, for example, each power line 22 is electrically connected to a first capacitor C1.

[0042] In some embodiments, Figure 4 As shown, the display module 200 may further include an integrated circuit 30, and the integrated circuit 30 may include a power supply terminal 31, and the power supply terminal 31 is electrically connected to the power supply line 22 on the display panel 20. The power supply terminal 31 can be used to provide a power supply voltage PVDD, and the power supply voltage PVDD provided by the power supply terminal 31 can be transmitted to the power supply line 22, and then the power supply line 22 can transmit the power supply voltage PVDD to the pixel circuit on the display panel (not shown in the figure). The power supply terminal 31 can be understood as the output terminal of the power supply voltage PVDD.

[0043] As described above, the power line 22 may be in a grid structure, that is, a plurality of power lines 22 are connected to each other, and the plurality of power lines 22 are electrically connected to the same power terminal 31. When the voltage drop is ignored, it can be considered that the power voltage on the power terminal 31 is the same as the power voltage on the power line 22, and therefore the change of the power voltage on the power terminal 31 is the same as the change of the power voltage on the power line 22. That is, when the power voltage of the power line 22 jumps upward due to the jump of the data voltage, the power voltage of the power terminal 31 also jumps upward; when the power voltage of the power line 22 jumps downward due to the jump of the data voltage, the power voltage of the power terminal 31 also jumps downward.

[0044] One end of the first capacitor C1 can be connected to the power supply terminal 31. Since the power supply terminal 31 is electrically connected to the power line 22 on the display panel 20, one end of the first capacitor C1 is electrically connected to the power line 22 through the power supply terminal 31. The other end of the first capacitor C1 receives the jump voltage. Due to the coupling effect of the first capacitor C1, the power supply voltage of the power supply terminal 31 will jump along with the voltage jump of the other end of the first capacitor C1. Since the power supply voltage of the power supply terminal 31 will be transmitted to the power line 22, the power supply voltage of the power supply terminal 31 jumps, which is equivalent to the power supply voltage of the power line 22 having the same jump. Therefore, when one end of the first capacitor C1 is electrically connected to the power line 22 through the power supply terminal 31, the first capacitor C1 can change the power supply voltage on the power line 22. In addition, by connecting one end of the first capacitor C1 to the power supply terminal 31, the first capacitor C1 can be electrically connected to multiple power lines 22. In this way, only one first capacitor C1 can be set, and the first capacitor C1 does not need to be set in the display area of ​​the display panel 20. This is beneficial to reduce costs and improve the resolution of the display panel.

[0045] In some embodiments, Figure 4 As shown, the integrated circuit 30 may further include an analog voltage terminal 32. The integrated circuit 30 may generate a data voltage Vdata required for display by the display panel 20 according to the analog voltage AVDD of the analog voltage terminal 32. The integrated circuit 30 may further include a data voltage terminal 33, and the data voltage terminal 33 may be electrically connected to the data line 21 of the display panel 20. The number of the data voltage terminals 33 may include multiple. The data voltage Vdata generated by the integrated circuit 30 may be transmitted to the data line 21 of the display panel 20 via the data voltage terminal 33, and then the data line 21 may transmit the data voltage Vdata to the pixel circuit of the display panel 20.

[0046] The inventor has found that when the data voltages on the multiple data lines 21 change in the same way, the analog voltage AVDD of the analog voltage terminal 32 will become over-compensated and unable to maintain a stable voltage. In other words, when the data voltages on the multiple data lines 21 change, the analog voltage AVDD of the analog voltage terminal 32 will produce ripples. The inventor has found that when the data voltages on the multiple data lines 21 all jump upward, the analog voltage AVDD of the analog voltage terminal 32 will jump downward; when the data voltages on the multiple data lines 21 all jump downward, the analog voltage AVDD of the analog voltage terminal 32 will jump upward. Therefore, the jumping direction of the analog voltage AVDD of the analog voltage terminal 32 is opposite to the jumping direction of the data voltages on the multiple data lines 21.

[0047] Specifically, the display scene of the display panel is Figure 2 Take the display scene shown as an example, Figure 5As shown, at position ①, the data voltage Vdata on the data line 21 jumps from the voltage corresponding to the grayscale of 127 to the black state voltage, and the data voltage Vdata jumps upward. Due to the coupling effect, the power supply voltage of the power line 22 at position ① will also jump upward; and the jump direction of the analog voltage AVDD of the analog voltage terminal 32 is opposite to the jump direction of the data voltage. At position ①, the analog voltage AVDD of the analog voltage terminal 32 jumps downward. At position ②, the data voltage Vdata on the data line 21 jumps from the black state voltage to the voltage corresponding to the grayscale of 127, and the data voltage Vdata jumps downward. Due to the coupling effect, the power supply voltage of the power line 22 at position ② will also jump downward; and the jump direction of the analog voltage AVDD of the analog voltage terminal 32 is opposite to the jump direction of the data voltage. At position ②, the analog voltage AVDD of the analog voltage terminal 32 jumps upward.

[0048] Based on the above research findings, one end of the first capacitor C1 can be electrically connected to the power supply terminal 31, and the other end of the first capacitor C1 can be electrically connected to the analog voltage terminal 32. Since the jump direction of the analog voltage AVDD of the analog voltage terminal 32 is opposite to the jump direction of the data voltage on the multiple data lines 21, the change in the power supply voltage on the power line 22 caused by the jump of the analog voltage AVDD of the analog voltage terminal 32 can at least partially offset the change in the power supply voltage on the power line 22 caused by the data voltage on the data line 21, thereby facilitating the improvement of the stability of the power supply voltage on the power line 22. In addition, by electrically connecting the other end of the first capacitor C1 to the analog voltage terminal 32, there is no need to additionally set up a voltage terminal capable of providing a jump voltage, so that only one first capacitor C1 is needed to improve the stability of the power supply voltage on the power line 22, and the structure is relatively simple.

[0049] like Figure 6 As shown, the display panel 20 may include a display area AA and a non-display area NA at least partially surrounding the display area AA. The data line 21 and the power line 22 are located in the display area AA. The non-display area NA may include a binding area BA. The display module 200 may also include a flexible circuit board (FPC) 40. The flexible circuit board 40 is bound to the binding area BA. The integrated circuit 30 and the first capacitor C1 may both be located on the flexible circuit board 40. The integrated circuit 30 may be a driving chip. The first capacitor C1 is located on the flexible circuit board 40, which can be understood as the first capacitor C1 is formed on the flexible circuit board 40, and the first capacitor C1 does not belong to the integrated circuit 30.

[0050] In the embodiment of the present application, by disposing the first capacitor C1 on the flexible circuit board 40 , the structure of the integrated circuit 30 does not need to be changed.

[0051] As an example, the first capacitor C1 may be a chip capacitor.

[0052] Exemplarily, the binding area BA may include binding terminals (not shown in the figure), for example, the binding area BA may include a binding terminal for transmitting a power supply voltage and a binding terminal for transmitting a data voltage, the binding terminal for transmitting the power supply voltage is connected to the power line 22 in the display area, and the binding terminal for transmitting the data voltage is connected to the data line 21 in the display area.

[0053] The flexible circuit board 40 is connected to each binding terminal. The flexible circuit board 40 provides a signal transmission connection path between the binding terminal and the integrated circuit 30. The power supply voltage provided by the power supply terminal 31 on the integrated circuit 30 can be transmitted to the binding terminal for transmitting the power supply voltage through the flexible circuit board 40, and then to the power line 22 through the binding terminal for transmitting the power supply voltage. The integrated circuit 30 can generate a data voltage according to the analog voltage of the analog voltage terminal 32, and then the generated data voltage can be transmitted to the binding terminal for transmitting the data voltage through the flexible circuit board 40, and then to the data line 21 through the binding terminal for transmitting the data voltage.

[0054] Optionally, after the flexible circuit board 40 is bound to the binding area BA, the portion not bound to the binding area BA can be folded back to the non-light-emitting surface of the display panel 20, and the integrated circuit 30 can be located on the non-light-emitting surface of the display panel 20, which is conducive to realizing a narrow frame design.

[0055] In some embodiments, the integrated circuit 30 may be a display driver chip (Display Driver Integrated Circuit, DDIC). The DDIC may convert the data to be displayed into data voltages and transmit them to each data line 21. In the case where the integrated circuit 30 is a DDIC, the DDIC may provide a high-level power supply voltage PVDD for the display panel 20. Optionally, the DDIC may also provide a low-level power supply voltage PVEE for the display panel 20.

[0056] In other embodiments, Figure 7 As shown, the integrated circuit 30 may include a first integrated circuit 301 and a second integrated circuit 302. The first integrated circuit 301 may be a power management chip (Power Management Interface Controller, PMIC), and the second integrated circuit 302 may be a DDIC. The first integrated circuit 301 includes a power supply terminal 31, and the second integrated circuit 302 includes an analog power supply terminal 32. The second integrated circuit 302 may also include a data voltage terminal 33.

[0057] The first integrated circuit 301 can be electrically connected to the display panel 20 and the second integrated circuit 302, and the first integrated circuit 301 provides operating voltages for the display panel 20 and the second integrated circuit 302. For example, the first integrated circuit 301 provides a high-level power supply voltage PVDD for the display panel 20 through the power supply terminal 31. The first integrated circuit 301 can also provide a low-level power supply voltage PVEE for the display panel 20. The first integrated circuit 301 can provide a voltage to the analog power supply terminal 32 of the second integrated circuit 302.

[0058] In some embodiments, Figure 8 As shown, the display module 200 may further include a second capacitor C2, one end of the second capacitor C2 is electrically connected to the power supply terminal 31, and the other end of the second capacitor C2 is electrically connected to the ground terminal GND. It is understandable that the voltage of the ground terminal GND is a fixed voltage, so the second capacitor C2 can be understood as a voltage-stabilizing capacitor, and the second capacitor C2 can be used to stabilize the voltage of the power supply terminal 31.

[0059] The capacitance value of the first capacitor C1 can be less than or equal to the capacitance value of the second capacitor C2. The second capacitor C2 is used to stabilize the voltage of the power supply terminal 31, while the first capacitor C1 is used to pull the voltage change of the power supply terminal 31. In most cases, it is hoped that the voltage of the power supply terminal 31 is relatively stable. The capacitance value of the second capacitor C2 is relatively large, so the second capacitor C2 has a strong ability to stabilize the voltage of the power supply terminal 31.

[0060] In some embodiments, Figure 8 As shown, the display module 200 may further include a third capacitor C3, one end of the third capacitor C3 is electrically connected to the analog voltage terminal 32, and the other end of the third capacitor C3 is electrically connected to the ground terminal GND. Similarly, the voltage of the ground terminal GND is a fixed voltage, so the third capacitor C3 can be understood as a voltage-stabilizing capacitor, and the third capacitor C3 can be used to stabilize the voltage of the analog voltage terminal 32.

[0061] The capacitance value of the first capacitor C1 may be greater than or equal to the capacitance value of the third capacitor C3. The inventor has found that the voltage at the analog voltage terminal 32 is usually relatively stable, so the capacitance value of the voltage stabilizing capacitor required can be slightly smaller, that is, the capacitance value of the third capacitor C3 can be smaller. The voltage fluctuation at the analog voltage terminal 32 is relatively small, so when the capacitance value of the first capacitor C1 is large, the coupling ability of the first capacitor C1 is strong, and even if the voltage fluctuation at the analog voltage terminal 32 is relatively small, the voltage change of the power supply terminal 31 can be achieved.

[0062] For example, Figure 8As shown, the display module 200 may further include a fourth capacitor C4, one end of the fourth capacitor C4 is electrically connected to the data voltage terminal 33, and the other end of the fourth capacitor C4 is electrically connected to the ground terminal GND. Similarly, the voltage of the ground terminal GND is a fixed voltage, so the fourth capacitor C4 can be understood as a voltage-stabilizing capacitor, and the fourth capacitor C4 can be used to stabilize the voltage of the data voltage terminal 33.

[0063] The display panel may have different operating modes, for example, the operating mode of the display panel may include a first operating mode and a second operating mode. In the first operating mode, the capacitance value of the first capacitor C1 is C11, and in the second operating mode, the capacitance value of the first capacitor C1 is C12, C11≠C12. In this way, the capacitance value of the first capacitor C1 can be adjusted according to the operating mode of the display panel to flexibly adapt to different needs.

[0064] It should be noted that the operating modes of the display panel mentioned in the embodiments of the present application include the first operating mode and the second operating mode, which do not simply refer to the two operating modes of the display panel, but the first operating mode and the second operating mode are used to represent different operating modes of the display panel. In different application scenarios, the operating modes of the display panel are different. For example, in different operating modes, the display panel requires different power supply voltages, or in different operating modes, the display panel will have different brightness.

[0065] As an example, in the first working mode, the power supply voltage on the power supply line 22 is PVDD1, and in the second working mode, the power supply voltage on the power supply line 22 is PVDD2, PVDD1≠PVDD2.

[0066] For example, one of the first working mode and the second working mode is a low power consumption working mode, and the other is a high power consumption working mode.

[0067] For example, the greater the power supply voltage on the power line 22, the greater the capacitance value of the corresponding first capacitor C1. Alternatively, the greater the power supply voltage on the power line 22, the smaller the capacitance value of the corresponding first capacitor C1. The magnitude relationship between the power supply voltage on the power line 22 and the capacitance value of the first capacitor C1 can be set according to the actual characteristics or actual needs of the display panel, and this application does not limit this.

[0068] Optionally, (PVDD1-PVDD2)*(C11-C12)>0. For example, PVDD1>PVDD2, and C11>C12. Alternatively, PVDD1<PVDD2, and C11<C12.

[0069] As another example, in different working modes, the display panel may have different brightness, and the data voltage corresponding to the same gray scale may be different. When the display panel displays a picture, the display panel may present different brightness according to the environment in which the display panel is located. For example, at the target gray scale and in the first working mode, the data voltage on the data line 21 is Vdata1, and at the target gray scale and in the second working mode, the data voltage on the data line 21 is Vdata2, and Vdata1≠Vdata2.

[0070] The data voltage corresponding to the grayscale 0 of the display panel is the black state voltage. In different working modes, the black state voltage can be the same. The target grayscale can be any grayscale other than grayscale 0. For example, the grayscale range that the display panel can display is 0 to 255, and the target grayscale can be any grayscale in grayscales 1 to 255.

[0071] Taking the target grayscale of 127 grayscale as an example, the data voltage corresponding to 127 grayscale in the first working mode is different from the data voltage corresponding to 127 grayscale in the second working mode. In the first working mode and the second working mode, the data voltage jump amount from 127 grayscale to 0 grayscale is different. Therefore, the capacitance value of the first capacitor C1 in the two working modes can be set to be different to adapt to different data voltage jump amounts.

[0072] For example, Vdata1>Vdata2, C11>C12. Or, Vdata1<Vdata2, C11<C12. The magnitude relationship of the data voltage on the data line 21 and the magnitude relationship of the capacitance value of the first capacitor C1 in different working modes can be set according to the actual characteristics or actual needs of the display panel, and this application does not limit this.

[0073] In some embodiments, such as Fig. 9 As shown, the first capacitor C1 may include at least two sub-capacitors connected in parallel, and at least one sub-capacitor is connected in series with the switch element K. For example, the first capacitor C1 includes a first sub-capacitor C01 and a second sub-capacitor C02 connected in parallel, and the second sub-capacitor C02 is connected in series with the switch element K. When a larger capacitance value is required, the switch element K can be controlled to be turned on; when a smaller capacitance value is required, the switch element K can be controlled to be turned off.

[0074] In some embodiments, such as Fig.10 As shown, the first capacitor C1 may include at least two sub-capacitors connected in series, and at least one sub-capacitor is connected in parallel with the switch element K. For example, the first capacitor C1 includes a first sub-capacitor C01 and a second sub-capacitor C02 connected in series, and the first sub-capacitor C01 is connected in parallel with the switch element K. When a larger capacitance value is required, the switch element K can be controlled to be turned on; when a smaller capacitance value is required, the switch element K can be controlled to be turned off.

[0075] The switch element K may be a transistor or other types of switch devices.

[0076] In some examples, such as Fig.11 As shown, the power terminal 31 is connected to a first connection line 51, and the analog voltage terminal 32 is connected to a second connection line 52. The first connection line 51 transmits a signal of the power terminal 31, for example, the first connection line 51 can transmit the power voltage provided by the power terminal 31 to the display area of ​​the display panel. The second connection line 52 transmits a signal of the analog voltage terminal 32, for example, the second connection line 52 can transmit the signal of the analog voltage terminal 32 to the data voltage generating circuit, so that the data voltage generating circuit generates a data signal.

[0077] The first connection line 51 and the second connection line 52 may both extend along the first direction, the first capacitor C1 may extend along the second direction, and the first direction intersects the second direction. For example, the contact point of the connection line 311 between the first capacitor C1 and the power supply terminal 31 is N1, and the contact point of the connection line 321 between the first capacitor C1 and the analog voltage terminal 32 is N2. The extension direction of the first capacitor C1 can be understood as the extension direction of the line passing through the contact point N1 and the contact point N2.

[0078] As an example, Fig.12 As shown, the first connection line 51 , the second connection line 52 , the connection line 311 between the first capacitor C1 and the power terminal 31 , and the connection line 321 between the first capacitor C1 and the analog voltage terminal 32 may be located in the same film layer.

[0079] Based on the same inventive concept, the embodiment of the present application also provides an integrated circuit. The integrated circuit is used to provide a signal for a display panel. Figure 4 As shown, the display panel includes a data line 21 and a power line 22, and the integrated circuit 30 includes a first capacitor C1, which is electrically connected to the power line 22. The change in the power voltage on the power line 22 caused by the first capacitor C1 can at least partially offset the change in the power voltage on the power line 22 caused by the data voltage on the data line 21.

[0080] In the embodiment of the present application, by setting the first capacitor C1, the change of the power voltage on the power line 22 caused by the first capacitor C1 can at least partially offset the change of the power voltage on the power line 22 caused by the data voltage on the data line 21. For example, the direction of change of the power voltage on the power line 22 caused by the first capacitor C1 is opposite to the direction of change of the power voltage on the power line 22 caused by the data voltage on the data line 21, which can help improve the stability of the power voltage on the power line 22, and further improve the problem of bright lines or dark lines that appear at the junction of the dark state and the bright state of the display panel, so as to improve the display effect and improve the user experience.

[0081] In the present application, the integrated circuit may specifically be an integrated chip.

[0082] like Figure 4 As shown, the integrated circuit 30 includes a power supply terminal 31, an analog voltage terminal 32 and a data voltage terminal 33. The data voltage terminal 33 is electrically connected to the data line 21, and the data voltage terminal 33 is electrically connected to the analog voltage terminal 32. The integrated circuit 30 can generate the data voltage Vdata required for the display panel 20 to display according to the analog voltage AVDD of the analog voltage terminal 32, and the data voltage Vdata generated by the integrated circuit 30 can be transmitted to the data line 21 of the display panel 20 through the data voltage terminal 33, and then the data line 21 can transmit the data voltage Vdata to the pixel circuit of the display panel 20.

[0083] The power terminal 31 is electrically connected to the power line 22 . The power terminal 31 can be used to provide a power voltage PVDD. The power voltage PVDD provided by the power terminal 31 can be transmitted to the power line 22 .

[0084] One end of the first capacitor C1 is electrically connected to the power supply terminal 31, and the other end of the first capacitor C1 is electrically connected to the analog voltage terminal 32. Since the jump direction of the analog voltage AVDD of the analog voltage terminal 32 is opposite to the jump direction of the data voltage on the multiple data lines 21, the change in the power supply voltage on the power line 22 caused by the jump of the analog voltage AVDD of the analog voltage terminal 32 can at least partially offset the change in the power supply voltage on the power line 22 caused by the data voltage on the data line 21, thereby facilitating the improvement of the stability of the power supply voltage on the power line 22. In addition, by electrically connecting the other end of the first capacitor C1 to the analog voltage terminal 32, there is no need to additionally set a voltage terminal capable of providing a jump voltage, so that only one first capacitor C1 is needed to improve the stability of the power supply voltage on the power line 22, and the structure is relatively simple.

[0085] like Figure 7 As shown, the integrated circuit 30 may include a first integrated circuit 301 and a second integrated circuit 302. The first integrated circuit 301 may be a PMIC, and the second integrated circuit 302 may be a DDIC. The first integrated circuit 301 includes a power supply terminal 31, and the second integrated circuit 302 includes an analog power supply terminal 32 and a data voltage terminal 33. Either the first integrated circuit 301 or the second integrated circuit 302 includes a first capacitor C1.

[0086] Based on the same inventive concept, the present application also provides a display device, including the display panel provided by the present application. Fig.13 , Fig.13 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.13 The provided display device 1000 includes the display module 200 provided by any of the above embodiments of the present application. Fig.13The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display module provided in the embodiment of the present application. For details, please refer to the specific description of the display module in the above embodiments, and this embodiment will not be repeated here.

[0087] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display module, characterized in that: include: Display panel, including data cables and power cables; A first capacitor is electrically connected to the power line, and the first capacitor is used to at least partially offset the change of the power voltage on the power line caused by the data voltage on the data line; The working mode of the display panel includes a first working mode and a second working mode; In the first working mode, the capacitance value of the first capacitor is C11, and in the second working mode, the capacitance value of the first capacitor is C12, C11≠C12; In the first working mode, the power supply voltage on the power line is PVDD1, and in the second working mode, the power supply voltage on the power line is PVDD2, PVDD1≠PVDD2; (PVDD1-PVDD2)*(C11-C12)>0.

2. The display module according to claim 1, characterized in that: The display module further includes an integrated circuit, the integrated circuit includes a power supply terminal, the power supply terminal is electrically connected to the power supply line, and the first capacitor is electrically connected to the power supply line through the power supply terminal.

3. The display module according to claim 2, characterized in that: The integrated circuit further includes an analog voltage terminal, one end of the first capacitor is electrically connected to the power supply terminal, and the other end of the first capacitor is electrically connected to the analog voltage terminal.

4. The display module according to claim 3, characterized in that: The power supply end is connected to a first connection line, the analog voltage end is connected to a second connection line, the first connection line and the second connection line extend along a first direction, the first capacitor extends along a second direction, and the first direction intersects with the second direction.

5. The display module according to claim 3, characterized in that: The display module also includes a flexible circuit board, and the integrated circuit and the first capacitor are both located on the flexible circuit board.

6. The display module according to claim 3, characterized in that: The integrated circuit includes a display driver chip.

7. The display module according to claim 3, characterized in that: The integrated circuit includes a first integrated circuit and a second integrated circuit, the first integrated circuit includes a power management chip, and the second integrated circuit includes a display driver chip; The first integrated circuit includes the power supply terminal, and the second integrated circuit includes the analog voltage terminal.

8. The display module according to claim 3, characterized in that: The display module also includes a second capacitor, one end of the second capacitor is electrically connected to the power end, the other end of the second capacitor is electrically connected to the ground end, and the capacitance value of the first capacitor is less than or equal to the capacitance value of the second capacitor.

9. The display module according to claim 8, characterized in that: The display module also includes a third capacitor, one end of the third capacitor is electrically connected to the analog voltage end, the other end of the second capacitor is electrically connected to the ground end, and the capacitance of the first capacitor is greater than or equal to the capacitance of the second capacitor.

10. The display module according to claim 3, characterized in that: The first capacitor is a chip capacitor.

11. The display module according to claim 1, characterized in that: At the target gray scale and in the first operation mode, the data voltage on the data line is Vdata1 , and at the target gray scale and in the second operation mode, the data voltage on the data line is Vdata2 , Vdata1 ≠ Vdata2 .

12. The display module according to claim 1, characterized in that: The first capacitor includes at least two sub-capacitors connected in parallel, and at least one sub-capacitor is connected in series with the switch element.

13. The display module according to claim 1, characterized in that: The first capacitor includes at least two sub-capacitors connected in series, and at least one sub-capacitor is connected in parallel with the switch element.

14. An integrated circuit, characterized in that: used to provide a signal for a display panel, the display panel comprising a data line and a power line, the integrated circuit comprising a first capacitor, the first capacitor being electrically connected to the power line, the first capacitor being used to at least partially offset a change in a power voltage on the power line caused by a data voltage on the data line; The operating modes of the display panel include a first operating mode and a second operating mode; in the first operating mode, the capacitance value of the first capacitor is C11, and in the second operating mode, the capacitance value of the first capacitor is C12, C11≠C12; in the first operating mode, the power supply voltage on the power line is PVDD1, and in the second operating mode, the power supply voltage on the power line is PVDD2, PVDD1≠PVDD2; (PVDD1-PVDD2)*(C11-C12)>0.

15. The integrated circuit according to claim 14, characterized in that The integrated circuit includes a power supply terminal, an analog voltage terminal and a data voltage terminal, the data voltage terminal is electrically connected to the data line, and the data voltage terminal is electrically connected to the analog voltage terminal, the power supply terminal is electrically connected to the power line, one end of the first capacitor is electrically connected to the power supply terminal, and the other end of the first capacitor is electrically connected to the analog voltage terminal.

16. The integrated circuit according to claim 15, characterized in that The integrated circuit includes a first integrated circuit and a second integrated circuit, the first integrated circuit includes the power supply terminal, and the second integrated circuit includes the analog voltage terminal and the data voltage terminal; Either one of the first integrated circuit and the second integrated circuit includes the first capacitor.

17. A display device, characterized in that: Comprising a display module as described in any one of claims 1 to 13.

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