A display panel and a driving method thereof, and a display device

Abstract

The present disclosure relates to the field of display technology, and discloses a display panel, a driving method thereof, and a display device. The display panel includes a gate driving circuit and a driving integrated circuit, the gate driving circuit includes a cascaded first shift register unit and a second shift register unit, the first shift register unit is used to output a gate driving signal, a cascade control signal, and a sensing driving signal, and the second shift register unit is used to output a gate driving signal and a cascade control signal; the driving integrated circuit is connected to each pixel driving circuit, and is used to obtain a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each first shift register unit, and determine a compensation sensing value of a pixel row corresponding to each second shift register unit based on each sensing voltage signal. The display panel provided by the present disclosure can realize rapid detection of each shift register unit on the basis of realizing a simplified circuit structure of the gate driving circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a display panel and a driving method thereof, and a display device. Background Art

[0002] At present, in order to reduce costs, the gate drive circuit design (GOA) is used in the panel. The simpler the GOA circuit, the higher the product yield and the narrower the frame. In the related technology, due to the influence of compensation time, the panel has the problem of poor uniformity.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel and a driving method thereof, and a display device.

[0005] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0006] A gate driving circuit, the gate driving circuit comprising a first shift register unit and a second shift register unit connected in cascade, the first shift register unit being used to output a gate driving signal, a cascade control signal and a sensing driving signal, and the second shift register unit being used to output a gate driving signal and a cascade control signal; the first shift register unit can output sensing driving signals of a pixel driving circuit having the same number as the corresponding plurality of pixel rows;

[0007] A driver integrated circuit is connected to each pixel driving circuit, and is used to obtain a sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to each first shift register unit, and determine a compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit based on each sensing voltage signal.

[0008] In an exemplary embodiment of the present disclosure, the gate drive circuit includes multiple repeating units, and the repeating units include a first shift register unit and N second shift register units, where N is a natural number; within the same repeating unit, the first shift register unit and each second shift register unit are cascaded in sequence; in any two adjacent repeating units, the last level second shift register unit in the previous repeating unit is connected to the first shift register unit of the next repeating unit.

[0009] In an exemplary embodiment of the present disclosure, the first shift register unit and the second shift register unit both include: a cascade control module, connected to a pull-up node, a second clock signal terminal and a cascade signal output terminal, the cascade control module being used to respond to a signal of the pull-up node to transmit a signal of the second clock signal terminal to the cascade signal output terminal for output; a gate control module, connected to a pull-up node, a third clock signal terminal and a gate signal output terminal, the gate control module being used to respond to a signal of the pull-up node to transmit a signal of the third clock signal terminal to the gate signal output terminal for output.

[0010] In an exemplary embodiment of the present disclosure, in the same first shift register unit and the same second shift register unit, the cascade control module and the gate control module are both one or more, and the number of the gate control modules is k times the number of the cascade control modules, where k is a positive integer greater than or equal to 1.

[0011] In an exemplary embodiment of the present disclosure, the first shift register unit also includes: a sensing module, connected to an input terminal, a sensing control terminal, a pre-stored node, a common node and a first clock signal terminal, the sensing module being used to respond to a signal from the sensing control terminal to write the signal from the input terminal into the pre-stored node for storage, and respond to a signal from the pre-stored node to transmit the signal from the first clock signal terminal to the common node; a leakage control module, connected to a first power supply terminal, a first node and the pre-stored node, the leakage control module being used to respond to a signal from the pre-stored node to transmit the signal from the first power supply terminal to the first node so that the potential difference between the node and the common node is stabilized; an isolation module, connected to the common node, the pull-up node and the first clock signal terminal, the isolation module being used to respond to a signal from the first clock signal terminal to conduct the common node and the pull-up node so as to control the gate control module to output the sensing drive signal through the pull-up node.

[0012] In an exemplary embodiment of the present disclosure, the sensing module includes: a first transistor, a first electrode connected to an input terminal, a second electrode connected to a first node, and a gate connected to the sensing control terminal; a second transistor, a first electrode connected to the first node, a second electrode connected to the pre-stored node, and a gate connected to the sensing control terminal; a storage capacitor, one end of which is connected to the pre-stored node and the other end receives a first level signal; a third transistor, a first electrode connected to the first clock signal terminal, a second electrode connected to the common node, and a gate connected to the pre-stored node; the leakage control module includes: a fiftieth transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the first node, and a gate connected to the pre-stored node, and the fiftieth transistor is used to respond to the signal of the pre-stored node and transmit the signal of the first power supply terminal to the first node to stabilize the potential difference between the first node and the pre-stored node; the isolation module includes: a fourth transistor, a first electrode connected to the common node, a second electrode connected to the first control node, and a gate connected to the first clock signal terminal; a fifth transistor, a first electrode connected to the first control node, a second electrode connected to the pull-up node, and a gate connected to the first clock signal terminal.

[0013] In an exemplary embodiment of the present disclosure, the driver integrated circuit is further used for:

[0014] Acquiring a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each of the first shift register units;

[0015] The interpolation method is used to determine the compensation sensing value of the pixel driving circuit corresponding to the pixel row corresponding to each of the second shift register units based on the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to each of the first shift register units.

[0016] In an exemplary embodiment of the present disclosure, the driver integrated circuit is further used for:

[0017] Acquiring a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each of the first shift register units;

[0018] The interpolation method is used to determine the compensation sensing value of the pixel driving circuit of the pixel row corresponding to the second shift register unit located between the two adjacent first shift register units based on the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to the two adjacent first shift register units.

[0019] In an exemplary embodiment of the present disclosure, the driver integrated circuit is further used for:

[0020] Acquiring a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each of the first shift register units;

[0021] Determine a first average value of a sensing voltage signal generated by a pixel driving circuit of each pixel row corresponding to the first shift register unit in each repetitive unit;

[0022] The first average value is determined as a compensation sensing value of a pixel driving circuit of each pixel row corresponding to the second shift register unit in the same repetitive unit.

[0023] In an exemplary embodiment of the present disclosure, the driver integrated circuit is further used for:

[0024] Acquiring a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each of the first shift register units;

[0025] Determine a second average value of the sensing voltage signal generated by the pixel driving circuit corresponding to each pixel row of two adjacent first shift register units;

[0026] The second average value is determined as a compensation sensing value of a pixel driving circuit of each pixel row corresponding to the second shift register unit between the two adjacent first shift register units.

[0027] According to a second aspect of the present disclosure, a display panel driving method is further provided, for driving the display panel according to any embodiment of the present disclosure, the driving method comprising:

[0028] Acquiring a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each of the first shift register units;

[0029] Determine the compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit based on each sensing voltage signal;

[0030] The compensation sensing value is used to perform threshold voltage compensation on the driving transistors in the pixel rows corresponding to each of the second shift register units.

[0031] Determining the compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit based on each sensing voltage signal in any embodiment of the present disclosure includes:

[0032] The interpolation method is used to determine the compensation sensing value of the pixel driving circuit of the pixel row corresponding to the second shift register unit located between the two adjacent first shift register units based on the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to the two adjacent first shift register units.

[0033] Determining the compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit based on each sensing voltage signal in any embodiment of the present disclosure includes:

[0034] Determine a first average value of a sensing voltage signal generated by a pixel driving circuit of each pixel row corresponding to the first shift register unit in each repetitive unit;

[0035] The first average value is determined as a compensation sensing value of a pixel driving circuit of each pixel row corresponding to the second shift register unit in the same repetitive unit.

[0036] Determining the compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit based on each sensing voltage signal in any embodiment of the present disclosure includes:

[0037] Determine a second average value of the sensing voltage signal generated by the pixel driving circuit corresponding to each pixel row of two adjacent first shift register units;

[0038] The second average value is determined as a compensation sensing value of a pixel driving circuit of each pixel row corresponding to the second shift register unit between the two adjacent first shift register units.

[0039] According to a third aspect of the present disclosure, a display device is also provided, comprising the display panel described in any embodiment of the present disclosure.

[0040] The display panel provided by the present disclosure comprises a cascaded first shift register unit and a second shift register unit in the gate driving circuit. The first shift register unit can output a sensing driving signal in addition to outputting a cascade control signal and a gate driving signal, while the second shift register unit only outputs a cascade control signal and a gate driving signal, that is, the second shift register unit does not need a sensing driving signal, thereby simplifying the circuit structure of the second shift register unit. On this basis, the driver integrated circuit generates a sensing voltage signal according to the pixel driving circuit of the pixel row corresponding to each first shift register unit, and uses an interpolation method or an average method to determine the compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit, thereby realizing rapid detection of each shift register unit on the basis of simplifying the circuit structure of the gate driving circuit.

[0041] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0043] Figure 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

[0044] Figure 2 for Figure 1 An exemplary structural diagram of the first shift register unit;

[0045] Figure 3 for Figure 1 An exemplary structural diagram of the second shift register unit;

[0046] Figure 4 for Figure 1 Another exemplary structural diagram of the first shift register unit;

[0047] Figure 5 for Figure 1 Another exemplary structural diagram of the second shift register unit;

[0048] Figure 6 A schematic diagram of a circuit for sensing a pixel driving circuit according to an embodiment of the present disclosure;

[0049] Figure 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure;

[0050] Figure 8 is a schematic structural diagram of a gate driving circuit according to another embodiment of the present disclosure;

[0051] Figure 9a To implement an embodiment of the present disclosure Figure 4 A schematic diagram of the circuit structure of the shift register unit shown;

[0052] Figure 9b To implement another embodiment of the present disclosure Figure 4 A schematic diagram of the circuit structure of the shift register unit shown;

[0053] Fig.10a To implement an embodiment of the present disclosure Figure 5 A schematic diagram of the circuit structure of the shift register unit shown;

[0054] Fig.10b To implement another embodiment of the present disclosure Figure 5 A schematic diagram of the circuit structure of the shift register unit shown;

[0055] Fig.11 for Figure 9a Timing diagram of the circuit shown;

[0056] Fig.12is a schematic diagram of determining a compensation sensing value according to an embodiment of the present disclosure;

[0057] Fig.13 is a schematic diagram of determining a compensation sensing value according to another embodiment of the present disclosure;

[0058] Fig.14 FIG. 4 is a schematic diagram of determining a compensated sensing value according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0060] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0061] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0062] Figure 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure, Figure 2 for Figure 1 An exemplary structural diagram of the first shift register unit in FIG. Figure 3 for Figure 1 An exemplary structural diagram of the second shift register unit in FIG. Figure 1 to Figure 3As shown, the display panel may include a gate driving circuit and a driving integrated circuit DIC, the gate driving circuit includes a cascaded first shift register unit Sense GOA and a second shift register unit Link GOA, the first shift register unit Sense GOA is used to output a gate driving signal, a cascade control signal and a sensing driving signal, and the second shift register unit Link GOA is used to output a gate driving signal and a cascade control signal; the driving integrated circuit DIC is connected to the first shift register unit Sense GOA, and the driving integrated circuit DIC is used to obtain a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each first shift register unit SenseGOA, and determine a compensation sensing value of a pixel driving circuit of a pixel row corresponding to each second shift register unit Link GOA based on each of the sensing voltage signals by using an interpolation method or an average method.

[0063] The display panel provided by the present disclosure comprises a cascaded first shift register unit SenseGOA and a second shift register unit Link GOA in the gate driving circuit. The first shift register unit Sense GOA can output a sensing driving signal in addition to a cascade control signal and a gate driving signal, while the second shift register unit Link GOA only outputs a cascade control signal and a gate driving signal, that is, the second shift register unit Link GOA does not need to output a sensing driving signal, thereby simplifying the circuit structure of the second shift register unit Link GOA. On this basis, the driver integrated circuit DIC generates a sensing voltage signal according to the pixel driving circuit of the pixel row corresponding to each first shift register unit Sense GOA, and uses an interpolation method or an average method to determine the compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit Link GOA based on each of the sensing voltage signals, thereby realizing fast detection of each shift register unit on the basis of simplifying the circuit structure of the gate driving circuit.

[0064] The cascade control signal output by the shift register unit of the present disclosure is used to cascade the shift register units at various levels, and the gate drive signal is used to drive the pixel rows corresponding to the display area. Figure 2 , Figure 3As shown, the first shift register unit Sense GOA and the second shift register unit Link GOA may include a cascade control module 60 and a gate control module 40, wherein the cascade control module 60 is connected to the pull-up node PU, the second clock signal terminal CLKD and the cascade signal output terminal CR, and the cascade control module 60 can respond to the signal of the pull-up node PU to transmit the signal of the second clock signal terminal CLKD to the cascade signal output terminal CR for output; the gate control module 40 is connected to the pull-up node PU, the third clock signal terminal CLKE and the gate signal output terminal G, and the gate control module 40 can respond to the signal of the pull-up node PU to transmit the signal of the third clock signal terminal CLKE to the gate signal output terminal G for output. Among them, the cascade control module 60 is used to output the cascade signal, and the gate control module 40 is used to output the gate drive signal to the pixel drive circuit of the display area, that is, the gate drive signal and the cascade signal are output by two different circuit modules. Thus, the outputs of the cascade control module 60 and the gate control module 40 can be independently controlled.

[0065] In addition, in the same first shift register unit Sense GOA and the same second shift register unit Link GOA of the present disclosure, the cascade control module 60 and the gate control module 40 are both one or more, and the number of the gate control modules 40 is k times the number of the cascade control modules 60, where k is a positive integer greater than or equal to 1. When k=1, Figure 2 , Figure 3 As shown, the number of cascade control modules 60 and gate control modules 40 in the first shift register unit Sense GOA and the second shift register unit Link GOA is the same. Under this structure, the cascade signal output terminal CR of the Nth shift register unit GOA can be connected to the input terminal of the (N-1)th shift register unit GOA, that is, the cascade signal of the Nth shift register unit GOA is used as the input signal of the (N-1)th shift register unit GOA, where N is a positive integer greater than or equal to 2. When k is greater than or equal to 2, multiple gate control modules 40 in the first shift register unit Sense GOA and the second shift register unit Link GOA reuse the same cascade control module 60. Exemplarily, Figure 4 for Figure 1 Another exemplary structural diagram of the first shift register unit in FIG. Figure 5 for Figure 1 Another exemplary structural diagram of the second shift register unit in FIG. Figure 4 , Figure 5As shown, k=4, that is, the same shift register unit includes a cascade control module 60 and four gate control modules 40. In other words, in the same shift register unit, four gate control modules 40 reuse one cascade control module 60. Under this structure, one shift register unit can output four rows of gate drive signals for driving four rows of pixels for display. The cascade signal output terminal CR of the Nth-stage shift register unit GOA can be connected to the input terminal of the (N-2)th-stage shift register unit GOA, that is, the cascade signal of the Nth-stage shift register unit GOA is used as the input signal of the (N-2)th-stage shift register unit GOA, where N is a positive integer greater than or equal to 3.

[0066] The first shift register unit Sense GOA also outputs a sensing drive signal, and the pixel driving circuit outputs a sensing voltage signal under the control of the sensing drive signal, and the sensing voltage signal represents the detection result of the threshold voltage and real-time mobility of the driving transistor in the pixel driving circuit of the display area. The following is an exemplary description of the output of the sensing drive signal by the first shift register unit Sense GOA of the present disclosure, taking the 3T1C pixel driving circuit as an example. Figure 6 FIG. 1 is a schematic diagram of a circuit for sensing a pixel driving circuit according to an embodiment of the present disclosure, as shown in FIG. Figure 6 As shown, the pixel driving circuit includes a driving transistor DT, a scanning transistor CT, a sensing transistor ST and a storage capacitor Cst. The first electrode of the scanning transistor CT is connected to the data signal line Data, the second electrode is connected to the first node N1, and the gate is connected to the scanning signal line SCAN; the first electrode of the sensing transistor ST is connected to the second node N2, the second electrode is connected to the sensing signal line SL, and the gate is connected to the sensing driving signal line SEN; the first electrode of the driving transistor DT is connected to the first power supply terminal Vdd, the second electrode is connected to the second node N2, and the gate is connected to the first node N1; one end of the storage capacitor Cst is connected to the first node N1, and the other end is connected to the second node N2. The anode of the light-emitting unit OLED is connected to the second node, and the cathode is connected to the second power supply terminal Vss. The light-emitting unit OLED emits light and displays under the driving current provided by the driving transistor DT. The sensing and compensation principles of the circuit are as follows:

[0067] In the display phase of a frame of data, the sensing module in the first shift register unit Sense GOA is turned on to select the pixel row to be sensed, for example, the pixel row to be sensed is selected as the third row, and then the potential of the second electrode of the third row driving transistor DT is output by the sensing signal line SL in the Blank phase of the frame of data, that is, the sensing voltage signal. Exemplarily, the scanning transistor CT and the sensing transistor ST can be controlled to be turned on first, so as to write the data signal to the first node N1 through the scanning transistor CT and write the reference voltage signal Vref to the second electrode of the sensing transistor ST through the sensing transistor ST, and then the scanning transistor CT is controlled to be turned off and the sensing transistor ST is controlled to be turned on, and the driving transistor DT is turned on under the action of the storage capacitor Cst to charge the second node N2 with the voltage signal of the first power supply terminal Vdd, and when the second node N2 is charged to a high potential and remains unchanged, the turned-on sensing transistor ST transmits the voltage signal of the second node N2 to the sensing signal line SL, and the second electrode signal of the driving transistor DT output by the sensing signal line SL is the sensing voltage signal. After the sensing voltage signal is processed by an external circuit (the external circuit may include, for example, a timer, an analog-to-digital converter, a digital-to-analog converter, etc.), compensation information about the threshold voltage and current coefficient of the third row driving transistor DT can be obtained. Then, in the Display stage of the next frame, the compensation information obtained above is applied to the data signal, and the compensated data signal is provided by the data signal line Data, thereby realizing compensation for the threshold voltage and real-time mobility of the driving transistor DT. It should be understood that the above 3T1C pixel driving circuit is only an exemplary description, and pixel driving circuits of other structures can also perform threshold voltage sensing and compensation through the above method, that is, external compensation, which will not be described in detail here.

[0068] like Figure 2 and Figure 4 As shown, the present disclosure can set a sensing module 200 in the first shift register unit Sense GOA, and the sensing module 200 outputs the sensing drive signal in the corresponding pixel row. The second shift register unit Link GOA is only used to output the gate drive signal and the cascade control signal, that is, the driving integrated circuit DIC does not detect the threshold voltage and real-time mobility of the driving transistor in the pixel row corresponding to the second shift register unit Link GOA. Therefore, the sensing module 200 may not be set in the second shift register unit Link GOA, thereby simplifying the circuit structure of the second shift register unit Link GOA, thereby optimizing the circuit structure of the gate drive circuit as a whole, which is conducive to the realization of a narrow frame of the display panel.

[0069] In addition, because the second shift register unit Link GOA does not have the sensing module 200, the present disclosure obtains the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to each first shift register unit Sense GOA through the driving integrated circuit DIC, and the driving integrated circuit DIC then obtains the compensated sensing value through calculation according to the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to each first shift register unit Sense GOA, and then uses these compensated sensing values ​​as the threshold voltage and real-time mobility detection results of the driving transistor in each pixel row corresponding to each second shift register unit Link GOA, and uses the compensated sensing value to compensate the driving transistor in each pixel row corresponding to the second shift register unit Link GOA.

[0070] The present disclosure simplifies the circuit structure of the gate drive circuit, which is conducive to achieving a narrow frame of the panel. In addition, because the driver integrated circuit DIC only detects the threshold voltage and real-time mobility of the driving transistor in the row of pixels corresponding to the first shift register unit Sense GOA, and the pixel row corresponding to the second shift register unit Link GOA is not detected, in other words, the present disclosure only detects the threshold voltage of the driving transistor in some pixel rows, thereby reducing the detection time, especially for high-resolution panels, which can greatly reduce the detection time. The pixel rows that are not detected are replaced by the driver integrated circuit DIC to calculate the compensation sensing value through the existing sensing voltage signal to compensate the driving transistor, thereby reducing the overall compensation time, which can solve the problem of poor display uniformity caused by excessive compensation time in the prior art.

[0071] In an exemplary embodiment, the gate driving circuit may include a plurality of repeating units Q, and one repeating unit Q may include a first shift register unit Sense GOA and N second shift register units Link GOA, where N is a natural number; in the same repeating unit Q, the first shift register unit Sense GOA and each second shift register unit Link GOA are sequentially cascaded, and in any two adjacent repeating units Q, the last second shift register unit Link GOA in the previous repeating unit Q is connected to the first shift register unit Sense GOA of the next repeating unit Q. Specifically, Figure 7 FIG. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure. Figure 7 As shown, when N is 1, a second shift register unit Link GOA is distributed between two adjacent first shift register units Sense GOA, so that the first shift register unit Sense GOA and the second shift register unit Link GOA are alternately distributed in sequence. Figure 8FIG. 1 is a schematic diagram of a gate driving circuit according to another embodiment of the present disclosure. Figure 8 As shown, when N≥2, a repeating unit Q includes a first shift register unit Sense GOA and a plurality of second shift register units Link GOA. In this structure, a plurality of second shift register units Link GOA are distributed between two adjacent first shift register units Sense GOA. It should be understood that the shift register units are cascaded through the cascade control signal output by the cascade control module 60, and this exemplary embodiment only takes the cascade control signal of the Nth stage shift register unit as the input signal of the (N+2)th stage shift register unit as an example for illustrative description. In other embodiments, each shift register unit may also have other cascade modes, and the present disclosure is not limited thereto.

[0072] Figure 9a To implement an embodiment of the present disclosure Figure 4 The circuit structure diagram of the shift register unit shown in FIG. Fig.10a To implement an embodiment of the present disclosure Figure 5 The circuit structure diagram of the shift register unit shown in the figure is exemplified by taking a shift register unit including a cascade control module 60 and four gate control modules 40 as an example. The four gate control modules can be the first gate control module 41 to the fourth gate control module 44, and the four third clock signal terminals CLKE are the third clock signal terminals CLKE1 to CLKE4. Figure 9a and Fig.10a As shown, the first shift register unit Sense GOA and the second shift register unit Link GOA may also include:

[0073] The first pull-down module 10 is connected to the pull-down node PD and the pull-up node PU and receives the first level signal VGL1. The first pull-down module 10 can be used to respond to the signal of the pull-down node PD and reset the pull-up node PU using the first level signal VGL1. Exemplarily, the first pull-down module may include a fourteenth transistor M14 and a fifteenth transistor M15. The first electrode of the fourteenth transistor M14 is connected to the pull-up node PU, the second electrode is connected to the first electrode of the fifteenth transistor M15, and the gate is connected to the pull-down node PD. The second electrode of the fifteenth transistor M15 receives the first level signal VGL1, and the gate is connected to the pull-down node PD. When the pull-down node PD is at a high level, the fourteenth transistor M14 and the fifteenth transistor M15 are turned on and the pull-up node PU can be pulled down using the first level signal VGL1.

[0074] The first gate control module 41 is connected to the pull-up node PU, the first gate signal output terminal G1 and the third clock signal terminal CLKE1. The first gate control module 41 can be used to transmit the third clock signal CLKE1 to the first gate signal output terminal G1 in response to the signal of the pull-up node PU to output the first output signal. Exemplarily, the first gate control module 40 may include a twenty-sixth transistor, the first electrode of the twenty-sixth transistor is connected to the third clock signal terminal, the second electrode is connected to the first gate signal output terminal G1, and the gate is connected to the pull-up node PU. When the pull-up node PU is at a high level, the twenty-sixth transistor is turned on to output the third clock signal.

[0075] The first output reset module 51 includes a first gate signal output terminal G1 connected to the pull-down node PD and receives the second level signal VGL2. The first output reset module 51 can be used to respond to the signal of the pull-down node PD and reset the first gate signal output terminal G1 using the second level signal VGL2. Exemplarily, the first output reset module 51 can include a twenty-seventh transistor M27, the gate of the twenty-seventh transistor M27 is connected to the pull-down node PD, the first electrode is connected to the first gate signal output terminal G1, and the second electrode receives the second level signal. When the pull-down node PD is at a high level, the twenty-seventh transistor M27 is turned on and resets the first gate signal output terminal G1 using the second level signal.

[0076] The second gate control module 42 is connected to the pull-up node PU, the second gate signal output terminal G2 and the third clock signal terminal CLKE2. The second gate control module 42 can be used to respond to the signal of the pull-up node PU and transmit the signal of the third clock signal terminal CLKE2 to the second gate signal output terminal G2 to output the second output signal. Exemplarily, the second gate control module 40 may include a twenty-ninth transistor M29, the first electrode of the twenty-ninth transistor M29 is connected to the third clock signal terminal CLKE2, the second electrode is connected to the second gate signal output terminal G2, and the gate is connected to the pull-up node PU. When the pull-up node PU is at a high level, the twenty-ninth transistor M29 is turned on to transmit the signal of the third clock signal terminal CLKE2 to the second gate signal output terminal G2 for output.

[0077] The second output reset module 52 is connected to the pull-down node PD and the second gate signal output terminal G2 and receives the second level signal VGL2. The second output reset module 52 can be used to respond to the signal of the pull-down node PD and reset the second gate signal output terminal G2 using the second level signal VGL2. Exemplarily, the second output reset module can include a thirtieth transistor M30, a first electrode of the thirtieth transistor M30 is connected to the second gate signal output terminal G2, a second electrode receives the second level signal VGL2, and a gate is connected to the pull-down node PD. When the pull-down node PD is at a high level, the thirtieth transistor M30 is turned on and resets the second gate signal output terminal G2 using the second level signal VGL2.

[0078] The third gate control module 43 is connected to the pull-up node PU, the third gate signal output terminal G3 and the third clock signal terminal CLKE3. The third gate control module 43 can be used to respond to the signal of the pull-up node PU and transmit the signal of the third clock signal terminal CLKE3 to the third gate signal output terminal G3 to output the third output signal. Exemplarily, the third gate control module 43 may include a thirty-second transistor M32, the first electrode of the thirty-second transistor M32 is connected to the third clock signal terminal CLKE3, the second electrode is connected to the third gate signal output terminal G3, and the gate is connected to the pull-up node PU. When the pull-up node PU is at a high level, the thirty-second transistor M32 is turned on to transmit the signal of the third clock signal terminal CLKE3 to the third gate signal output terminal G3 for output.

[0079] The third output reset module 53 is connected to the pull-down node PD and the third gate signal output terminal G3 and receives the second level signal VGL2. The third output reset module 53 can be used to respond to the signal of the pull-down node PD and reset the third gate signal output terminal G3 using the second level signal VGL2. Exemplarily, the third output reset module may include a thirty-third transistor M33, a first electrode of the thirty-third transistor M33 is connected to the third gate signal output terminal G3, a second electrode receives the second level signal VGL2, and a gate is connected to the pull-down node PD. When the pull-down node PD is at a high level, the thirty-third transistor M33 is turned on and resets the third gate signal output terminal G3 using the second level signal VGL2.

[0080] The fourth gate control module 44 is connected to the pull-up node PU, the fourth gate signal output terminal G4 and the third clock signal terminal CLKE3. The fourth gate control module 44 can be used to respond to the signal of the pull-up node PU and transmit the signal of the third clock signal terminal CLKE3 to the fourth gate signal output terminal G4 to output the fourth output signal. Exemplarily, the fourth gate control module 40 may include a thirty-fifth transistor M35, the first electrode of the thirty-fifth transistor M35 is connected to the third clock signal terminal CLKE3, the second electrode is connected to the fourth gate signal output terminal G4, and the gate is connected to the pull-up node PU. When the pull-up node PU is at a high level, the thirty-fifth transistor M35 is turned on to transmit the signal of the third clock signal terminal CLKE3 to the fourth gate signal output terminal G4 for output.

[0081] The fourth output reset module 54 is connected to the pull-down node PD and the fourth gate signal output terminal G4 and receives the second level signal VGL2. The fourth output reset module 54 can be used to respond to the signal of the pull-down node PD and reset the fourth gate signal output terminal G4 using the second level signal VGL2. Exemplarily, the fourth output reset module may include a thirty-sixth transistor M36, the first electrode of the thirty-sixth transistor M36 is connected to the fourth gate signal output terminal G4, the second electrode receives the second level signal VGL2, and the gate is connected to the pull-down node PD. When the pull-down node PD is at a high level, the thirty-sixth transistor M36 is turned on and resets the fourth gate signal output terminal G4 using the second level signal VGL2.

[0082] The cascade control module 60 is connected to the pull-up node PU, the cascade signal output terminal CR and the second clock signal terminal CLKD3. The cascade control module 60 can be used to respond to the signal of the pull-up node PU and transmit the signal of the second clock signal terminal CLKD3 to the cascade signal output terminal CR to output the cascade control signal. Exemplarily, the cascade control module 60 may include a twenty-third transistor M23, the first electrode of the twenty-third transistor M23 is connected to the second clock signal terminal CLKD3, the second electrode is connected to the cascade signal output terminal CR, and the gate is connected to the pull-up node PU. When the pull-up node PU is at a high level, the twenty-third transistor M23 is turned on to transmit the second clock signal to the cascade signal output terminal CR for output.

[0083] The cascade output reset module 70 is connected to the pull-down node PD and the cascade signal output terminal CR and receives the first level signal VGL1. The cascade output reset module 70 can be used to respond to the signal of the pull-down node PD and transmit the first level signal VGL1 to the cascade signal output terminal CR to reset the cascade signal output terminal CR.

[0084] The first node control module 20 is connected to the pull-up node PU, the second power supply terminal GVDD2 and the first control node K1. The first node control module 20 can transmit the signal of the second power supply terminal GVDD2 to the first control node K1 in response to the signal of the pull-up node PU, so as to control the potential stability of the first control node K1. Exemplarily, the first node control module 20 may include an eleventh transistor M11, the first electrode of the eleventh transistor M11 is connected to the second power supply terminal GVDD2, the second electrode is connected to the first control node K1, and the gate is connected to the pull-up node PU. When the pull-up node PU is at a high level, the eleventh transistor M11 is turned on to transmit the signal of the second power supply terminal GVDD2 to the first control node K1.

[0085] The pull-up module 100 is connected to the input control terminal CR (N-2) and the pull-up node PU. The pull-up module 100 can be used to transmit the input control signal to the pull-up node PU in response to the input control signal provided by the input control terminal CR (N-2), so as to pull the pull-up node PU to a high level. Exemplarily, the pull-up module 100 may include a seventh transistor M7 and an eighth transistor M8, the gate and the first electrode of the seventh transistor M7 are both connected to the input control terminal CR (N-2), the second electrode is connected to the first electrode of the eighth transistor M8, the gate of the eighth transistor M8 is connected to the input control terminal CR (N-2), and the second electrode is connected to the pull-up node PU, thereby, when the input control terminal CR (N-2) is at a high level, the seventh transistor M7 and the eighth transistor M8 can transmit the high level signal to the pull-up node PU, and pull the pull-up node PU to a high level. In addition, the second electrode of the seventh transistor M7 and the first electrode of the eighth transistor M8 can be connected to the first control node K1, so that the voltage difference between the first electrode and the second electrode of the seventh transistor M7 and the voltage difference between the first electrode and the second electrode of the eighth transistor M8 are maintained stable through the first control node K1, and the pull-up node PU is prevented from leaking through the seventh transistor M7 and the eighth transistor M8. In other embodiments, the second electrode of the seventh transistor M7 and the first electrode of the eighth transistor M8 can be connected to the second control node K2. For example, Figure 9b To implement another embodiment of the present disclosure Figure 4 The circuit structure diagram of the shift register unit shown in FIG. Fig.10b To implement another embodiment of the present disclosure Figure 5 The circuit structure diagram of the shift register unit shown in FIG. Figure 9b and Fig.10bAs shown, the first shift register unit Sense GOA and the second shift register unit Link GOA may further include a second node control module 30, the second node control module 30 is connected to the second power supply terminal GVDD2 and the second control node K2 respectively, and the second node control module 30 can transmit the second voltage signal to the second control node K2 under the control of the second voltage signal provided by the second power supply terminal GVDD2, so as to control the potential of the second control node K2 to be stable, so as to stabilize the potential difference between the second control node K2 and the pull-up node and the potential difference between the second control node K2 and the first power supply terminal GVDD1, and prevent the pull-up node from leaking through the seventh transistor M7 and the eighth transistor M8. It should be understood that the input control terminal CR(N-2) described in this exemplary embodiment can be understood as the cascade signal output terminal of the (N-2)th stage shift register unit connected to the input control terminal of the Nth stage shift register unit.

[0086] The first reset module 110 is connected to the first reset control terminal TRST, the pull-up node PU and receives the first level signal VGL1. The first reset module 110 can be used to transmit the first level signal VGL1 to the pull-up node PU in response to the signal of the first reset control terminal TRST to reset the pull-up node PU. Exemplarily, the first reset module 110 may include a ninth transistor M9 and a tenth transistor M10, the gates of the ninth transistor M9 and the tenth transistor M10 are both connected to the first reset control terminal TRST, the first electrode of the ninth transistor M9 is connected to the pull-up node PU, the second electrode is connected to the first electrode of the tenth transistor M10, and the second electrode of the tenth transistor M10 receives the first level signal VGL1. Thus, when the first reset control terminal TRST is at a high level, the ninth transistor M9 and the tenth transistor M10 are turned on to pull the pull-up node PU down to a low level using the first level signal VGL1, and a reset of the pull-up node PU is completed.

[0087] The first control module 80 is connected to the third power supply terminal GVDD3 and the pull-down node PD. The first control module 80 can be used to respond to the third voltage signal provided by the third power supply terminal GVDD3 and transmit the third voltage signal to the pull-down node PD to pull the pull-down node PD up to a high level. Exemplarily, the first control module 80 can include an eighteenth transistor M18, the first electrode and the gate of the eighteenth transistor M18 are both connected to the third power supply terminal GVDD3, and the second electrode is connected to the pull-down node PD. When the third power supply terminal GVDD3 is at a high level, the eighteenth transistor M18 can transmit the high-level third voltage signal to the pull-down node PD to pull up the pull-down node PD. In other embodiments, such as Figure 9b and Fig.10bAs shown, the first control module 80 may also include a 39th transistor M39 and a 40th transistor M40, the first electrode and the gate of the 39th transistor M39 are both connected to the third power supply terminal GVDD3, the second electrode is connected to the first electrode of the 40th transistor M40, and the second electrode of the 40th transistor M40 is connected to the gate of the 18th transistor M18, and the node PD may also be pulled up and down by the third voltage signal under the control of the third voltage signal provided by the third power supply terminal GVDD3. Moreover, under this structure, the first shift register unit Sense GOA and the second shift register unit Link GOA may also include a second control module 90, the second control module 90 may be connected to the gate of the 18th transistor M18, the pull-up node PU and receive the third level signal VGL3, and the second control module 90 may turn off the 18th transistor M18 by the third level signal VGL3 under the control of the voltage signal of the pull-up node PU. The second control module 90 may include a forty-first transistor M41, a gate of the forty-first transistor M41 is connected to the pull-up node PU, a first electrode is connected to the gate of the eighteenth transistor M18, and a second electrode receives a third level signal VGL3. When the pull-up node PU is at a high level, the forty-first transistor M41 is turned on and the eighteenth transistor M18 is turned off using the third level signal VGL3.

[0088] The second reset module 150 is connected to the pull-up node PU and the second reset control terminal CR (N+6) and receives the first level signal VGL1. The second reset module 150 can be used to respond to the signal of the second reset control terminal CR (N+6) and transmit the first level signal VGL1 to the pull-up node PU to reset the pull-up node PU. Specifically, after the shift signal output is completed, the pull-up node PU can be reset by the second reset module 150. Exemplarily, the second reset module 150 may include a twelfth transistor M12 and a thirteenth transistor M13, the gates of the twelfth transistor M12 and the thirteenth transistor M13 are both connected to the second reset control terminal CR (N + 6), the first electrode of the twelfth transistor M12 is connected to the pull-up node PU, the second electrode is connected to the first electrode of the thirteenth transistor M13, the second electrode of the thirteenth transistor M13 receives the first level signal VGL1, after completing the output of the shift signal of this row, under the control of the second reset control terminal CR (N + 6), the twelfth transistor M12 and the thirteenth transistor M13 use the first level signal VGL1 to pull down the pull-up node PU, thereby resetting the pull-up node PU. It should be understood that the second reset control terminal CR (N + 6) described in this exemplary embodiment can be understood as the second reset control terminal of the cascade signal output terminal of the (N + 6)th stage shift register unit connected to the Nth stage shift register unit.

[0089] The third reset module 130 is connected to the pull-up node PU and the first pull-down node PD and receives the first level signal VGL1. The third reset module 130 can be used to transmit the first level signal VGL1 to the pull-down node PD in response to the signal of the pull-up node PU to reset the pull-down node PD. Exemplarily, the third reset module 130 may include a nineteenth transistor M19, the gate of the nineteenth transistor M19 is connected to the pull-up node PU, the first electrode is connected to the pull-down node PD, and the second electrode receives the first level signal VGL1. When the pull-up node PU is at a high level, the nineteenth transistor M19 is turned on and uses the first level signal VGL1 to reset the pull-down node PD.

[0090] The fourth reset module 140 is connected to the input control terminal CR (N-2), the pull-down node PD and receives the first level signal VGL1. The fourth reset module 140 can transmit the first level signal VGL1 to the pull-down node PD in response to the signal of the input control terminal CR (N-2) to reset the pull-down node PD when the input control terminal CR (N-2) provides an input signal. Exemplarily, the fourth reset module 140 may include a twenty-second transistor M22, the first electrode of the twenty-second transistor M22 is connected to the pull-down node PD, the second electrode receives the first level signal VGL1, and the gate is connected to the input control terminal CR (N-2). When the input control terminal CR (N-2) outputs a high level, the twenty-second transistor M22 resets the pull-down node PD using the first level signal VGL1.

[0091] The "pull-up" mentioned in the present disclosure refers to pulling the potential at the corresponding circuit node to a high level to charge the node. It can be understood that the "pull-up" can be achieved by the directional movement of charges, and therefore can be specifically achieved by electronic components with corresponding functions or a combination thereof, and the present disclosure does not impose any restrictions on this.

[0092] like Figure 9aAs shown, the first shift register unit Sense GOA may also include a sensing module 200, an isolation module 300, a leakage control module 400 and a sensing reset module 160. The sensing module 200 is connected to the sensing control terminal OE, the input control terminal CR (N-2), the first power terminal GVDD1, the pre-stored node H, the common node N and the first clock signal terminal CLKA. The sensing module 200 can respond to the signal of the sensing control terminal OE to write the signal of the input control terminal CR (N-2) into the pre-stored node H for storage, and use the signal of the pre-stored node H to transmit the signal of the first clock signal terminal CLKA to the common node N. The first power terminal can be used to prevent the sensing module 200 from leaking electricity to the pre-stored node H under the action of the signal of the pre-stored node H, thereby keeping the potential of the pre-stored node H stable. Exemplarily, the sensing module 200 may include a first transistor M1, a second transistor M2, and a third transistor M3. The first electrode of the first transistor M1 is connected to the input control terminal CR(N-2), the second electrode is connected to the first node M, and the gate is connected to the sensing control terminal OE; the first electrode of the second transistor M2 is connected to the first node M, the second electrode is connected to the pre-stored node H, and the gate is connected to the sensing control terminal OE; the first electrode of the third transistor M3 is connected to the first clock signal terminal CLKA, the second electrode is connected to the common node N, and the gate is connected to the pre-stored node H. When the sensing control terminal OE is at a high level, the first transistor M1 and the second transistor M2 are turned on, and the signal of the input control terminal CR(N-2) is transmitted to the pre-stored node H for storage. Under the action of the on-level of the pre-stored node H, the third transistor M3 is turned on to transmit the signal of the first clock signal CLKA to the common node N. The leakage control module 400 may include a fiftieth transistor M50, a first electrode of the fiftieth transistor M50 being connected to the first power supply terminal GVDD1, a second terminal being connected to the first node M, and a gate being connected to the pre-stored node H. The fiftieth transistor M50 may be turned on under the control of the voltage signal of the pre-stored node H and transmit the voltage signal of the first power supply terminal to the first node M, thereby controlling the potential difference between the first node and the pre-stored node H to be stable and preventing the second transistor M2 from leaking, thereby maintaining the potential of the pre-stored node H stable.

[0093] The isolation module 300 is connected to the common node N, the pull-up node PU and the first clock signal terminal CLKA. The isolation module 300 can be turned on to transmit the signal of the common node N to the pull-up node PU under the control of the signal of the first clock signal terminal CLKA, and then output the sensing drive signal in the sensing stage using the high level signal of the third clock signal terminal CLKE1~CLKE4 under the control of the pull-up node PU, that is, the driving transistor of any row of pixels can be compensated in any frame. Exemplarily, the isolation module 300 may include a fourth transistor M4 and a fifth transistor M5, the first electrode of the fourth transistor M4 is connected to the common node N, the second electrode is connected to the first control node K1, and the gate is connected to the first clock signal terminal CLKA; the first electrode of the fifth transistor M5 is connected to the first control node K1, the second electrode is connected to the pull-up node PU, and the gate is connected to the first clock signal terminal CLKA. When the first clock signal terminal CLKA is at a high level, the voltage signal of the common node N is transmitted to the pull-up node PU and the pull-up node PU is pulled high. At the same time, by connecting the first control node K1, the potential difference between the first control node K1 and the common node N and between the first control node K1 and the pull-up node PU can be controlled to be stable when the first clock signal terminal CLKA is at a low level, thereby preventing the fourth transistor M4 and the fifth transistor M5 from leaking electricity, thereby maintaining the potential of the common node N and the pull-up node PU stable. In other embodiments, such as Figure 9b As shown, the isolation module 300 may only include a fourth transistor M4, a gate of the fourth transistor M4 is connected to the first clock signal terminal CLKA, a first electrode is connected to the common node N, and a second electrode is connected to the pull-up node PU. When the first clock signal terminal CLKA is at a high level, the voltage signal of the common node N is transmitted to the pull-up node PU to pull up the pull-up node PU.

[0094] The sensing reset module 160 can be connected to the pull-down node PD, the pre-stored node H, and the first clock signal terminal CLKA and receive the first level signal VGL1. The sensing reset module 160 can be used to transmit the first level signal VGL1 to the pull-down node PD in response to the signal of the first clock signal terminal CLKA and the pre-stored node H to reset the pull-down node PD in the sensing stage. Exemplarily, the sensing reset module 160 can include a twentieth transistor M20 and a twenty-first transistor M21, the first electrode of the twentieth transistor M20 is connected to the pull-down node PD, the second electrode is connected to the first electrode of the twenty-first transistor M21, and the gate is connected to the first clock signal terminal CLKA, the twentieth transistor M20 can be used to turn on the first electrode and the second electrode in response to the signal of the first clock signal terminal CLKA; the second electrode of the twenty-first transistor M21 receives the first level signal VGL1, and the gate is connected to the pre-stored node H, the twenty-first transistor M21 can be used to transmit the first level signal VGL1 to the second electrode of the eleventh transistor M11 connected thereto in response to the signal of the pre-stored node H, and accordingly, the twenty-first transistor M21 is also used to reset the pull-down node PD using the first level signal VGL1.

[0095] Fig.11 for Figure 9a The timing diagram of the circuit shown, taking lines 5 to 8 as an example, the circuit works as follows:

[0096] First, the sensing control terminal OE and the first-stage input signal terminal STU are both high to reset all rows. Then in the Display stage:

[0097] (1) The third cascade signal output terminal CR <3> Being at a high potential causes PU<5-8> to be written with a high voltage and to be kept at a high potential.

[0098] (2) The second clock signal terminal CLKD7 and the third clock signal terminal CLKE5-8 are at high potential, so that the seventh cascade signal output terminal CR <7> The fifth gate signal output terminal G5 to the eighth gate signal output terminal G8 are at high potentials in sequence.

[0099] (3) Eleventh cascade signal output terminal CR <11> is a high potential, making PU<5-8> a low potential.

[0100] After shifting in sequence to complete the display of all rows in the Display phase, the Blank phase is entered. In the Blank phase, since the sensing control terminal OE has selected the row to be detected, it is only necessary to open the first clock signal terminal CLKA of the corresponding row to charge the pull-up node PU of the corresponding row, and the corresponding third clock signal terminal CLKE outputs a high level to output the sensing drive signal of the corresponding row.

[0101] by Figure 4 and Figure 9aTake the circuit shown as an example, Figure 4 and Figure 9a As shown, the driver integrated circuit DIC can detect the threshold voltage of the driving transistors of the four pixel rows corresponding to a first shift register unit Sense GOA, that is, a first shift register unit Sense GOA can output the sensing driving signal of the driving transistors of the four pixel rows. Then, after one or more second shift register units Link GOA, the driver integrated circuit DIC can detect the threshold voltage of the driving transistors of the four pixel rows corresponding to the next first shift register unit Sense GOA.

[0102] Exemplarily, taking the output of the sensing drive signal by the Nth first shift register unit Sense GOA as an example, the driver integrated circuit DIC can output the threshold voltage detection value of the driving transistor in the Nth to (N+3)th row pixels corresponding to the Nth first shift register unit Sense GOA. Then, the (N+1)th shift register unit is the second shift register unit Link GOA, and the driver integrated circuit DIC does not detect the threshold voltage of the driving transistor in the (N+4)th to (N+7)th row pixels corresponding to the (N+1)th shift register unit. Next, the (N+2)th shift register unit is the first shift register unit Sense GOA again, and the driver integrated circuit DIC can output the threshold voltage detection value of the driving transistor in the (N+8)th to (N+11)th row pixels corresponding to the (N+2)th shift register unit, and so on.

[0103] Under this structure, the driver integrated circuit DIC can calculate compensation values ​​based on the threshold voltage values ​​actually detected in the Nth to (N+3)th rows, (N+8)th to (N+11)th rows, etc., and use these compensation values ​​as compensation sensing values ​​of the threshold voltages of the driving transistors in the undetected pixel rows, such as the (N+4)th to (N+7)th rows, (N+12)th to (N+15)th rows, corresponding to each second shift register unit Link GOA, and perform threshold compensation on the driving transistors in the pixel rows that have not been actually detected based on the compensation sensing values.

[0104] Below Figure 9a and Fig.10a The circuit structure shown forms Figure 7 The gate driving circuit shown is taken as an example to further introduce the solution of determining the compensated sensing value based on the sensed voltage signal that has been detected in the present disclosure.

[0105] In an exemplary embodiment, the driver integrated circuit DIC may use an interpolation method to determine the threshold voltage compensation value of the driving transistor in the pixel row corresponding to the second shift register unit Link GOA. Specifically, after acquiring the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to each first shift register unit Sense GOA, the driver integrated circuit DIC uses the interpolation method to determine the compensation sensing value of the pixel driving circuit corresponding to each second shift register unit Link GOA based on the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to each first shift register unit Sense GOA.

[0106] In an exemplary embodiment, Fig.12 FIG. 1 is a schematic diagram of determining a compensated sensing value according to an embodiment of the present disclosure. In the figure, the ordinate represents the sensing value, and the abscissa represents the pixel row. Fig.12 As shown, the pixel rows corresponding to the sensing driving signals output by each first shift register unit Sense GOA are respectively the Nth to (N+3)th rows, (N+8)th to (N+11)th rows, (N+16)th to (N+19)th rows..., Mth to (M+3)th rows..., then the driving integrated circuit DIC can obtain the compensation sensing values ​​of the driving transistors in the (N+4)th to (N+7)th rows, (N+12)th to (N+15)th rows, (N+20)th to (N+23)th rows... which are not detected by the interpolation method after obtaining the sensing voltage signals of the above pixel rows. Because the compensation difference between adjacent rows is small, the interpolation calculation result, i.e., the compensation sensing value, can reflect the sensing values ​​of those undetected pixel rows, thereby saving the sensing time for these rows. In this way, the compensation sensing value is used to compensate the threshold voltage of the driving transistor, and the time required for compensating all the pixel rows of the panel is greatly compressed, thereby simplifying the circuit structure to achieve a narrow frame while achieving fast sensing and fast compensation.

[0107] In an exemplary embodiment, the driver integrated circuit DIC can also determine the first average value of the sensing voltage signal generated by the pixel driving circuit of the pixel rows corresponding to two adjacent first shift register units Sense GOA based on the sensing voltage signal generated by the pixel driving circuit of the pixel rows corresponding to each first shift register unit SenseGOA, and then determine the first average value as the compensation sensing value of the pixel row corresponding to the second shift register unit Link GOA located between the two adjacent first shift register units Sense GOA.

[0108] For example, Fig.13 FIG. 1 is a schematic diagram of determining a compensated sensing value according to another embodiment of the present disclosure. In the figure, the ordinate represents the sensing value, and the abscissa represents the pixel row. Fig.13As shown, the pixel rows corresponding to the sensing drive signals output by each first shift register unit Sense GOA are respectively the Nth to (N+3)th rows, the (N+8)th to (N+11)th rows, the (N+16)th to (N+19)th rows, ..., then after acquiring the sensing voltage signals of the above pixel rows, the driving integrated circuit DIC can sequentially calculate the first average values ​​of the sensing voltage signals of each pixel row corresponding to the first shift register unit Sense GOA in each repeating unit Q, and then determine the first average value as the compensation sensing value of each pixel row corresponding to the second shift register unit Link GOA in the same repeating unit Q. For example, the pixel rows corresponding to the first shift register unit Sense GOA in the first repeating unit Q are the Nth to (N+3)th rows, then the driving integrated circuit DIC can calculate the average of the sensing voltage signals of the Nth to (N+3)th rows as the first average value K1, and then use the first average value K1 as the compensation sensing value of the pixel rows corresponding to each second shift register unit Link GOA in the first repeating unit Q, that is, the compensation sensing values ​​of the pixel rows corresponding to each second shift register unit Link GOA in the first repeating unit Q (that is, the (N+4)th to (N+7)th rows) are all the average of the sensing voltage signals of the Nth to (N+3)th rows. Similarly, the pixel rows corresponding to the first shift register unit Sense GOA in the second repeating unit Q are the (N+8)th to (N+11)th rows, and the driver integrated circuit DIC can calculate the first average value K1' of the sensing voltage signal of the (N+8)th to (N+11)th rows, and then use the first average value K1' as the compensation sensing value of the pixel rows corresponding to each second shift register unit Link GOA in the second repeating unit Q (i.e., the (N+12)th to (N+15)th rows), that is, the compensation sensing values ​​of the pixel rows corresponding to each second shift register unit Link GOA in the second repeating unit Q (i.e., the (N+12)th to (N+15)th rows) are all the first average values ​​of the sensing voltage signal of the (N+8)th to (N+11)th rows. In this way, the driver integrated circuit DIC sequentially determines the compensation sensing values ​​of the pixel rows corresponding to each second shift register unit Link GOA.

[0109] In an exemplary embodiment, after obtaining the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to each first shift register unit Sense GOA, the driving integrated circuit DIC can also determine the second average value of the sensing voltage signal of each pixel row corresponding to two adjacent first shift register units Sense GOA, and then determine the second average value as the compensation sensing value of each pixel row corresponding to the second shift register unit Link GOA located in the two adjacent first shift register units Sense GOA.

[0110] For example, Fig.14FIG. 1 is a schematic diagram of determining a compensated sensing value according to another embodiment of the present disclosure. In the figure, the ordinate represents the sensing value, and the abscissa represents the pixel row. Fig.14 As shown, the pixel rows corresponding to the sensing driving signals output by each first shift register unit Sense GOA are respectively the Nth to (N+3)th rows, the (N+8)th to (N+11)th rows, the (N+16)th to (N+19)th rows, ..., then after obtaining the sensing voltage signals of the above pixel rows, the driving integrated circuit DIC can sequentially calculate the average values ​​of the sensing voltage signals output by two adjacent first shift register units Sense GOA, recorded as the second average value, and then use the second average value as the compensation sensing value of the pixel row corresponding to the second shift register unit Link GOA located between the two first shift register units Sense GOA. For example, the driving integrated circuit DIC can calculate the average of the sensing voltage signals of the Nth to (N+3)th rows and the (N+8)th to (N+11)th rows as the second average value K2 based on the sensing voltage signals generated by the pixel driving circuits of the pixel rows corresponding to the first shift register unit Sense GOA in the first repeating unit Q and the first shift register unit Sense GOA in the second repeating unit Q. The second average value K2 is used as the compensation sensing value of the threshold voltage of the driving transistors of the (N+4)th to (N+7)th rows corresponding to the second shift register unit Link GOA in the first repeating unit Q, that is, the threshold voltages of the driving transistors in the pixels of the (N+4)th, (N+5)th, (N+6)th and (N+7)th rows are all compensated using the second average value K2 obtained from the sensing voltage signals of the Nth to (N+3)th rows and the (N+8)th to (N+11)th rows. Similarly, the driving integrated circuit DIC can calculate the second mean value K2' of the sensing voltage signals of the (N+8)th to (N+11)th rows and the (N+16)th to (N+19)th rows. The second mean value K2' is used as the compensation sensing value of the threshold voltage of the driving transistors of the (N+12)th to (N+15)th rows, that is, the threshold voltage sensing values ​​of the driving transistors in the pixels of the (N+12)th, (N+13)th, (N+14)th and (N+15)th rows are all the second mean value K2' of the sensing voltage signals of the (N+8)th to (N+11)th and (N+16)th to (N+19)th rows.

[0111] It can be seen that in Figure 7 In the gate driving circuit shown in the figure, the compensation time for the driving transistor in the pixel row can be halved as a whole, so as to realize fast sensing and fast compensation. Of course, in other embodiments, the specific sensing time that can be saved depends on the ratio of the number of the first shift register unit Sense GOA to the second shift register unit Link GOA in the gate driving circuit, and after the ratio of the number of the two shift register units changes, the same can be based on Figure 12 to Figure 14 The method shown performs threshold voltage compensation on the driving transistors in the pixel rows corresponding to the second shift register unit Link GOA.

[0112] The present disclosure further provides a display panel driving method, which can be executed by a driver integrated circuit DIC to drive the display panel described in any of the above embodiments of the present disclosure. The driving method may include the following steps:

[0113] S110 , obtaining a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each first shift register unit Sense GOA.

[0114] S120 , determining a compensation sensing value of a pixel driving circuit corresponding to each second shift register unit Link GOA based on each sensing voltage signal.

[0115] In an exemplary embodiment, this step may be specifically performed as follows: Fig.12 As shown, the interpolation method is used to determine the compensation sensing value of the pixel row corresponding to the second shift register unit Link GOA located between the two adjacent first shift register units Sense GOA based on the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to the two adjacent first shift register units Sense GOA. The specific principle of compensation by the interpolation method can be found in the introduction of the above embodiment, which will not be repeated here.

[0116] In an exemplary embodiment, if Fig.13 As shown, this step may also include: determining a first average value of the sensing voltage signal of each pixel row corresponding to the first shift register unit Sense GOA in each repeating unit; and determining the first average value as the compensation sensing value of each pixel row corresponding to the second shift register unit Link GOA in the same repeating unit.

[0117] In an exemplary embodiment, if Fig.14 As shown, this step may also include: determining a second mean value of the sensing voltage signal of each pixel row corresponding to two adjacent first shift register units Sense GOA; determining the second mean value as the compensation sensing value of each pixel row corresponding to the second shift register unit Link GOA between the two adjacent first shift register units Sense GOA.

[0118] The specific principle of determining the first mean value, the second mean value and using the first mean value and the second mean value for compensation can be found in the introduction of the above embodiment, which will not be described in detail here.

[0119] S130 , using the compensation sensing value to perform threshold voltage compensation on the driving transistors in the pixel rows corresponding to each second shift register unit Link GOA.

[0120] The driving method disclosed in the present invention is optimized through algorithms, and the time required for performing compensation on all pixel rows of a panel is greatly compressed, thereby enabling rapid sensing and rapid compensation of narrow-framed panels.

[0121] In addition, the present disclosure also provides a display device, which may include the display panel described in any of the above embodiments of the present disclosure.

[0122] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the generality of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

Claims

1. A display panel, characterized in that: include: A gate driving circuit, the gate driving circuit comprising a first shift register unit and a second shift register unit connected in cascade, the first shift register unit being used to output a gate driving signal, a cascade control signal and a sensing driving signal, and the second shift register unit being used to output a gate driving signal and a cascade control signal; the first shift register unit can output sensing driving signals of a pixel driving circuit having the same number as the corresponding plurality of pixel rows; A driving integrated circuit is connected to each pixel driving circuit, and the driving integrated circuit is used to obtain the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to each first shift register unit, and use an interpolation method or an averaging method to determine the compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit based on each of the sensing voltage signals.

2. The display panel according to claim 1, characterized in that: The gate driving circuit includes a plurality of repeating units, wherein the repeating unit includes a first shift register unit and N second shift register units, where N is a natural number; In the same repeating unit, the first shift register unit and each second shift register unit are cascaded in sequence; In any two adjacent repeating units, the last-stage second shift register unit in the previous repeating unit is connected to the first shift register unit in the next repeating unit.

3. The display panel according to claim 1, characterized in that: The first shift register unit and the second shift register unit both include: A cascade control module, connected to the pull-up node, the second clock signal terminal and the cascade signal output terminal, the cascade control module is used to respond to the signal of the pull-up node to transmit the signal of the second clock signal terminal to the cascade signal output terminal for output; The gate control module is connected to the pull-up node, the third clock signal terminal and the gate signal output terminal, and is used to respond to the signal of the pull-up node to transmit the signal of the third clock signal terminal to the gate signal output terminal for output.

4. The display panel according to claim 3, characterized in that: In the same first shift register unit and the same second shift register unit, the cascade control module and the gate control module are both one or more, and the number of the gate control modules is k times the number of the cascade control modules, where k is a positive integer greater than or equal to 1.

5. The display panel according to claim 3, characterized in that: The first shift register unit further includes: A sensing module connected to the input terminal, the sensing control terminal, the pre-stored node, the common node and the first clock signal terminal, the sensing module being used to write the signal of the input terminal into the pre-stored node for storage in response to the signal of the sensing control terminal, and to transmit the signal of the first clock signal terminal to the common node in response to the signal of the pre-stored node; a leakage control module connected to the first power supply end, the first node and the pre-stored node, the leakage control module being used to transmit the signal of the first power supply end to the first node in response to the signal of the pre-stored node, so as to stabilize the potential difference between the node and the common node; An isolation module is connected to the common node, the pull-up node and the first clock signal terminal, and the isolation module is used to respond to the signal of the first clock signal terminal to turn on the common node and the pull-up node, so as to control the gate control module to output the sensing drive signal through the pull-up node.

6. The display panel according to claim 5, characterized in that: The sensing module comprises: A first transistor, a first electrode connected to the input terminal, a second electrode connected to the first node, and a gate connected to the sensing control terminal; A second transistor, a first electrode connected to the first node, a second electrode connected to the pre-stored node, and a gate connected to the sensing control terminal; A storage capacitor, one end of which is connected to the pre-storage node, and the other end of which receives a first level signal; a third transistor, a first electrode connected to the first clock signal terminal, a second electrode connected to the common node, and a gate connected to the pre-stored node; The leakage control module comprises: a fiftieth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first node, and a gate connected to the pre-stored node, the fiftieth transistor being used to transmit a signal from the first power supply terminal to the first node in response to a signal from the pre-stored node, so as to stabilize a potential difference between the first node and the pre-stored node; The isolation module comprises: a fourth transistor, a first electrode connected to the common node, a second electrode connected to the first control node, and a gate connected to the first clock signal terminal; A fifth transistor has a first electrode connected to the first control node, a second electrode connected to the pull-up node, and a gate connected to the first clock signal terminal.

7. The display panel according to claim 1, characterized in that: The driver integrated circuit is also used for: Acquiring a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each of the first shift register units; The interpolation method is used to determine the compensation sensing value of the pixel driving circuit corresponding to the pixel row corresponding to each of the second shift register units based on the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to each of the first shift register units.

8. The display panel according to claim 7, characterized in that: The driver integrated circuit is also used for: Acquiring a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each of the first shift register units; The interpolation method is used to determine the compensation sensing value of the pixel driving circuit of the pixel row corresponding to the second shift register unit located between the two adjacent first shift register units based on the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to the two adjacent first shift register units.

9. The display panel according to claim 2, characterized in that: The driver integrated circuit is also used for: Acquiring a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each of the first shift register units; Determine a first average value of a sensing voltage signal generated by a pixel driving circuit of each pixel row corresponding to the first shift register unit in each repetitive unit; The first average value is determined as a compensation sensing value of a pixel driving circuit of each pixel row corresponding to the second shift register unit in the same repetitive unit.

10. The display panel according to claim 1, characterized in that: The driver integrated circuit is also used for: Acquiring a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each of the first shift register units; Determine a second average value of the sensing voltage signal generated by the pixel driving circuit corresponding to each pixel row of two adjacent first shift register units; The second average value is determined as a compensation sensing value of a pixel driving circuit of each pixel row corresponding to the second shift register unit between the two adjacent first shift register units.

11. A display panel driving method, characterized in that: Used to drive the display panel according to any one of claims 1 to 10, the driving method comprising: Acquiring a sensing voltage signal generated by a pixel driving circuit of a pixel row corresponding to each of the first shift register units; Determine the compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit based on each sensing voltage signal by using an interpolation method or an average method; The compensation sensing value is used to perform threshold voltage compensation on the driving transistors in the pixel rows corresponding to each of the second shift register units.

12. The method according to claim 11, characterized in that The method of determining the compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit based on each sensing voltage signal includes: The interpolation method is used to determine the compensation sensing value of the pixel driving circuit of the pixel row corresponding to the second shift register unit located between the two adjacent first shift register units based on the sensing voltage signal generated by the pixel driving circuit of the pixel row corresponding to the two adjacent first shift register units.

13. The method according to claim 11, characterized in that The method of determining the compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit based on each sensing voltage signal includes: Determine a first average value of a sensing voltage signal generated by a pixel driving circuit of each pixel row corresponding to the first shift register unit in each repetitive unit; The first average value is determined as a compensation sensing value of a pixel driving circuit of each pixel row corresponding to the second shift register unit in the same repetitive unit.

14. The method according to claim 11, characterized in that The method of determining the compensation sensing value of the pixel driving circuit of the pixel row corresponding to each second shift register unit based on each sensing voltage signal includes: Determine a second average value of the sensing voltage signal generated by the pixel driving circuit corresponding to each pixel row of two adjacent first shift register units; The second average value is determined as a compensation sensing value of a pixel driving circuit of each pixel row corresponding to the second shift register unit between the two adjacent first shift register units.

15. A display device, characterized in that: A display panel comprising any one of claims 1 to 10.

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