A current detection port time division multiplexing circuit, switching power supply controller and switching power supply

Abstract

The present invention discloses a current-sense port time-division multiplexing circuit, a switching power supply controller, and a switching power supply. The current-sense port time-division multiplexing circuit has seven ports, namely, a PVDD terminal, an EXTOTP terminal, an OCP terminal, a CSSCP terminal, an EN terminal, a GATE_ON terminal, and a CS terminal; the current-sense port time-division multiplexing circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first comparator, a second comparator, a third comparator, an inverter, a first delay, a second delay, a third delay, a first AND gate, a second AND gate, a third AND gate, a first D flip-flop, and a second D flip-flop. The present invention can implement over-temperature protection (OTP), over-current protection (OCP), and CS terminal current-sense resistor short-circuit protection (CSSCP) by time-division multiplexing the CS port sampling signal, thereby ensuring that the switching power supply controller is shut down when the switching power supply system experiences over-temperature, over-current, or a CS terminal resistor short-circuit. Therefore, the present invention greatly guarantees the safety of user electrical equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a current detection port time division multiplexing circuit, a switching power supply controller and a switching power supply. Background Art

[0002] With the rapid development of electronic technology, electronic devices are becoming increasingly intertwined with people's lives and work. Power supplies are the heart of every electrical device; wherever there are electrical appliances, there's a power supply. Power supplies, as the power supply for portable electronic products, are constantly evolving towards miniaturization, safety, and high efficiency. Consequently, products in the small SOT23-6L package are becoming increasingly popular. However, given the limited number of pins and the need for safety, achieving comprehensive protection features presents new challenges in pin reuse.

[0003] In traditional ACDC chips, the current-sense port CS is only used to detect the primary-side inductor current to implement pulse-width modulation (PWM) control and overcurrent detection (OCP). It does not implement other protection functions, resulting in low pin utilization and poor product safety. Summary of the Invention

[0004] The purpose of the present invention is to provide a current sensing port time division multiplexing circuit, a switching power supply controller and a switching power supply, which realize over-temperature protection, over-current protection and CS terminal current sensing resistor short-circuit protection by time division multiplexing the CS port sampling signal.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A current-sense port time-division multiplexing circuit, the current-sense port time-division multiplexing circuit having seven ports, namely a PVDD terminal, an EXTOTP terminal, an OCP terminal, a CSSCP terminal, an EN terminal, a GATE_ON terminal, and a CS terminal; the current-sense port time-division multiplexing circuit comprising a first resistor, a second resistor, a third resistor, a fourth resistor, a first comparator, a second comparator, a third comparator, an inverter, a first delay device, a second delay device, a third delay device, a first AND gate, a second AND gate, a third AND gate, a first D flip-flop, and a second D flip-flop;

[0007] One end of the first resistor, the power supply end of the first comparator, the power supply end of the second comparator, the power supply end of the third comparator, and the D input end of the second D flip-flop are all connected to the PVDD end; the first output end of the first D flip-flop is connected to the EXTOTP end; the output end of the first AND gate is connected to the OCP end; the output end of the third AND gate is connected to the CSSCP end; the enable end of the first comparator, the enable end of the second comparator, the enable end of the third comparator, the reset end of the first D flip-flop, the reset end of the second D flip-flop, and the input end of the third delay are all connected to the EN end; the input end of the inverter, the input end of the second delay, and the second input end of the second AND gate are all connected to the GATE_ON end; the positive input end of the first comparator, the positive input end of the second comparator, and the positive input end of the third comparator are all connected to the CS end;

[0008] The other end of the first resistor is respectively connected to one end of the second resistor and the inverting input end of the first comparator; the other end of the second resistor is respectively connected to one end of the third resistor and the inverting input end of the second comparator; the other end of the third resistor is respectively connected to one end of the fourth resistor and the inverting input end of the third comparator; the other end of the fourth resistor is grounded; the output end of the first comparator is connected to the D input end of the first D flip-flop, and the clock end of the first D flip-flop is connected to the output end of the first delay device; the output end of the second comparator is connected to the first input end of the first AND gate; the second input end of the first AND gate is connected to the output end of the second delay device; the output end of the third comparator is connected to the first input end of the second AND gate; the output end of the second AND gate is connected to the clock end of the second D flip-flop; the second output end of the second D flip-flop is connected to the first input end of the third AND gate; and the second input end of the third AND gate is connected to the output end of the third delay device.

[0009] Optionally, the EN terminal is used to set the internal circuit to an initial logic high; the CS terminal and the GATE_ON terminal generate an over-temperature protection control enable signal at the EXTOTP terminal; the CS terminal and the GATE_ON terminal generate an over-current protection control enable signal at the OCP terminal; the CS terminal and the GATE_ON terminal generate a short-circuit protection enable signal at the CS terminal at the CSSCP terminal.

[0010] The present invention also provides a switching power supply controller, comprising: the above-mentioned current detection port time division multiplexing circuit, the power-on and power-off enabling circuit, the internal power supply circuit, the pulse width modulator, the logic control circuit and the driving circuit;

[0011] The PVDD terminal of the current-sense port time-division multiplexing circuit is respectively connected to the output terminal of the internal power supply circuit, the fourth input terminal of the pulse modulation circuit, and the second input terminal of the logic control circuit; the EN terminal of the current-sense port time-division multiplexing circuit is connected to the output terminal of the upper and lower power enabling circuit, the third input terminal of the pulse width modulator, the third input terminal of the logic control circuit, and the second input terminal of the driving circuit; the CS terminal of the current-sense port time-division multiplexing circuit is connected to the second input terminal of the pulse width modulator; the CS terminal of the current-sense port time-division multiplexing circuit is the input terminal of the switching power supply controller; the GATE_ON terminal of the current-sense port time-division multiplexing circuit is connected to the output terminal of the logic control circuit and the first input terminal of the driving circuit; the OCP terminal of the current-sense port time-division multiplexing circuit is connected to the fourth input terminal of the logic control circuit; the EXTOTP terminal of the current-sense port time-division multiplexing circuit is connected to the fifth input terminal of the logic control circuit; and the CSSCP terminal of the current-sense port time-division multiplexing circuit is connected to the sixth input terminal of the logic control circuit.

[0012] The output end of the upper and lower power enabling circuit is also connected to the first input end of the internal power supply circuit; the input ends of the upper and lower enabling circuits are respectively connected to the VDD end of the switching power supply controller, the second input end of the internal power supply circuit and the third input end of the drive circuit; the first input end of the pulse width modulator is connected to the FB end of the switching power supply controller; the output end of the pulse width modulator is connected to the first input end of the logic control circuit; the output end of the logic control circuit is also connected to the first end of the drive circuit; and the output end of the drive circuit is connected to the GATE end of the switching power supply controller.

[0013] The present invention also provides a switching power supply, comprising: a transformer, a power switch tube, a feedback device, an NTC resistor, a rectifier diode, a first current-sensing resistor, and a second current-sensing resistor; and also comprising the switching power supply controller mentioned above;

[0014] The FB terminal of the switching power supply controller is connected to the output terminal of the feedback device, and the CS terminal of the switching power supply controller is respectively connected to one end of the second current sensing resistor and the output end of the rectifier diode; the GATE terminal of the switching power supply controller is connected to the gate of the power switch tube.

[0015] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0016] The current-sense port time-division multiplexing circuit provided by the present invention implements over-temperature protection (OTP), over-current protection (OCP), and CS-terminal current-sense resistor short-circuit protection (CSSCP) by time-division multiplexing the CS port sampling signal. This ensures that the switching power supply controller is shut down in the event of overtemperature, overcurrent, or a CS-terminal resistor short-circuit in the switching power supply system. Therefore, the present invention significantly enhances the safety of user electrical devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is a schematic diagram of a traditional switching power conversion system;

[0019] Figure 2 A circuit diagram of the switching power supply provided by the present invention;

[0020] Figure 3 A connection diagram of the current detection port time division multiplexing circuit provided by the present invention;

[0021] Figure 4 This is the CS port short circuit protection control timing diagram;

[0022] Figure 5 This is the timing diagram of overcurrent protection and overtemperature protection control;

[0023] Description of main component symbols:

[0024] 10: Traditional switching power supply

[0025] 10A: Switching power supply of the present invention

[0026] 12: Feedback

[0027] 13: Traditional switching power supply controller

[0028] 13A: Switching power supply controller of the present invention

[0029] 131: UVLO circuit

[0030] 132: Internal power supply circuit (LDO)

[0031] 133: Pulse Width Modulator (PWM)

[0032] 134: Logic Control Circuit (LOGIC) in Traditional Switching Power Supply Controller

[0033] 134A: Logic Control Circuit (LOGIC) in the Switching Power Supply Controller of the Present Invention

[0034] 135: Drive circuit (DRIVER)

[0035] 136: Overcurrent protection circuit

[0036] 136A: Current-sensing port time-division multiplexing circuit

[0037] M1: external power switch tube

[0038] TR: Transformer

[0039] LP: Primary coil of TR

[0040] LS: secondary coil of TR

[0041] LA: TR's auxiliary coil, responsible for powering the capacitor C4 of the VDD port

[0042] D1: Full-wave rectifier diode for AC input

[0043] D2 / D3 / D4 / D5: diodes

[0044] R7: NTC resistor for 10A switching power supply

[0045] R1 / R2 / R3 / R4 / R8 / R21 / R22 / R23 / R24: resistors

[0046] C1 / C2 / C3 / C4: capacitors

[0047] 22 / 25 / 28: First comparator (C1), second comparator (C2), third comparator (C3); when the enable signal is logic high, the output terminal is in phase with the positive input terminal, that is, when the positive terminal voltage is higher than the reverse input terminal voltage, the output is logic high, otherwise the output is logic low; when the enable signal is logic low, the output signal is logic low

[0048] 21: Reverse

[0049] 26 / 29 / 31: AND Gate

[0050] 23 / 30: D flip-flop with clear terminal, rising edge triggered

[0051] 24: First delay (DELAY1)

[0052] 27: Second delay (DELAY2)

[0053] 32: Third delay 3 (DELAY3)

[0054] VDD: power supply port or VDD voltage

[0055] FB: Feedback port

[0056] CS: Current detection port or CS voltage

[0057] GATE: drive output port

[0058] GND: Ground port

[0059] VAC: Input line voltage

[0060] Vo: DC output voltage of the switching power supply system 10

[0061] PVDD: Output signal generated by internal power supply LDO

[0062] EN: Enable signal output by the UVLO function block

[0063] GATE_ON: output signal of logic control module

[0064] GATE_OFF: The reverse signal of GATE_ON

[0065] EXTOTP: Over-temperature protection enable signal

[0066] OCP: Overcurrent protection control signal or overcurrent protection

[0067] CSSCP: CS port short circuit protection enable signal

[0068] OTP: Over Temperature Protection

[0069] vref1: reference voltage 1

[0070] vref2: reference voltage 2

[0071] vref3: reference voltage 3

[0072] VCS: CS terminal voltage value

[0073] VLA: auxiliary coil voltage value

[0074] TD1: output signal of the first delay device DELAY1

[0075] TD2: output signal of the second delay device DELAY2

[0076] TD3: output signal of the third delay device DELAY3

[0077] T3: CS port short circuit protection detection time

[0078] Tdebounce: CS port short circuit protection debounce time

[0079] "1": Logic high

[0080] "0": logic low DETAILED DESCRIPTION

[0081] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0082] Traditional switching power conversion systems such as Figure 1 As shown, the input terminal of the EMI Filter 11 is connected to the input AC voltage VAC, and the output terminal is respectively connected to the first and third terminals of D1; the second terminal of D1 is connected to the first terminal of C1, the first terminal of R1, the first terminal of R2, the first terminal of C2, and the opposite-name terminal of the primary winding LP of the transformer TR; the fourth terminal of D1 is connected to the second terminal of C1 and the ground signal; the second terminal of R1 is connected to the first terminal of R3, the first terminal of C4, and the VDD terminal of the traditional switching power supply controller 13; the second terminal of R3 is connected to the first terminal of D4; the second terminal of D4 is connected to the same-name terminal of the auxiliary winding LA of the transformer TR; the opposite-name terminal of the auxiliary winding LA of the transformer TR The second end of terminal C4 is connected to the ground signal; the second end of R2 is connected to the second end of C2 and the first end of D2; the second end of D2 is connected to the same-name end of the primary coil LP of the transformer TR and the D end of the power tube M1; the G end of the power tube M1 is connected to the GATE end of the traditional switching power supply controller 13, and the S end is connected to the first end of R4 and the CS end of the traditional switching power supply controller 13; the second end of R4 is connected to the ground signal; the same-name end of the secondary coil LS of the transformer TR is connected to the second end of D3, and the opposite-name end is connected to the second end of C3 and the ground signal; the first end of D3 is connected to the first end of C3 and the input end of FeedBack 12; the output end of FeedBack 12 is connected to the FB end of the traditional switching power supply controller 13; the GND end of the traditional switching power supply controller 13 is connected to the ground signal.

[0083] In traditional switching power supply conversion systems, the current-sense port CS is only used to detect the primary-side inductor current to implement pulse-width modulation (PWM) control and overcurrent detection (OCP). It does not implement other protection functions, resulting in low pin utilization and poor product safety.

[0084] The purpose of the present invention is to provide a current sensing port time division multiplexing circuit, a switching power supply controller and a switching power supply, which realize over-temperature protection, over-current protection and CS terminal current sensing resistor short-circuit protection by time division multiplexing the CS port sampling signal.

[0085] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0086] like Figure 3 As shown, the current-sense port time-division multiplexing circuit provided by the present invention has seven ports, namely, a PVDD terminal, an EXTOTP terminal, an OCP terminal, a CSSCP terminal, an EN terminal, a GATE_ON terminal, and a CS terminal; the current-sense port time-division multiplexing circuit includes a first resistor R21, a second resistor R22, a third resistor R23, a fourth resistor R24, a first comparator (C1) 22, a second comparator (C2) 25, a third comparator (C3) 28, an inverter 21, a first delay (DELAY1) 24, a second delay (DELAY2) 27, a third delay (DELAY3) 32, a first AND gate 26, a second AND gate 29, a third AND gate 31, a first D flip-flop 23, and a second D flip-flop 30.

[0087] One end of the first resistor R21, the power supply terminal of the first comparator 22, the power supply terminal of the second comparator 25, the power supply terminal of the third comparator 28, and the D input terminal of the second D flip-flop 23 are all connected to the PVDD terminal. The first output terminal of the first D flip-flop 23 is connected to the EXTOTP terminal; the output terminal of the first AND gate 26 is connected to the OCP terminal; the output terminal of the third AND gate 31 is connected to the CSSCP terminal; the enable terminal of the first comparator 22, the enable terminal of the second comparator 25, the enable terminal of the third comparator 28, the reset terminal of the first D flip-flop 23, the reset terminal of the second D flip-flop 30, and the input terminal of the third delay 32 are all connected to the EN terminal; the input terminal of the inverter 21, the input terminal of the second delay 27, and the second input terminal of the second AND gate 26 are all connected to the GATE_ON terminal; and the positive input terminal of the first comparator 22, the positive input terminal of the second comparator 25, and the positive input terminal of the third comparator 28 are all connected to the CS terminal.

[0088] The other end of the first resistor R21 is connected to one end of the second resistor R22 and the inverting input of the first comparator 22, respectively. The other end of the second resistor R22 is connected to one end of the third resistor R23 and the inverting input of the second comparator 25, respectively. The other end of the third resistor R23 is connected to one end of the fourth resistor R24 and the inverting input of the third comparator 28, respectively. The other end of the fourth resistor R24 is grounded. The output of the first comparator 22 is connected to the D input of the first D flip-flop 23, and the clock terminal of the first D flip-flop 23 is connected to the output of the first delay 24. The output of the second comparator 25 is connected to the first input of the first AND gate 26. The second input of the first AND gate 26 is connected to the output of the second delay 27. The output of the third comparator 28 is connected to the first input of the second AND gate 29. The output of the second AND gate 29 is connected to the clock terminal of the second D flip-flop 30. The second output of the second D flip-flop 30 is connected to the first input of the third AND gate 31. The second input of the third AND gate 31 is connected to the output of the third delay 32.

[0089] The EN terminal in the current-sense port time-division multiplexing circuit is used to initially set the internal circuit to a logic high. The CS terminal and the GATE_ON terminal generate an over-temperature protection control enable signal EXTOTP at the EXTOTP terminal. The CS terminal and the GATE_ON terminal generate an over-current protection control enable signal OCP at the OCP terminal. The CS terminal and the GATE_ON terminal generate a CS terminal short-circuit protection enable signal CSSCP at the CSSCP terminal. The control signals EXTOTP, OCP, and CSSCP ensure that the switching power supply controller is shut down in the event of overtemperature, overcurrent, or a short circuit in the CS terminal resistor. Therefore, this invention significantly enhances the safety of user electrical devices.

[0090] like Figure 2 As shown, the present invention further provides a switching power supply controller 13A, comprising: the aforementioned current sensing port time division multiplexing circuit (TDM Protection) 136A, the upper and lower power enabling circuit (UVLO) 131, the internal power supply circuit (LDO) 132, the pulse width modulator (PWM) 133, the logic control circuit (LOGIC) 134A, and the driver circuit (DRIVER) 135. The current sensing port time division multiplexing circuit 136A, the upper and lower power enabling circuit 131, the internal power supply circuit 132, the pulse width modulator 133, the logic control circuit 134A, and the driver circuit 135 are embedded in an integrated circuit to save external components.

[0091] The PVDD terminal of the current-sense port time-division multiplexing circuit 136A is connected to the output terminal of the internal power supply circuit 132, the fourth input terminal of the pulse modulation circuit 133, and the second input terminal of the logic control circuit 134A respectively; the EN terminal of the current-sense port time-division multiplexing circuit 136A is connected to the output terminal of the power-on and power-off enabling circuit 131, the third input terminal of the pulse width modulator 133, the third input terminal of the logic control circuit 134A, and the second input terminal of the driving circuit 135; the CS terminal of the current-sense port time-division multiplexing circuit 136A is connected to the second input terminal of the pulse width modulator 133; the current-sense port time-division multiplexing circuit The CS terminal of 136A is the input terminal of the switching power supply controller 13A; the GATE_ON terminal of the current-sense port time-division multiplexing circuit 136A is connected to the output terminal of the logic control circuit 134A and the first input terminal of the drive circuit 135; the OCP terminal of the current-sense port time-division multiplexing circuit 136A is connected to the fourth input terminal of the logic control circuit 134A; the EXTOTP terminal of the current-sense port time-division multiplexing circuit 136A is connected to the fifth input terminal of the logic control circuit 134A; and the CSSCP terminal of the current-sense port time-division multiplexing circuit 136A is connected to the sixth input terminal of the logic control circuit 134A.

[0092] The output end of the upper and lower power enabling circuit 131 is also connected to the first input end of the internal power supply circuit 132; the input ends of the upper and lower enabling circuit 131 are respectively connected to the VDD end of the switching power supply controller 13A, the second input end of the internal power supply circuit 132, and the third input end of the driving circuit 135; the first input end of the pulse width modulator 135 is connected to the FB end of the switching power supply controller 13A; the output end of the pulse width modulator 135 is connected to the first input end of the logic control circuit 134A; the output end of the logic control circuit 134A is also connected to the first end of the driving circuit 135; the output end of the driving circuit 135 is connected to the GATE end of the switching power supply controller 13A.

[0093] like Figure 2 The present invention further provides a switching power supply, including: a transformer TR, a power switch tube M1, a feedback device (FeedBack) 12, an NTC resistor R7, a rectifier diode D5, a first current detection resistor R4 and a second current detection resistor R8; and also includes the above-mentioned switching power supply controller 13A.

[0094] The FB terminal of the switching power supply controller 13A is connected to the output terminal of the feedback device 12. The CS terminal of the switching power supply controller 13A is connected to one end of the second current-sense resistor R8 and one end of the rectifier diode D5. The GATE terminal of the switching power supply controller 13A is connected to the gate of the power switch M1. The drain of the power switch M1 is connected to the same-name terminal of the primary winding LP of the transformer, and the source is connected to one end of R4 and the other end of R8. The other end of the rectifier diode D5 is connected to the other end of the NTC resistor R7. One end of the NTC resistor is connected to the same-name terminal of the auxiliary winding LA of the transformer.

[0095] The working principle of the switching power supply using the current detection port time division multiplexing circuit provided by the present invention is as follows:

[0096] When VDD starts to power up from 0, <VDD ON When (VDD ON is the power-on threshold), EN is logic "0"; when VDD>VDD ON When EN is logic "1", the circuit enters normal operating mode. After VDD is powered on, an internal power supply PVDD is established by the LDO. PVDD is divided by series resistors R21, R22, R23, and R24 to generate reference voltages vref1, vref2, and vref3, respectively. R21, R22, R23, and R24 are precision resistors with matching proportional coefficients β1, β2, and β3 (0 < β1 < β2 < β3 < 1).

[0097] R24=β1 (R21+R22+R23+R24) (1)

[0098] R23+R24=β2 (R21+R22+R23+R24) (2)

[0099] R22+R23+R24=β3 (R21+R22+R23+R24) (3)

[0100] vref1=β3 ×PVDD (4)

[0101] vref2=β2 ×PVDD (5)

[0102] vref3 = β1 × PVDD (6).

[0103] After normal power-on, the EN signal is logic "1", and DELAY3 outputs signal TD3. Figure 4 As shown in the figure. During the T3 period, TD3 is logic "0", and after T3, TD3 is logic "1". Figure 4 As shown, during the T3 period, if CS is not short-circuited, when GATE is logic "1", the CS voltage will rise linearly.CS >vref3, the CSSCPEN signal changes from logic "1" to logic "0", the CSSCP signal remains at logic "0", and the short-circuit protection detection ends. Within T3, if a short circuit occurs in CS, CS remains at 0V and the CSSCPEN signal remains at logic "1". After T3, the CSSCP signal changes from logic "0" to logic "1", and the GATE signal is controlled by the LOGIC module to remain at logic "0", shutting down the switching power supply.

[0104] After GATE outputs normally, DELAY2 outputs signal TD2, such as Figure 5 As shown. When GATE changes from logic "0" to logic "1", TD2 delay time T2 also changes from logic "0" to logic "1"; after a fixed time, it changes from logic "1" to logic "0" again. When GATE is logic "1", the CS terminal voltage is calculated as follows:

[0105] V CS =I CS ×R4 (7)

[0106] Among them I CS As the conduction time of M1 increases linearly, when CS>vref2, the OCP signal is high, and the GATE is controlled by LOGIC to change from logic "1" to logic "0", completing one cycle of overcurrent detection.

[0107] DELAY1 outputs signal TD1, such as Figure 5 As shown. When GATE changes from logic "1" to logic "0", TD1 generates a pulse signal after T1 time. When GATE is logic "0", assuming D5 is an ideal rectifier and R8>>R4, the CS terminal voltage is calculated as follows:

[0108] V CS =V LA ×R8 / (R8+R7) (8)

[0109] As the temperature rises, R7 decreases and the CS voltage increases. CS >vref1, at the rising edge of TD1, the EXTOTP signal changes from logic "0" to logic "1". After several cycles of debounce time T debounce , through LOGIC control, the GATE signal is always logic "0", and the switching power supply is turned off.

[0110] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0111] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A current detection port time division multiplexing circuit, characterized in that: The current-sense port time-division multiplexing circuit has seven ports, namely, a PVDD terminal, an EXTOTP terminal, an OCP terminal, a CSSCP terminal, an EN terminal, a GATE_ON terminal, and a CS terminal; the current-sense port time-division multiplexing circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first comparator, a second comparator, a third comparator, an inverter, a first delay device, a second delay device, a third delay device, a first AND gate, a second AND gate, a third AND gate, a first D flip-flop, and a second D flip-flop; One end of the first resistor, the power supply end of the first comparator, the power supply end of the second comparator, the power supply end of the third comparator, and the D input end of the second D flip-flop are all connected to the PVDD end; the first output end of the first D flip-flop is connected to the EXTOTP end; the output end of the first AND gate is connected to the OCP end; the output end of the third AND gate is connected to the CSSCP end; the enable end of the first comparator, the enable end of the second comparator, the enable end of the third comparator, the reset end of the first D flip-flop, the reset end of the second D flip-flop, and the input end of the third delay are all connected to the EN end; the input end of the inverter, the input end of the second delay, and the second input end of the second AND gate are all connected to the GATE_ON end; the positive input end of the first comparator, the positive input end of the second comparator, and the positive input end of the third comparator are all connected to the CS end; The other end of the first resistor is respectively connected to one end of the second resistor and the inverting input end of the first comparator; the other end of the second resistor is respectively connected to one end of the third resistor and the inverting input end of the second comparator; the other end of the third resistor is respectively connected to one end of the fourth resistor and the inverting input end of the third comparator; the other end of the fourth resistor is grounded; the output end of the first comparator is connected to the D input end of the first D flip-flop, and the clock end of the first D flip-flop is connected to the output end of the first delay device; the output end of the second comparator is connected to the first input end of the first AND gate; the second input end of the first AND gate is connected to the output end of the second delay device; the output end of the third comparator is connected to the first input end of the second AND gate; the output end of the second AND gate is connected to the clock end of the second D flip-flop; the second output end of the second D flip-flop is connected to the first input end of the third AND gate; the second input end of the third AND gate is connected to the output end of the third delay device; The CS terminal and the GATE_ON terminal generate an over-temperature protection control enable signal at the EXTOTP terminal; the CS terminal and the GATE_ON terminal generate an over-current protection control enable signal at the OCP terminal; the CS terminal and the GATE_ON terminal generate a short-circuit protection enable signal at the CSSCP terminal.

2. The current detection port time division multiplexing circuit according to claim 1, characterized in that: The EN terminal is used to set the internal circuit to an initial logic high.

3. A switching power supply controller, characterized in that: include: The current detection port time division multiplexing circuit, power-on and power-off enabling circuit, internal power supply circuit, pulse width modulator, logic control circuit and drive circuit according to any one of claims 1-2; The PVDD terminal of the current-sense port time-division multiplexing circuit is respectively connected to the output terminal of the internal power supply circuit, the fourth input terminal of the pulse width modulator, and the second input terminal of the logic control circuit; the EN terminal of the current-sense port time-division multiplexing circuit is connected to the output terminal of the upper and lower power enabling circuit, the third input terminal of the pulse width modulator, the third input terminal of the logic control circuit, and the second input terminal of the driving circuit; the CS terminal of the current-sense port time-division multiplexing circuit is connected to the second input terminal of the pulse width modulator; the CS terminal of the current-sense port time-division multiplexing circuit is the input terminal of the switching power supply controller; the GATE_ON terminal of the current-sense port time-division multiplexing circuit is connected to the output terminal of the logic control circuit and the first input terminal of the driving circuit; the OCP terminal of the current-sense port time-division multiplexing circuit is connected to the fourth input terminal of the logic control circuit; the EXTOTP terminal of the current-sense port time-division multiplexing circuit is connected to the fifth input terminal of the logic control circuit; and the CSSCP terminal of the current-sense port time-division multiplexing circuit is connected to the sixth input terminal of the logic control circuit. The output end of the upper and lower power enabling circuit is also connected to the first input end of the internal power supply circuit; the input ends of the upper and lower power enabling circuit are respectively connected to the VDD end of the switching power supply controller, the second input end of the internal power supply circuit and the third input end of the drive circuit; the first input end of the pulse width modulator is connected to the FB end of the switching power supply controller; the output end of the pulse width modulator is connected to the first input end of the logic control circuit; the output end of the logic control circuit is also connected to the first end of the drive circuit; and the output end of the drive circuit is connected to the GATE end of the switching power supply controller.

4. A switching power supply comprising: A transformer, a power switch tube, a feedback device, an NTC resistor, a rectifier diode, a first current-sense resistor, and a second current-sense resistor; characterized in that it also includes the switching power supply controller according to claim 3; The FB terminal of the switching power supply controller is connected to the output terminal of the feedback device, and the CS terminal of the switching power supply controller is respectively connected to one end of the second current sensing resistor and the other end of the rectifier diode; the GATE terminal of the switching power supply controller is connected to the gate of the power switch tube.

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