Motor driver chip and its current detection circuit

Abstract

The present invention discloses a motor driver chip and its current detection circuit. The current detection circuit comprises an H-bridge circuit, a leakage current source, an operational amplifier, a dummy mirror transistor, a switch group, a current readout circuit, a mirror transistor, a digital-to-analog converter, and a comparator. The current readout circuit is connected to a first input of the comparator, and the output of the digital-to-analog converter is connected to a second input of the comparator. The motor driver chip and its current detection circuit proposed by the present invention can improve detection accuracy and speed while enhancing tolerance to external power supply noise and interference.

Description

Technical Field

[0001] The present invention belongs to the technical field of current detection, and relates to a current detection circuit, and in particular to a motor drive chip and a current detection circuit thereof. Background Art

[0002] Motor driver ICs must accurately and quickly measure the current flowing through the coils to achieve stable, precise, and efficient motor control. Compared to the external resistor measurement method, the mirror current measurement method is more accurate, less susceptible to process and environmental influences, and has a high level of integration, saving the cost of discrete components.

[0003] U.S. Patent No. 11171587B2, granted in November 2021, proposes a solution for measuring the current of two half-bridge low-side power transistors using a mirror current method. This solution connects the gate and source of the current measuring tube to the power transistor to be detected. By comparing the output current of the digital-to-analog converter with the current in the measuring tube, the power tube current is digitally quantified.

[0004] The problems with this solution are: (1) the drain voltages of the measurement tube and the power tube are not equal, and there is an error in the current mirror; (2) the voltage-to-current conversion module and the digital-to-analog conversion module are easily affected by disturbances from the power supply, which in turn affects the quantization accuracy.

[0005] In view of this, there is an urgent need to design a new current detection circuit to overcome at least some of the above-mentioned defects of the existing current detection circuit. Summary of the Invention

[0006] The present invention provides a motor drive chip and a current detection circuit thereof, which can improve detection accuracy and detection speed while enhancing tolerance to external power supply noise and interference.

[0007] In order to solve the above technical problems, according to one aspect of the present invention, the following technical solution is adopted:

[0008] A current detection circuit for a motor driver chip, the current detection circuit comprising: an H-bridge circuit, a leakage current source, an operational amplifier, a dummy mirror tube, a switch group, a current readout circuit, a mirror tube, a digital-to-analog converter, a comparator, and a current mirror;

[0009] The H-bridge circuit is a switch circuit for controlling the motor, and is connected to the dummy mirror tube via a switch group, and the H-bridge circuit is connected to the mirror tube;

[0010] The leakage current source is connected to the operational amplifier, the dummy mirror tube, the current readout circuit and the mirror tube respectively, so as to provide a bias current to the dummy mirror tube when the current detection circuit is idle;

[0011] The input ends of the operational amplifier are respectively connected to the dummy mirror tube and the mirror tube, and the output end of the operational amplifier is connected to the current readout circuit; the operational amplifier is used to clamp the drain voltage of the current mirror to realize the reading of the current in the H-bridge circuit;

[0012] The dummy mirror tube is connected to the current readout circuit and the mirror tube respectively, so as to maintain the circuit operating point when the current detection circuit is idle, thereby improving the switching speed;

[0013] The switch group is used to connect or disconnect the current detection circuit and the H-bridge circuit;

[0014] The current reading circuit is connected to a first input terminal of the comparator, and the output terminal of the digital-to-analog converter is connected to a second input terminal of the comparator; the current reading circuit is used to convert the current in the mirror tube into a voltage;

[0015] The mirror tube is used to scale the current in the H-bridge circuit in equal proportion;

[0016] The digital-to-analog converter is used to provide a comparison threshold;

[0017] The comparator is used to determine the magnitude relationship between the output voltage of the current readout circuit and a comparison threshold.

[0018] As an embodiment of the present invention, the H-bridge circuit includes a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a first inductor;

[0019] The voltage VM is connected to the drain of the tenth MOS transistor M10 and the drain of the eleventh MOS transistor M11 respectively. The source of the tenth MOS transistor M10 is connected to the first end of the first inductor and the drain of the twelfth MOS transistor M12 respectively.

[0020] The source of the eleventh MOS transistor M11 is connected to the second end of the first inductor and the drain of the thirteenth MOS transistor M13 respectively.

[0021] As an embodiment of the present invention, the H-bridge circuit includes a plurality of twelfth MOS transistors M12 connected in series and a plurality of thirteenth MOS transistors M13 connected in series.

[0022] As an embodiment of the present invention, the leakage current source includes a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a seventh MOS transistor M7;

[0023] The voltage VDD is connected to the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5 respectively;

[0024] The drain of the fourth MOS transistor M4 is connected to the source of the sixth MOS transistor M6, and the drain of the fifth MOS transistor M5 is connected to the source of the seventh MOS transistor M7; the gate of the fourth MOS transistor M4 is connected to the gate of the fifth MOS transistor M5, and the gate of the sixth MOS transistor M6 is connected to the gate of the seventh MOS transistor M7;

[0025] The drain of the sixth MOS transistor M6 is connected to the non-inverting input terminal of the operational amplifier, and the drain of the seventh MOS transistor M7 is connected to the inverting input terminal of the operational amplifier.

[0026] As an embodiment of the present invention, the dummy mirror transistor includes an eighth MOS transistor M8 and a ninth MOS transistor M9; the switch group includes a first switch and a second switch;

[0027] The drain of the eighth MOS transistor M8 is connected to the non-inverting input terminal of the operational amplifier and the first terminal of the first switch respectively; the drain of the ninth MOS transistor M9 is connected to the inverting input terminal of the operational amplifier and the first terminal of the second switch respectively;

[0028] The gate of the eighth MOS transistor M8 is connected to the gate of the ninth MOS transistor M9, and the source of the eighth MOS transistor M8 and the source of the ninth MOS transistor M9 are grounded respectively;

[0029] The second end of the first switch is connected to the first end of the first inductor, and the second end of the second switch is connected to the second end of the first inductor.

[0030] As an embodiment of the present invention, the current reading circuit includes a first resistor and a first MOS transistor M1;

[0031] The first end of the first resistor is connected to the voltage VDD; the second end of the first resistor is connected to the first input end of the comparator and the source of the first MOS transistor M1 respectively;

[0032] The drain of the first MOS transistor M1 is connected to the non-inverting input terminal of the operational amplifier; the output terminal of the comparator is connected to the gate of the first MOS transistor M1.

[0033] As an embodiment of the present invention, the mirror transistor includes a second MOS transistor M2 and a third MOS transistor M3;

[0034] The drain of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3 and the drain of the first MOS transistor M1 respectively;

[0035] As an embodiment of the present invention, the H-bridge circuit includes a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a first inductor; a voltage VM is connected to the drain of the tenth MOS transistor M10 and the drain of the eleventh MOS transistor M11, respectively; the source of the tenth MOS transistor M10 is connected to the first end of the first inductor and the drain of the twelfth MOS transistor M12, respectively; the source of the eleventh MOS transistor M11 is connected to the second end of the first inductor and the drain of the thirteenth MOS transistor M13, respectively;

[0036] The source of the second MOS transistor M2 is connected to the source of the twelfth MOS transistor, and the source of the third MOS transistor is connected to the source of the thirteenth MOS transistor.

[0037] According to another aspect of the present invention, the following technical solution is adopted: a motor driving chip, the motor driving chip including the current detection circuit of the motor driving chip mentioned above.

[0038] The beneficial effects of the present invention are that the motor drive chip and the current detection circuit thereof proposed in the present invention can improve detection accuracy and detection speed, while enhancing tolerance to external power supply noise and interference.

[0039] In one usage scenario of the present invention, the present invention improves the accuracy of the mirror current by clamping the drain voltage of the measuring tube and the mirror tube through an operational amplifier; by using a dummy tube to maintain the operating point of the operational amplifier when neither the two power tubes nor the measuring tubes are connected, the speed of switching between different states is improved; by using an internal power supply voltage with a certain noise suppression effect as a reference point, the mirror current is converted into a voltage, and digital quantization is completed by comparing it with the output voltage of a resistive digital-to-analog converter that also uses the internal power supply voltage as a reference, thereby enhancing tolerance to external power supply noise and interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 The figure is a circuit diagram of a current detection circuit in an existing current detection scheme.

[0041] Figure 2 FIG. 4 is a circuit diagram of a current detection circuit according to an embodiment of the present invention.

[0042] Figure 3 FIG. 1 is a waveform diagram of a control signal in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0045] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments described. The same or similar existing technical means and some technical features of the embodiments are mutually replaced within the scope of the description and protection of the present invention.

[0046] The description of the steps in each embodiment in the specification is only for the convenience of explanation, and the implementation method of this application is not limited by the order of implementation of the steps.

[0047] The term "connection" as used in this specification includes both direct connection and indirect connection, such as connection through active devices, passive devices or electrically conductive media; it may also include connection through other active devices or passive devices that are well known to those skilled in the art and can achieve the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits.

[0048] The present invention discloses a current detection circuit for a motor drive chip. Figure 2 is a circuit diagram of a current detection circuit according to an embodiment of the present invention; Figure 2 The current detection circuit includes: an H-bridge circuit 201, a leakage current source 202, an operational amplifier 203, a dummy mirror tube 204, a switch group 205, a current readout circuit 206, a mirror tube 207, a digital-to-analog converter 208, and a comparator 209.

[0049] The H-bridge circuit 201 is a switching circuit for controlling the motor and is connected to a dummy mirror transistor 204 via a switch group 205. The H-bridge circuit 201 is connected to a mirror transistor 207. The leakage current source 202 is connected to an operational amplifier 203, a dummy mirror transistor 204, a current readout circuit 206, and a mirror transistor 207, respectively, to provide a bias current to the dummy mirror transistor 204 when the current detection circuit is idle.

[0050] The input end of the operational amplifier 203 is connected to the dummy mirror tube 204 and the mirror tube 207 respectively, and the output end of the operational amplifier 203 is connected to the current readout circuit 206; the operational amplifier 203 is used to read the current mirror (referring to Figure 2The drain voltages of the second MOS transistor M2, the third MOS transistor M3, the twelfth MOS transistor M12, and the thirteenth MOS transistor M13 in the H-bridge circuit 201 are clamped to enable reading of the current in the H-bridge circuit 201. The dummy mirror transistor 204 is connected to the current readout circuit 206 and the mirror transistor 207, respectively, to maintain the circuit operating point when the current detection circuit is idle, thereby improving switching speed. The switch group 205 is used to connect or disconnect the current detection circuit and the H-bridge circuit 201; the current readout circuit 206 is connected to the first input of the comparator 209, and the output of the digital-to-analog converter 208 is connected to the second input of the comparator 209. The current readout circuit 206 is used to convert the current in the mirror transistor 207 into a voltage.

[0051] The mirror tube 207 is used to scale the current in the H-bridge circuit 201 ; the digital-to-analog converter 208 is used to provide a comparison threshold; and the comparator 209 is used to determine the magnitude relationship between the output voltage of the current readout circuit 206 and the comparison threshold.

[0052] In one embodiment of the present invention, the H-bridge circuit includes a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a first inductor. A voltage VM is connected to the drain of the tenth MOS transistor M10 and the drain of the eleventh MOS transistor M11, respectively. The source of the tenth MOS transistor M10 is connected to the first end of the first inductor and the drain of the twelfth MOS transistor M12, respectively. The source of the eleventh MOS transistor M11 is connected to the second end of the first inductor and the drain of the thirteenth MOS transistor M13, respectively.

[0053] The H-bridge circuit may include a plurality of twelfth MOS transistors M12 connected in series and a plurality of thirteenth MOS transistors M13 connected in series. Of two adjacent twelfth MOS transistors M12, the source of one twelfth MOS transistor M12 is connected to the drain of the other twelfth MOS transistor M12; and of two adjacent thirteenth MOS transistors M13, the source of one thirteenth MOS transistor M13 is connected to the drain of the other thirteenth MOS transistor M13.

[0054] The leakage current source includes a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a seventh MOS transistor M7. A voltage VDD is connected to the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5, respectively. The drain of the fourth MOS transistor M4 is connected to the source of the sixth MOS transistor M6, and the drain of the fifth MOS transistor M5 is connected to the source of the seventh MOS transistor M7. The gate of the fourth MOS transistor M4 is connected to the gate of the fifth MOS transistor M5, and the gate of the sixth MOS transistor M6 is connected to the gate of the seventh MOS transistor M7. The drain of the sixth MOS transistor M6 is connected to the non-inverting input of an operational amplifier, and the drain of the seventh MOS transistor M7 is connected to the inverting input of the operational amplifier.

[0055] The dummy mirror transistor includes an eighth MOS transistor M8 and a ninth MOS transistor M9; the switch group includes a first switch and a second switch. The drain of the eighth MOS transistor M8 is respectively connected to the non-inverting input terminal of the operational amplifier and the first terminal of the first switch; the drain of the ninth MOS transistor M9 is respectively connected to the inverting input terminal of the operational amplifier and the first terminal of the second switch; the gate of the eighth MOS transistor M8 is connected to the gate of the ninth MOS transistor M9, and the sources of the eighth MOS transistor M8 and the ninth MOS transistor M9 are respectively grounded; the second terminal of the first switch is connected to the first terminal of the first inductor, and the second terminal of the second switch is connected to the second terminal of the first inductor.

[0056] The current readout circuit includes a first resistor and a first MOS transistor M1; a first end of the first resistor is connected to a voltage VDD; a second end of the first resistor is connected to a first input end of a comparator and a source of the first MOS transistor M1, respectively; a drain of the first MOS transistor M1 is connected to a non-inverting input end of an operational amplifier; and an output end of the comparator is connected to a gate end of the first MOS transistor M1.

[0057] The mirror transistor includes a second MOS transistor M2 and a third MOS transistor M3; the drain of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3 and the drain of the first MOS transistor M1 respectively; the source of the second MOS transistor M2 is connected to the source of the twelfth MOS transistor, and the source of the third MOS transistor is connected to the source of the thirteenth MOS transistor.

[0058] Figure 3 This is a control signal waveform diagram in one embodiment of the present invention; please refer to Figure 3 In one embodiment of the present invention, Figure 3 The waveform of the control signal is shown.

[0059] In one use scenario of the present invention, the present invention uses two measuring tubes to mirror the currents of two low-side power tubes (selected using PH1 and PH2) in a certain proportion, respectively. The gate and source are connected together, and the drain is clamped by feedback from an operational amplifier. When the currents of both power tubes do not need to be measured (PH1 and PH2 are both low), the power tube and the measuring tube are disconnected from the feedback loop. At this time, a pair of dummy tubes of the same size as the measuring tubes are connected to maintain the operating point of the operational amplifier. In this way, when the mirror current of the measuring tube is connected again, the operational amplifier does not need to settle for a long time. The two additional leakage currents Ib introduced will also be connected during measurement, but because they can be ignored compared to the current to be measured, they will not affect the accuracy of the mirror. The current of the measuring tube is connected to the low-voltage power supply VDD through a resistor. The output voltage and the output voltage of the resistive digital-to-analog converter (DAC) are passed through a comparator to complete the digital quantization of the power tube current.

[0060] In summary, the motor driver chip and current detection circuit thereof proposed in the present invention can improve detection accuracy and detection speed, while enhancing tolerance to external power supply noise and interference.

[0061] In one usage scenario of the present invention, the present invention improves the accuracy of the mirror current by clamping the drain voltage of the measuring tube and the mirror tube through an operational amplifier; by using a dummy tube to maintain the operating point of the operational amplifier when neither the two power tubes nor the measuring tubes are connected, the speed of switching between different states is improved; by using an internal power supply voltage with a certain noise suppression effect as a reference point, the mirror current is converted into a voltage, and digital quantization is completed by comparing it with the output voltage of a resistive digital-to-analog converter that also uses the internal power supply voltage as a reference, thereby enhancing tolerance to external power supply noise and interference.

[0062] It should be noted that the present application can be implemented in software and / or a combination of software and hardware; for example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In some embodiments, the software program of the present application can be executed by a processor to implement the above steps or functions. Similarly, the software program of the present application (including related data structures) can be stored in a computer-readable recording medium; for example, a RAM memory, a magnetic or optical drive, or a floppy disk and the like. In addition, some steps or functions of the present application can be implemented in hardware; for example, as a circuit that cooperates with a processor to perform various steps or functions.

[0063] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The description and application of the present invention here are illustrative and are not intended to limit the scope of the present invention to the above-described embodiments. The effects or advantages involved in the embodiments may not be embodied in the embodiments due to interference from various factors, and the description of the effects or advantages is not used to limit the embodiments. Variations and changes to the embodiments disclosed here are possible, and the replacement of the embodiments and various equivalent components are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the present invention. Other variations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A current detection circuit for a motor driver chip, characterized in that: The current detection circuit includes: an H-bridge circuit, a leakage current source, an operational amplifier, a dummy mirror tube, a switch group, a current readout circuit, a mirror tube, a digital-to-analog converter, a comparator and a current mirror; The H-bridge circuit is a switch circuit for controlling the motor, and is connected to the dummy mirror tube via a switch group, and the H-bridge circuit is connected to the mirror tube; The leakage current source is connected to the operational amplifier, the dummy mirror tube, the current readout circuit and the mirror tube respectively, so as to provide a bias current to the dummy mirror tube when the current detection circuit is idle; The input ends of the operational amplifier are respectively connected to the dummy mirror tube and the mirror tube, and the output end of the operational amplifier is connected to the current readout circuit; the operational amplifier is used to clamp the drain voltage of the current mirror to realize the reading of the current in the H-bridge circuit; The dummy mirror tube is connected to the current readout circuit and the mirror tube respectively, so as to maintain the circuit operating point when the current detection circuit is idle, thereby improving the switching speed; The switch group is used to connect or disconnect the current detection circuit and the H-bridge circuit; The current reading circuit is connected to a first input terminal of the comparator, and the output terminal of the digital-to-analog converter is connected to a second input terminal of the comparator; the current reading circuit is used to convert the current in the mirror tube into a voltage; The mirror tube is used to scale the current in the H-bridge circuit in equal proportion; The digital-to-analog converter is used to provide a comparison threshold; The comparator is used to determine the magnitude relationship between the output voltage of the current readout circuit and a comparison threshold.

2. The current detection circuit of the motor driver chip according to claim 1, wherein: The H-bridge circuit includes a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a first inductor; The voltage VM is connected to the drain of the tenth MOS transistor M10 and the drain of the eleventh MOS transistor M11 respectively. The source of the tenth MOS transistor M10 is connected to the first end of the first inductor and the drain of the twelfth MOS transistor M12 respectively. The source of the eleventh MOS transistor M11 is connected to the second end of the first inductor and the drain of the thirteenth MOS transistor M13 respectively.

3. The current detection circuit of the motor driver chip according to claim 2, characterized in that: The H-bridge circuit includes a plurality of twelfth MOS transistors M12 connected in series and a plurality of thirteenth MOS transistors M13 connected in series.

4. The current detection circuit of the motor driver chip according to claim 1, wherein: The leakage current source includes a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a seventh MOS transistor M7; The voltage VDD is connected to the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5 respectively; The drain of the fourth MOS transistor M4 is connected to the source of the sixth MOS transistor M6, and the drain of the fifth MOS transistor M5 is connected to the source of the seventh MOS transistor M7; the gate of the fourth MOS transistor M4 is connected to the gate of the fifth MOS transistor M5, and the gate of the sixth MOS transistor M6 is connected to the gate of the seventh MOS transistor M7; The drain of the sixth MOS transistor M6 is connected to the non-inverting input terminal of the operational amplifier, and the drain of the seventh MOS transistor M7 is connected to the inverting input terminal of the operational amplifier.

5. The current detection circuit of the motor driver chip according to claim 2, wherein: The dummy mirror transistor includes an eighth MOS transistor M8 and a ninth MOS transistor M9; the switch group includes a first switch and a second switch; The drain of the eighth MOS transistor M8 is connected to the non-inverting input terminal of the operational amplifier and the first terminal of the first switch respectively; the drain of the ninth MOS transistor M9 is connected to the inverting input terminal of the operational amplifier and the first terminal of the second switch respectively; The gate of the eighth MOS transistor M8 is connected to the gate of the ninth MOS transistor M9, and the source of the eighth MOS transistor M8 and the source of the ninth MOS transistor M9 are grounded respectively; The second end of the first switch is connected to the first end of the first inductor, and the second end of the second switch is connected to the second end of the first inductor.

6. The current detection circuit of the motor driver chip according to claim 1, wherein: The current reading circuit includes a first resistor and a first MOS transistor M1; The first end of the first resistor is connected to the voltage VDD; the second end of the first resistor is connected to the first input end of the comparator and the source of the first MOS transistor M1 respectively; The drain of the first MOS transistor M1 is connected to the non-inverting input terminal of the operational amplifier; the output terminal of the comparator is connected to the gate of the first MOS transistor M1.

7. The current detection circuit of the motor driver chip according to claim 6, characterized in that: The mirror transistor includes a second MOS transistor M2 and a third MOS transistor M3; The drain of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3 and the drain of the first MOS transistor M1 respectively.

8. The current detection circuit of the motor driver chip according to claim 7, characterized in that: The H-bridge circuit includes a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a first inductor; a voltage VM is connected to the drain of the tenth MOS transistor M10 and the drain of the eleventh MOS transistor M11, respectively; the source of the tenth MOS transistor M10 is connected to the first end of the first inductor and the drain of the twelfth MOS transistor M12, respectively; the source of the eleventh MOS transistor M11 is connected to the second end of the first inductor and the drain of the thirteenth MOS transistor M13, respectively; The source of the second MOS transistor M2 is connected to the source of the twelfth MOS transistor, and the source of the third MOS transistor is connected to the source of the thirteenth MOS transistor.

9. A motor driver chip, characterized in that: The motor driver chip includes the current detection circuit of the motor driver chip according to any one of claims 1 to 8.

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