A low dropout linear regulator

Abstract

The present invention provides a low voltage difference linear regulator, which can improve the power supply rejection ratio and loop stability. The invention comprises an input end of an error amplification module, which inputs a reference voltage signal; an output end of the error amplification module is connected to the gate of a first low voltage NMOS tube; a source of the first low voltage NMOS tube outputs a correction voltage, and the first low voltage NMOS tube is used to adjust the input voltage of the low voltage difference linear regulator; an input end of a clock generation module is connected to the source of the first low voltage NMOS tube to generate a first clock signal CK; a level conversion module is used to convert the first clock signal CK into a second clock signal CK1; a charge pump module is used to output a boosted voltage; an output feedback module is used to adjust the output voltage of the low voltage difference linear regulator; the output end of the charge pump module is connected to the gate of a second low voltage NMOS tube; the source of the second low voltage NMOS tube is connected to one end of a feedback resistor, and the other end is connected to a negative phase input end of the error amplification module.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic chip design, and in particular to a low voltage difference linear regulator. Background Art

[0002] Low-Dropout Voltage Regulator (LDO) is a DC linear regulator with an input voltage greater than the output voltage. It has the advantages of fast input and output response, low noise, and low cost. Therefore, it is widely used in portable electronic products and is one of the essential modules in electronic system power management. The basic structure of LDO includes four parts: error amplifier module, power tube, feedback network, and bandgap reference. The fully integrated LDO without inductor is conducive to reducing chip area and cost and has higher reliability. In the prior art, the power tube of the output stage of the fully integrated LDO can use PMOS devices or NMOS devices. However, the LDO based on the PMOS output stage has the problem that the power supply rejection ratio is not good enough and the phase compensation cannot achieve a relatively stable loop. For the LDO based on the conventional NMOS output stage, because the threshold voltage of the NMOS tube is a positive value, the output voltage range is limited, the threshold voltage of the NMOS device used cannot be too high, and the size of the NMOS device becomes larger due to low overload. In addition, for the LDO based on the depletion-type NMOS output stage, its output range is also limited, the threshold voltage of the depletion-type NMOS device cannot be too low, and the L value of the depletion-type NMOS is usually larger than that of the general NMOS. The increase in the size of the NMOS will increase the chip area and cost.

[0003] Therefore, there is an urgent need to provide a new type of low voltage dropout linear regulator to improve the above problems. Summary of the invention

[0004] The present invention provides a low voltage dropout linear regulator, which reduces the limitation on the output voltage range by using a low voltage NMOS tube with a lower threshold voltage, and can improve the power supply rejection ratio and loop stability compared with the original LDO with a PMOS output stage.

[0005] In a first aspect, the present invention proposes a low voltage difference linear regulator, comprising: an error amplification module, a clock generation module, a level conversion module, a charge pump module, a first low voltage NMOS tube and an output feedback module; wherein: the error amplification module comprises a positive phase input terminal, a negative phase input terminal and an output terminal, the positive phase input terminal inputs a reference voltage signal Vref; the output terminal is connected to the gate of the first low voltage NMOS tube; the source of the first low voltage NMOS tube outputs a correction voltage V VCO, the first low-voltage NMOS tube is used to adjust the input voltage of the low-voltage difference linear regulator; the input end of the clock generation module is connected to the source of the first low-voltage NMOS tube, and is used to generate a first clock signal CK; the level conversion module is used to convert the first clock signal CK into a second clock signal CK1, and the first clock signal CK and the second clock signal CK1 are connected to the charge pump module; the charge pump module is used to output a boosted voltage Vgate1; the output feedback module includes a second low-voltage NMOS tube and a feedback resistor, and is used to adjust the output voltage of the low-voltage difference linear regulator; wherein the output end of the charge pump module is connected to the gate of the second low-voltage NMOS tube; the source of the second low-voltage NMOS tube is connected to one end of the feedback resistor, and the connection point is the output end of the low-voltage difference linear regulator; the active end of the feedback resistor connected to the second low-voltage NMOS tube is connected to the negative phase input end of the error amplification module.

[0006] The beneficial effects of the low-voltage difference linear regulator provided by the present invention are: on the one hand, a charge pump module is applied to the structure of the low-voltage difference linear regulator. By inputting clock signals of different amplitudes, the charge pump module can output voltages of different sizes, which can meet the needs of different application scenarios; on the other hand, the use of a low-voltage NMOS tube with a lower threshold voltage can reduce the restriction on the output voltage range, and the device size is smaller. Compared with the LDO of the PMOS output stage, the power supply rejection ratio and loop stability can be improved.

[0007] In a possible embodiment, the charge pump module includes: a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a first capacitor C1 and a second capacitor C2;

[0008] The drain of the first NMOS tube M1 and the drain of the second NMOS tube M2 are connected, the second end of the first capacitor C1 is connected to the first clock signal CK, and the second end of the second capacitor C2 is connected to the third clock signal CK_i; the gate of the first NMOS tube M1, the source of the second NMOS tube M2 and the source of the fourth NMOS tube M4 are all connected to the first end of the second capacitor C2, the source of the first NMOS tube M1, the gate of the second NMOS tube M2 and the source of the third NMOS tube M3 are all connected to the first end of the first capacitor C1, and the gate of the third NMOS tube M3 is connected to the fourth clock signal CK1_i.

[0009] The gate of the fourth NMOS tube M4 is connected to the second clock signal CK1, wherein the third clock signal CK_i5 is the inverted clock signal of the first clock signal CK, and the fourth clock signal CK1_i is the inverted clock signal of the second clock signal CK1. The on-resistance of the low-voltage NMOS tube in the charge pump module is much smaller than that of the high-voltage tube under the same area, so the area of ​​the MOS tube can be saved; at the same time, when the area of ​​the MOS tube is reduced, the parasitic capacitance of the charge pump module is also reduced, which can improve the efficiency of the charge pump and reduce the area of ​​the auxiliary drive circuit.

[0010] In another possible embodiment, the error amplification module is a single-stage amplification structure or a multi-stage amplification structure.

[0011] In other possible embodiments, the low voltage drop linear regulator further includes a first filter capacitor C4; one end of the first filter capacitor C4 is coupled to the gate of the second low voltage NMOS tube, and the first filter capacitor C4 is connected to the gate of the second low voltage NMOS tube.

[0012] The other end of the capacitor C4 is grounded. The first filter capacitor C4 is used to filter out the ripples of the output voltage 5Vout of the low voltage difference linear regulator, so as to make the output signal Vout efficient and smooth.

[0013] In another possible embodiment, the low voltage drop linear regulator further includes a second filter capacitor C3; one end of the second filter capacitor C3 is coupled to the gate of the second low voltage NMOS tube, and the other end of the second filter capacitor C3 is coupled to the source of the first low voltage NMOS tube. The second filter capacitor C3 is used to filter out the ripple of the output voltage Vout of the low voltage drop linear regulator, so that the output signal Vout is efficiently smoothed.

[0014] In a second aspect, the present invention further provides a low voltage drop linear regulator, comprising: an error amplification module, a clock generation module, a phase generation module, a charge pump module and an output feedback module; wherein:

[0015] The error amplification module comprises a positive phase input terminal, a negative phase input terminal and an output terminal, the positive phase input terminal is input with a reference voltage signal Vref; the output terminal is connected with the first input terminal of the phase generation module.

[0016] The output end of the clock generation module is connected to the second input end of the phase generation module, and the clock generation module is used to generate a first clock signal CK; the phase generation module is used to convert the first clock signal CK into a second clock signal CK1, and the first clock signal CK and the second clock signal CK1 are connected to the charge pump module. The charge pump module is used to output the adjustment voltage Vgate2 according to the output polarity of the output end of the error amplification module, and the output feedback module includes a second low-voltage NMOS tube and a feedback resistor, which are used to adjust the output voltage of the low-voltage difference linear regulator; wherein the output end of the charge pump module is connected to the gate of the second low-voltage NMOS tube; the source of the second low-voltage NMOS tube is connected to one end of the feedback resistor, and the connection point is the output end of the low-voltage difference linear regulator; the active end of the feedback resistor connected to the second low-voltage NMOS tube is connected to the negative phase input end of the error amplification module.

[0017] The beneficial effects of the low-dropout linear regulator provided by the present invention are: on the one hand, a charge pump module is applied to the output stage of the structure of the low-dropout linear regulator, and by inputting clock signals of different amplitudes, the charge pump module can output voltages of different magnitudes, which can meet the needs of different application scenarios; on the other hand, the use of the first low-voltage NMOS device and the second low-voltage NMOS device with lower threshold voltage can reduce the restriction on the output voltage range, and the device size is smaller. Compared with the LDO of the PMOS output stage, the power supply rejection ratio and loop stability can be improved.

[0018] In a possible embodiment, the output of the error amplification module is a low level; the charge pump module includes: a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a first capacitor C1 and a second capacitor C2;

[0019] Among them, the drain of the first NMOS tube M1 and the drain of the second NMOS tube M2 are connected, the second end of the first capacitor C1 is connected to the first clock signal CK, and the second end of the second capacitor C2 is connected to the third clock signal CK_i; the gate of the first NMOS tube M1, the source of the second NMOS tube M2 and the source of the fourth NMOS tube M4 are all connected to the first end of the second capacitor C2, the source of the first NMOS tube M1, the gate of the second NMOS tube M2 and the source of the third NMOS tube M3 are all connected to the first end of the first capacitor C1, the gate of the third NMOS tube M3 is connected to the fourth clock signal CK1_i, and the gate of the fourth NMOS tube M4 is connected to the second clock signal CK1, wherein the third clock signal CK_i is an inverted clock signal of the first clock signal CK, and the fourth clock signal CK1_i is an inverted clock signal of the second clock signal CK1.

[0020] In another possible embodiment, the output of the error amplification module is a high level; the charge pump module includes: a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a first capacitor C1 and a second capacitor C2;

[0021] Among them, the drain of the first NMOS tube M1 and the drain of the second NMOS tube M2 are connected, and the second end of the first capacitor C1 and the second end of the second capacitor C2 are both connected to the first clock signal CK; the gate of the first NMOS tube M1, the source of the second NMOS tube M2 and the source of the fourth NMOS tube M4 are all connected to the first end of the second capacitor C2, the gate of the second NMOS tube M2, the source of the first NMOS tube M1 and the source of the third NMOS tube M3 are all connected to the first end of the first capacitor C1, and the gate of the third NMOS tube M3 and the gate of the fourth NMOS tube M4 are both connected to the first clock signal CK.

[0022] In other possible embodiments, the error amplification module is a single-stage amplification structure or a multi-stage amplification structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 It is a schematic diagram of the circuit structure of a traditional low voltage drop linear regulator;

[0025] Figure 2 is a circuit structure diagram of a low voltage drop linear regulator according to an embodiment of the present invention;

[0026] Figure 3 4 is a circuit structure diagram of another low voltage drop linear regulator according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] like Figure 1 As shown in FIG. 1 , the conventional LDO structure includes: a reference voltage source 01, an error amplifier module 201, an output NMOS tube 03, a resistor feedback network 04, and an output load 05. The reference voltage source 01 generates a reference voltage Vref that does not change with temperature and power supply voltage. The output voltage Vout is fed back as a voltage V through the resistor voltage divider network 04. fb, the reference voltage Vref and the feedback voltage Vfb enter the error amplifier module 201, thereby amplifying their difference and driving the output NMOS tube 03. When the circuit is balanced, the reference voltage Vref is approximately equal to the feedback voltage V fb At this time, the current obtained by the output load 05 is pulled out from the output NMOS tube 03. Figure 1 As shown, assuming that the output resistance of the output NMOS tube 03 is Ro-pass, the output resistance of the error amplifier module is R oa , the gate parasitic capacitance of the output NMOS tube 03 is Cpar, then Figure 1 There are three poles and one zero in the LDO structure shown. In order to ensure the stability of the loop, a large output capacitor must be used as a load, which increases the cost and wastes area.

[0028] The present invention proposes two low-voltage dropout linear regulators including low-voltage NMOS tubes. Both of the two different low-voltage dropout linear regulators include a charge pump module. The function of the charge pump module in the first low-voltage dropout linear regulator is to pull up the output voltage. The second low-voltage dropout linear regulator includes a phase generator (CKphasegenerator) module. Through the high and low levels output by the error amplifier module, the phase generator module generates a clock signal or two opposite clock signals to the charge pump module. The above-mentioned low-voltage dropout linear regulator can reduce the restriction on the output voltage range, the device size is smaller, and compared with the LDO of the PMOS output stage, it can improve the power supply rejection ratio and loop stability.

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] Figure 2 It is a circuit structure diagram of the low voltage difference linear regulator of the present invention, comprising: an error amplification module 201, a clock generation module 202, a level conversion module 203, a charge pump module 204, a first low voltage NMOS tube 205 and an output feedback module 206.

[0031] Wherein: the error amplification module 201 includes a positive phase input terminal, a negative phase input terminal and an output terminal, the positive phase input terminal is connected to the reference voltage source 10, and the reference voltage source 10 generates a reference voltage signal Vref; the output terminal of the error amplification module 201 is connected to the gate of the first low voltage NMOS tube 205; the source of the first NMOS tube 205 outputs the correction voltage V VCOThe first low-voltage NMOS tube 205 is used to adjust the input voltage of the low-voltage difference linear regulator; the input end of the clock generation module 202 is connected to the source of the first low-voltage NMOS tube 205, and is used to generate a first clock signal CK; the level conversion module 203 is used to convert the first clock signal CK into a second clock signal CK1, and the first clock signal CK and the second clock signal CK1 are connected to the charge pump module 204; the charge pump module 204 is used to output a boosted voltage Vgate1; the output feedback module 206 includes a second low-voltage NMOS tube 20 61 and a feedback resistor 2062 are used to adjust the output voltage of the low-voltage difference linear regulator; wherein the output end of the charge pump module 204 is connected to the gate of the second low-voltage NMOS tube 2061, and is used to generate and control the gate voltage of the second low-voltage NMOS tube 2061; the source of the second low-voltage NMOS tube 2061 is connected to one end of the feedback resistor 2062, and the connection point is the output end of the low-voltage difference linear regulator; the other end of the feedback resistor 2062 connected to the second low-voltage NMOS tube 2061 is connected to the negative phase input end of the error amplification module 201.

[0032] Among them, the threshold voltages of the first low-voltage NMOS tube 205 and the second low-voltage NMOS tube 2061 are approximately zero. A low-voltage NMOS tube is set at both the input stage and the output stage of the LDO, which can reduce the limitation on the output voltage range. The clock generation module 202 generates a first clock signal CK, which is passed through a level shifting module (Levelshifer) 203 to generate a second clock signal CK1. The two clock signals are connected to the charge pump module 204, and the boosted voltage Vgate1 is output, and a stable voltage Vout is output through the second low-voltage NMOS tube 2061 and the feedback resistor 2062.

[0033] It is worth noting that the charge pump module 204 in this embodiment may be a basic charge pump stage structure, and in practice, a plurality of cascaded charge pump structures may also be used according to the required output voltage value.

[0034] It should be understood that the error amplification module 201 may be a single-stage amplification structure, ie, an error amplifier, or a multi-stage amplification structure, such as composed of a plurality of cascaded error amplifiers.

[0035] Figure 2 A basic charge pump stage structure diagram is also shown. The charge pump module 204 includes: a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a first capacitor C1 and a second capacitor C2. The first capacitor C1 and the second capacitor C2 are charging capacitors in the circuit structure of the charge pump module.

[0036] The drain of the first NMOS tube M1 and the drain of the second NMOS tube M2 are connected, the second end of the first capacitor C1 is connected to the first clock signal CK, and the second end of the second capacitor C2 is connected to the third clock signal CK_i; the gate of the first NMOS tube M1, the source of the second NMOS tube M2 and the source of the fourth NMOS tube M4 are all connected to the first end of the second capacitor C2, the source of the first NMOS tube M1, the gate of the second NMOS tube M2 and the source of the third NMOS tube M3 are all connected to the first end of the first capacitor C1, and the gate of the third NMOS tube M3 is connected to the fourth clock signal CK1_i.

[0037] The gate of the fourth NMOS transistor M4 is connected to the second clock signal CK1 , wherein the third clock signal CK_i5 is an inverted clock signal of the first clock signal CK, and the fourth clock signal CK1_i is an inverted clock signal of the second clock signal CK1 .

[0038] In one possible implementation, referring to Figure 2 The above-mentioned low voltage drop linear regulator further includes a first filter capacitor C4; one end of the first filter capacitor C4 is coupled to the gate of the second low voltage NMOS tube 2061.

[0039] The first filter capacitor C4 is connected to the gate of the second low-voltage NMOS transistor 2061, and the other end of the first filter capacitor C4 is grounded. Optionally, a second filter capacitor C3 may also be included; one end of the second filter capacitor C3 is coupled to the gate of the second low-voltage NMOS transistor 2061, and the other end of the second filter capacitor C3 is connected to the source of the second low-voltage NMOS transistor 2061. The second filter capacitor C3 is used to filter out the ripple of the output voltage Vout of the low-voltage difference linear regulator, so that the output signal Vout is efficiently smoothed.

[0040] The present invention also proposes another circuit structure of a low voltage dropout linear regulator, such as Figure 3 As shown, the structure includes: an error amplification module 201, a clock generation module 202, a phase generation module 303, a charge pump module 204 and an output feedback module 206; wherein:

[0041] The error amplification module 201 includes a positive phase input terminal, a negative phase input terminal and an output terminal, the positive phase input terminal inputs a reference voltage signal Vref; the negative phase output terminal of the error amplification module 201 is connected to the first input terminal of the 0 phase generation module. The output terminal of the clock generation module 202 is connected to the second input terminal of the phase generation module 303, and the clock generation module 202 is used to generate a first clock signal CK;

[0042] The phase generation module 303 is used to convert the first clock signal CK into a second clock signal CK1. The first clock signal CK and the second clock signal CK1 are connected to the charge pump module 204.

[0043] The module 204 is used to output the adjustment voltage 5Vgate2 according to the output polarity of the output end of the error amplification module. The output feedback module 206 includes a second low-voltage NMOS tube 2061 and a feedback resistor 2062.

[0044] Used to adjust the output voltage of the low-dropout linear regulator.

[0045] Among them, the output end of the charge pump module 204 is connected to the gate of the second low-voltage NMOS tube 2061, which is used to generate and control the gate voltage of the second low-voltage NMOS tube 2061; the source of the second low-voltage NMOS tube 2061 is connected to one end of the feedback resistor 2062, and the connection point is the output end of the low-voltage difference linear regulator; the other end of the feedback resistor 2062 connected to the second low-voltage NMOS tube 2061 is connected to the negative phase input end of the error amplification module 201.

[0046] In this embodiment, the phase generating module (CKPhasegenerator) 303 can output different clock signals to the charge pump module 204 according to the different levels of the error amplifier module 201. In a possible implementation, when the output end of the error amplifier module 201 is at a low level, the charge pump module 204 is used to pull up the output voltage. The charge pump module 204 can output positive charge to increase the voltage. Figure 3 (a) in the figure shows the structure of the charge pump module 204. It can be seen that the connection method of the charge pump module 204 is the same as that of the above Figure 2 The circuit structure of the charge pump module 204 shown has the same wiring method.

[0047] In another possible implementation, when the output terminal of the error amplification module 201 is at a high level, the charge pump module 204 is used to appropriately lower the voltage value. The charge pump module 204 can output negative charge to reduce the voltage. Figure 3 (b) in FIG. 1 shows a structural diagram of the charge pump module 204. It can be seen that the connection method of the charge pump module 204 is similar to that of FIG. Figure 2The difference between the charge pump modules shown is that: the first capacitor C1 and the second capacitor C2 are both connected to the same clock signal, the gate of the first NMOS tube M1, the source of the second NMOS tube M2 and the source of the fourth NMOS tube M4 are all connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is connected to the first clock signal CK, the gate of the second NMOS tube M2, the source of the first NMOS tube M1 and the source of the third NMOS tube M3 are all connected to the first end of the first capacitor C1, the gate of the third NMOS tube M2 and the gate of the fourth NMOS tube M4 are both connected to the first clock signal CK, when CK='1', the capacitor is charged, and when CK='0', the capacitor voltage is discharged to the output end.

[0048] In summary, by adopting the above technical solution, the advantage of the present invention is that the on-resistance of the low-voltage NMOS tube under the same area is much smaller than that of the high-voltage MOS tube, so the area of ​​the MOS tube can be saved; at the same time, when the area of ​​the MOS tube is reduced, its parasitic capacitance is also small, which can improve the efficiency of the charge pump module and assist in the area of ​​the driving circuit. On the one hand, the charge pump module is applied to the output stage of the structure of the low-voltage difference linear regulator. By inputting clock signals of different amplitudes, the charge pump module can output voltages of different sizes, which can meet the needs of different application scenarios; on the other hand, the use of the first low-voltage NMOS tube and the second low-voltage NMOS tube with lower threshold voltage can reduce the restriction on the output voltage range, and the device size is smaller. Compared with the LDO of the PMOS output stage, the power supply rejection ratio and loop stability can be improved.

[0049] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application shall be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A low voltage dropout linear regulator, characterized in that: include: Error amplification module, clock generation module, level conversion module, charge pump module, first low-voltage NMOS tube and output feedback module; wherein: The error amplification module comprises a positive phase input terminal, a negative phase input terminal and an output terminal, the positive phase input terminal inputs a reference voltage signal Vref; the output terminal is connected to the gate of the first low voltage NMOS tube; The source of the first low voltage NMOS tube outputs a correction voltage V VCO , the drain of the first low-voltage NMOS tube is connected to a power supply, and the first low-voltage NMOS tube is used to adjust the input voltage of the low-dropout linear regulator; The input end of the clock generation module is connected to the source of the first low-voltage NMOS tube, and is used to generate a first clock signal CK; the output end of the clock generation module is connected to the input end of the level conversion module; The level conversion module is used to convert the first clock signal CK into a second clock signal CK1, and the first clock signal CK and the second clock signal CK1 are connected to the charge pump module; The charge pump module comprises: a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a first capacitor C1 and a second capacitor C2; the charge pump module is used to output a boosted voltage Vgate1; The drain of the first NMOS tube M1 is connected to the drain of the second NMOS tube M2, the second end of the first capacitor C1 is connected to the first clock signal CK, and the second end of the second capacitor C2 is connected to the third clock signal CK_i; the gate of the first NMOS tube M1, the source of the second NMOS tube M2 and the source of the fourth NMOS tube M4 are all connected to the first end of the second capacitor C2, the source of the first NMOS tube M1, the gate of the second NMOS tube M2 and the source of the third NMOS tube M3 are all connected to the first end of the first capacitor C1, the gate of the third NMOS tube M3 is connected to the fourth clock signal CK1_i, the gate of the fourth NMOS tube M4 is connected to the second clock signal CK1, the drain of the third NMOS tube M3 is connected to the gate of the second low-voltage NMOS tube, and the drain of the fourth NMOS tube M4 is connected to the gate of the second low-voltage NMOS tube, wherein the third clock signal CK_i is an inverted clock signal of the first clock signal CK, and the fourth clock signal CK1_i is an inverted clock signal of the second clock signal CK1; The output feedback module includes a second low-voltage NMOS tube and a feedback resistor, which is used to adjust the output voltage of the low-voltage difference linear regulator; Among them, the output end of the charge pump module is connected to the gate of the second low-voltage NMOS tube; the source of the second low-voltage NMOS tube is connected to one end of the feedback resistor, the other end of the feedback resistor is grounded, and the connection point is the output end of the low-voltage difference linear regulator; the drain of the second low-voltage NMOS tube is connected to the power supply; the active end of the feedback resistor connected to the second low-voltage NMOS tube is connected to the negative phase input end of the error amplification module.

2. The low voltage dropout linear regulator according to claim 1, characterized in that: The error amplification module is a single-stage amplification structure or a multi-stage amplification structure.

3. The low voltage dropout linear regulator according to any one of claims 1 to 2, characterized in that: The first filter capacitor C4 is also included; one end of the first filter capacitor C4 is coupled to the gate of the second low-voltage NMOS tube, and the other end of the first filter capacitor C4 is grounded.

4. The low voltage dropout linear regulator according to any one of claims 1 to 2, characterized in that: Also includes a second filter capacitor C3; One end of the second filter capacitor C3 is coupled to the gate of the second low-voltage NMOS transistor, and the other end of the second filter capacitor C3 is coupled to the source of the first low-voltage NMOS transistor.

5. A low voltage dropout linear regulator, characterized in that: include: Error amplification module, clock generation module, phase generation module, charge pump module and output feedback module; wherein: The error amplification module comprises a positive phase input terminal, a negative phase input terminal and an output terminal, the positive phase input terminal inputs a reference voltage signal Vref; the output terminal is connected to the first input terminal of the phase generation module; The output end of the clock generation module is connected to the second input end of the phase generation module, and the clock generation module is used to generate a first clock signal CK; The phase generation module is used to convert the first clock signal CK into a second clock signal CK1, and the first clock signal CK and the second clock signal CK1 are connected to the charge pump module; The charge pump module includes: a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a first capacitor C1 and a second capacitor C2; the charge pump module is used to output an adjustment voltage Vgate2 according to the output polarity of the output end of the error amplification module; wherein the drain of the first NMOS tube M1 is connected to the drain of the second NMOS tube M2, the second end of the first capacitor C1 is connected to the first clock signal CK, and the second end of the second capacitor C2 is connected to the third clock signal CK_i; the gate of the first NMOS tube M1, the source of the second NMOS tube M2 and the source of the fourth NMOS tube M4 are all connected to the first end of the second capacitor C2, the source of the first NMOS tube M1, the gate of the second NMOS tube M2 and the source of the third NMOS tube M3 are all connected to the first end of the first capacitor C1, the gate of the third NMOS tube M3 is connected to the fourth clock signal CK1_i, the gate of the fourth NMOS tube M4 is connected to the second clock signal CK1, the drain of the third NMOS tube M3 is connected to the gate of the second low-voltage NMOS tube, and the drain of the fourth NMOS tube M4 is connected to the gate of the second low-voltage NMOS tube, wherein the third clock signal CK_i is an inverted clock signal of the first clock signal CK, and the fourth clock signal CK1_i is an inverted clock signal of the second clock signal CK1; or The drain of the first NMOS tube M1 is connected to the drain of the second NMOS tube M2, and the second end of the first capacitor C1 and the second end of the second capacitor C2 are both connected to the first clock signal CK; the gate of the first NMOS tube M1, the source of the second NMOS tube M2 and the source of the fourth NMOS tube M4 are all connected to the first end of the second capacitor C2, the gate of the second NMOS tube M2, the source of the first NMOS tube M1 and the source of the third NMOS tube M3 are all connected to the first end of the first capacitor C1, the gate of the third NMOS tube M3 and the gate of the fourth NMOS tube M4 are both connected to the first clock signal CK, the drain of the third NMOS tube M3 is connected to the gate of the second low-voltage NMOS tube, and the drain of the fourth NMOS tube M4 is connected to the gate of the second low-voltage NMOS tube; The output feedback module includes a second low-voltage NMOS tube and a feedback resistor, which is used to adjust the output voltage of the low-voltage difference linear regulator; Among them, the output end of the charge pump module is connected to the gate of the second low-voltage NMOS tube; the source of the second low-voltage NMOS tube is connected to one end of the feedback resistor, the other end of the feedback resistor is grounded, and the connection point is the output end of the low-voltage difference linear regulator; the drain of the second low-voltage NMOS tube is connected to the power supply; the active end of the feedback resistor connected to the second low-voltage NMOS tube is connected to the negative phase input end of the error amplification module; the output end of the phase generation module is connected to the input end of the charge pump module.

6. The low voltage dropout linear regulator according to claim 5, characterized in that: The error amplification module is a single-stage amplification structure or a multi-stage amplification structure.

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