Power converter for high power density applications

Abstract

A power semiconductor package includes a leadframe, a semiconductor chip, and a molded package. The leadframe includes a raised portion including a source portion; a drain portion; and a plurality of leads. The semiconductor chip includes a metal oxide semiconductor field effect transistor (MOSFET) disposed on the leadframe. The semiconductor chip includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source portion of the raised portion of the leadframe. The semiconductor chip functions as a low-side field effect transistor as a flip chip connected to a heat sink by a first thermal interface material. A high-side field effect transistor is connected to the heat sink by a second thermal interface material. The low-side field effect transistor and the high-side field effect transistor are mounted on a printed circuit board.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to a power converter for high power density applications. More specifically, the present invention relates to a power converter with a heat sink that reduces electromagnetic interference (EMI) emissions. BACKGROUND

[0002] In recent years, the power density target of power converters has increased to higher levels. High power density applications refer to more than 1200 kilowatts per cubic meter. For example, a USB-C charger with a power density of 1500 kilowatts per cubic meter is considered a high power density application. For example, an electric vehicle on-board charger with a power density of 3000 kilowatts per cubic meter is considered a high power density application. As shown in FIG. 1, two field effect transistors (FETs) are typically connected in series as a high-side FET and a low-side FET for power converter applications. Figure 1 The requirements for power converters for high power density applications include lower package parasitic capacitance and inductance at the FET component level, lower electromagnetic interference (EMI) noise at the converter component level, better heat dissipation capability, and easier printed circuit board design.

[0003] Conventional power converters experience high EMI noise in high power density applications. This results in a reduction in switching frequency (e.g., to 75%) and an increase in thermal interface material thickness (e.g., from 50 microns to 100 microns), which reduces heat dissipation efficiency, power density, and power converter efficiency. It is necessary to improve power converters to meet the challenges of high power density applications. SUMMARY

[0004] A power semiconductor package is disclosed, including a lead frame, a semiconductor chip, and a molded package. The lead frame includes a raised portion including a source portion, a drain portion, and a plurality of leads. The semiconductor chip includes a metal oxide semiconductor field effect transistor (MOSFET) disposed on the lead frame. The semiconductor chip includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source portion of the raised portion of the lead frame.

[0005] The semiconductor chip functions as a low-side field effect transistor as a flip-chip connected to a heat sink by a first thermal interface material. A high-side field effect transistor is connected to the heat sink by a second thermal interface material. The low-side field effect transistor and the high-side field effect transistor are mounted on a printed circuit board. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A circuit diagram representing a conventional power converter.

[0007] Figure 2A This is a bottom view of a traditional power semiconductor package. Figure 2B This represents its side view. Figure 2C This represents its top view.

[0008] Figure 3A This is a bottom view of a power semiconductor package, as shown in an example of the present invention. Figure 3B This represents its side view. Figure 3C This represents its top view.

[0009] Figure 4 In an example of the present invention, a printed circuit board, a low-end field-effect transistor, a high-end field-effect transistor, and a heat sink are included.

[0010] Figure 5A In the example of this invention, Figure 3A , 3B The top view of the molded power semiconductor package shown in the dashed line in Figure 3C. Figure 5B This represents its side view.

[0011] Figure 6A , 6B 6C and 6D represent simulated EMI data in the examples of this invention. Detailed Implementation

[0012] Figure 2A This invention represents the present invention. Figure 4 A bottom view of the power semiconductor package 100 of the high-end field-effect transistor 320 used as a power converter. Figure 2B This represents its side view. Figure 2C This is a top view. The power semiconductor package 100 includes a bottom source electrode exposed from the bottom surface of a molded package 190, a top drain electrode 142 exposed from the top surface of the molded package 190, and a plurality of leads 192 extending to the bottom side, wherein the bottom surfaces of the plurality of leads 192 are substantially coplanar with the bottom surface of the molded package 190. The molded package 190 has a first thickness measured from the bottom surface to the top surface of the molded package 190. The plurality of leads 192 include at least a high-side source lead 192S, a high-side gate lead 192G, and a high-side drain lead 192D. The top drain electrode 142 exposed from the top surface of the molded package 190 is electrically connected to the high-side drain lead 192D. When the field-effect transistor of the power semiconductor package 100 performs high-power switching operation, the top drain electrode 142 exposed from the top surface of the molded package 190 significantly improves heat dissipation.

[0013] Figure 3A This invention represents Figure 4FIG. 4 is a bottom view of a power semiconductor package 200 used as a low side field effect transistor 340 of a power converter, Figure 3B FIG. 5 is a side view of the power semiconductor package 200 of FIG. 4, Figure 3C FIG. 6 is a top view of the power semiconductor package 200 of FIG. 4. The power semiconductor package 200 includes a top source electrode 241 exposed from a top surface of a molded package 290 and a plurality of leads 292 having a bottom surface substantially coplanar with a bottom surface of the molded package 290. The molded package 290 has a second thickness measured from a lower surface to a top surface of the molded package 290. The plurality of leads 292 includes at least a low side source lead 292S, a low side gate lead 292G, and a low side drain lead 292D. The top source electrode 241 exposed from the top surface of the molded package 290 is conductively connected to the low side source lead 292S. The top source electrode 241 exposed from the top surface of the molded package 290 greatly improves heat dissipation when the field effect transistor of the power semiconductor package 200 is operated at high power switching. Figure 5A FIG. 7 is a top view of the power semiconductor package 200 of FIG. 4 having a dashed molded package (transparent to show internal components), Figure 5B FIG. 8 is a side view of the power semiconductor package 200 of FIG. 7. The power semiconductor package 200 includes Figure 5B a lead frame 410, Figure 5A and Figure 5B a semiconductor chip 420 (shown in dashed lines) and a molded package 290. The lead frame 410 includes a raised portion 440 including a source portion 442, a drain portion 462, and a plurality of leads 292.

[0014] The semiconductor chip 420 includes a metal oxide semiconductor field effect transistor (MOSFET) 422 disposed on the lead frame 410. The semiconductor chip 420 includes a source electrode 421, a drain electrode 423, and a gate electrode 425. The source electrode 422 is disposed on a first surface 431 of the semiconductor chip 420. The source 421 is conductively and mechanically connected to the source portion 442 of the raised portion 440 of the lead frame 410. The drain 423 is disposed on a second surface 433 of the semiconductor chip 420. The drain electrode 423 is conductively and mechanically connected to the drain portion 462 of the lead frame 420. The gate electrode 425 is disposed on the first surface 431 of the semiconductor chip 420. The gate electrode 425 is connected to a gate lead 499 of the plurality of leads 292.

[0015] The second surface 433 of the semiconductor chip 420 is opposite the first surface 431 of the semiconductor chip 420. A majority of the semiconductor chip 420 and the lead frame 410 are embedded in the molded package 290. A majority of the raised portion 440 is embedded in the molded package 390. Majority refers to greater than 50%. A top surface area of the source portion 442 of the raised portion 440 is exposed from the top surface of the molded package 290. Figure 3CThe top source electrode 241 shown is exposed from the molded package 290. In one example, the top surface region of the source portion 442 of the raised portion 440... Figure 3C The top source electrode 241 shown is configured to pass through Figure 4 Thermal interface material 342 connected to Figure 4 The heatsink 360 shown reduces electromagnetic interference (EMI) noise for high power density applications.

[0016] In an example of the present invention, the top surface region of the source portion 442 of the raised portion 440 Figure 3C The top source electrode 241 shown is L-shaped to accommodate the gate electrode 425 in region 291 of the molded package 290.

[0017] In one example, the top surface area of ​​the source portion 442 of the raised portion 440 is... Figure 3C The surface area of ​​the top source electrode 241 shown in the power semiconductor package 200 Figure 3B The area of ​​the top surface 201 shown is between 50% and 90%.

[0018] In another example, the top surface area of ​​the source portion 442 of the raised portion 440 Figure 3C The surface area of ​​the top source electrode 241 shown in the power semiconductor package 200 is... Figure 3B The area of ​​the top surface 201 shown is in the range of 60% to 70%.

[0019] In an example of the present invention, the power semiconductor package 200 is a gull-wing package (GWPAK) such that the corresponding exposed portion of each of the plurality of leads 292 folds out from the molded package 290.

[0020] Figure 4A cross-sectional view of the power converter 300 is shown. The power converter 300 includes a printed circuit board 310, a low-side field effect transistor 340 and a high-side field effect transistor 320 mounted on the printed circuit board 310, and a heat sink 360 disposed on the low-side field effect transistor 340 and the high-side field effect transistor 320. In the example of the present application, the printed circuit board 310 includes a plurality of contact pads or copper traces 312 for connecting to the low-side field effect transistor 340 and the high-side field effect transistor 320 mounted thereon. The plurality of contact pads or copper traces 312 includes a switch node pad 312C, a high-side drain pad 312D, and a low-side source pad 312S. The source lead 192S of the high-side field effect transistor 320 and the drain lead 292D of the low-side field effect transistor 340 are electrically connected to the switch node pad 312C on the printed circuit board 310. The drain lead 192D of the high-side field effect transistor 320 is electrically connected to the high-side drain pad 312D of the printed circuit board 310, and the source lead 292S of the low-side field effect transistor 340 is electrically connected to the low-side source pad 312S on the printed circuit board 310. The plurality of contact pads or copper traces 312 can further include a high-side gate pad (not shown) electrically connected to the gate lead 192G of the high-side field effect transistor 320 and a low-side gate pad (not shown) electrically connected to the gate lead 292G of the low-side field effect transistor 340.

[0021] In the example of the present application, the low-side field effect transistor 340 is coupled to the heat sink 360 by a thermal interface material 342. The high-side field effect transistor 320 is coupled to the heat sink 360 by a thermal interface material 322. The heat sink 360 further improves the heat dissipation of the high-side field effect transistor 320 and the low-side field effect transistor 340, thereby improving the power handling capability of the power converter 300.

[0022] In the example of the present application, the thermal interface material 322 and the thermal interface material 342 have a thermal conductivity greater than 15000 Watts per meter Kelvin. In one example, the thermal interface material 322 and the thermal interface material 342 are made of a ceramic filled silicone rubber material. In another example, the thermal interface material 322 and the thermal interface material 342 are made of a pyrolytic graphite material. In one example, the first thickness of the molded package 190 is different from the second thickness of the molded package 290. In another example, the first thickness of the molded package 190 plus the thermal interface material 322 is substantially the same as the second thickness of the molded package 290 plus the thermal interface material 342. In another example, the thickness of the thermal interface material 322 is substantially the same as the thickness of the thermal interface material 342. In another example, the first thickness of the molded package 190 is substantially the same as the second thickness of the molded package 290.

[0023] In an example of the invention, the thickness of thermal interface material 322 is in the range of 45 microns to 55 microns. The thickness of thermal interface material 342 is in the range of 45 microns to 55 microns.

[0024] In an example of the invention, power semiconductor package 200 is used as a low-side field effect transistor 340. Figure 4 The top source electrode 241 is shown directly connected to the bottom surface of thermal interface material 342. The top surface 348 of thermal interface material 342 is directly connected to the bottom surface 368 of heat sink 360. A high-side parasitic capacitor is formed between the top source electrode 241 and the heat sink 360, with thermal interface material 342 serving as a dielectric layer separating the two electrodes of the high-side parasitic capacitor. Figure 3C

[0025] In an example of the invention, power semiconductor package 100 is used as a low-side field effect transistor 340. The top drain electrode 142 at the top surface region 328 of high-side field effect transistor 320 is coupled to heat sink 360 through thermal interface material 322. The top surface region 328 of high-side field effect transistor 320 is directly attached to the bottom surface 337 of thermal interface material 322. The top surface 339 of thermal interface material 322 is directly attached to the bottom surface 368 of heat sink 360. A low-side parasitic capacitor is formed between the top drain electrode 142 and the heat sink 360, with thermal interface material 322 serving as a dielectric layer separating the two electrodes of the low-side parasitic capacitor. For typical applications, the high-side and low-side parasitic capacitances are in the range of about 200 pF. Figure 4

[0026] In an example of the invention, printed circuit board 310 includes a bottom surface 350 and a top surface 352. High-side field effect transistor 320 and low-side field effect transistor 340 are mounted in the top surface 352 of printed circuit board 310, sandwiched between printed circuit board 320 and heat sink 360. Heat sink 360 has a bottom surface facing and parallel to the top surface 352 of printed circuit board 310.

[0027] In an example of the invention in a high power density power converter application, the voltage of the source electrode of low-side field effect transistor 340 is fixed at ground. The voltage of the drain (top drain 142) of high-side field effect transistor 320 is fixed at bus voltage. The voltage of heat sink 360 can be floating or tied to a fixed voltage, such as the ground voltage of the source electrode of low-side field effect transistor 340 or the bus voltage of the top drain electrode 142 of high-side field effect transistor 320. In any case, since there is no voltage change during switching operation for both the high-side parasitic capacitor and the low-side parasitic capacitor, the parasitic high-side capacitor and the parasitic low-side capacitor attributed to heat sink 360 will not emit EMI regardless of the switching operation of the converter. Thus, the EMI of the converter is minimized.​​

[0028] Figure 6A , 6B 6C and 6D represent simulated EMI data in the examples of this invention. The horizontal axis represents the switching frequency on a linear scale, starting from 0 Hz and increasing by 20 MHz in each segment. Figure 6A and 6B The vertical axis in the figure represents common-mode EMI noise with the same linear scale. Figure 6C and 6D The vertical axis represents differential-mode EMI noise with the same linear scale. It is worth noting that in most applications, the switching frequency is in the range below 30 MHz, which is defined by... Figure 6A Arrow 822 Figure 6B Arrow 842 Figure 6C Arrow 862 and Figure 6D Arrow 882 indicates.

[0029] Figure 6A This indicates a case used in a conventional power converter, where the top surface electrode of the low-side field transistor is the drain electrode connected to the switching node. Figure 6B Indicates that according to Figure 4 The power converter of the present invention is shown. For the range below 30 MHz, Figure 6A The highest common-mode EMI noise level is 7.8, while Figure 6B The highest common-mode EMI noise is 0.1.

[0030] Figure 6C This indicates a case used in a conventional power converter, where the top surface electrode of the low-side field transistor is the drain electrode connected to the switching node. Figure 6D Indicates that according to Figure 4 The invention relates to the power converter. For the range below 30 MHz, Figure 6C The highest differential-mode EMI noise level is 6.0. Figure 6D The highest common-mode EMI noise level is 0.1.

[0031] The converter proposed according to the present invention improves high power density applications of 1200 kW / m³ or higher. For example, the converter proposed according to the present invention is suitable for USB-C chargers with a power density of 1500 kW / m³ or higher. For example, the converter proposed according to the present invention is suitable for on-board chargers for electric vehicles with a power density of 3000 kW / m³ or higher.

[0032] Those skilled in the art will recognize that modifications to the embodiments disclosed in this invention are possible. For example, the top surface region of the source portion 442 of the raised portion 440 exposed from the molded package 290. Figure 3CThe size of the top source electrode 241 shown can be varied. Other modifications, as would be apparent to one of ordinary skill in the art, are considered within the scope of the invention as defined by the claims.

Claims

1. A high power density power converter comprising: a printed circuit board comprising a plurality of mutually isolated contact pads, the plurality of contact pads including a high-side drain pad and a low-side source pad; a high-side field effect transistor mounted on the printed circuit board, the high-side field effect transistor including a high-side drain lead electrically connected to the high-side drain pad of the printed circuit board; and a top drain electrode electrically connected to the high-side drain lead; a low-side field effect transistor mounted on the printed circuit board, the low-side field effect transistor including a low-side source lead electrically connected to the low-side source pad of the printed circuit board; and a top source electrode electrically connected to the low-side source lead; a heat sink positioned above the high-side field effect transistor and the low-side field effect transistor; a first thermal interface material layer coupling the top drain electrode of the high-side field effect transistor to the heat sink; and a second thermal interface material layer coupling the top source electrode of the low-side field effect transistor to the heat sink.

2. The high power density power converter of claim 1, wherein the plurality of contact pads of the printed circuit board further includes a switch node pad; wherein the high-side field effect transistor further includes a high-side source lead connected to the switch node pad of the printed circuit board; and wherein the low-side field effect transistor further includes a low-side drain lead connected to the switch node pad.

3. The high power density power converter of claim 2, wherein the plurality of contact pads of the printed circuit board further includes a high-side gate pad and a low-side gate pad; wherein the high-side field effect transistor further includes a high-side gate lead connected to the high-side gate pad of the printed circuit board; and wherein the low-side field effect transistor further includes a low-side gate lead connected to the low-side gate pad of the printed circuit board.

4. The high power density power converter of claim 2, wherein the high-side field effect transistor and the low-side field effect transistor are mounted on a top surface of the printed circuit board; wherein the high-side field effect transistor is sandwiched between the printed circuit board and the heat sink; and wherein the low-side field effect transistor is sandwiched between the printed circuit board and the heat sink.

5. The high power density power converter of claim 4, wherein the heat sink includes a bottom surface facing the top surface of the printed circuit board; and wherein the bottom surface of the heat sink is parallel to the top surface of the printed circuit board.

6. The high power density power converter of claim 4, wherein a thickness of the first thermal interface material layer is substantially equal to a thickness of the second thermal interface material layer.

7. The high power density power converter of claim 4, wherein the high-side field effect transistor further includes a first molded package having a first thickness; and wherein the low-side field effect transistor further includes a second molded package having a second thickness.

8. The high power density power converter of claim 7, wherein the first thickness is the same as the second thickness.

9. The high power density power converter of claim 7, wherein the top source electrode of the low-side field effect transistor has an L-shape, exposed from a top surface of the second molded package. ​ ​ ​ 10. The high power density power converter of claim 7, wherein an area of the top source electrode region of the low side field effect transistor exposed from a top surface of the second molded package is in a range of 50% to 90% of a top surface area of the low side field effect transistor package.

11. The high power density power converter of claim 7, wherein an area of the top source electrode region of the low side field effect transistor exposed from a top surface of the first molded package is in a range of 60% to 70% of a top surface area of the low side field effect transistor package.

12. The high power density power converter of claim 1, wherein a top drain electrode of the high side field effect transistor is connected to a fixed bus voltage; and wherein a top source electrode of the low side field effect transistor is connected to ground.

13. The high power density power converter of claim 1, wherein a thermal conductivity of the first thermal interface material and a thermal conductivity of the second thermal interface material is greater than 15000 Watts per meter Kelvin.

14. The high power density power converter of claim 13, wherein the first thermal interface material and the second thermal interface material is selected from a group consisting of a ceramic filled silicone rubber material and a pyrolytic graphite material.

15. The high power density power converter of claim 13, wherein a thickness of the first thermal interface material and a thickness of the second thermal interface material is in a range of 45 micrometers to 55 micrometers.

16. The high power density power converter of claim 1, wherein a thermal conductivity of the first thermal interface material and a thermal conductivity of the second thermal interface material is greater than 15000 Watts per meter Kelvin. ​

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