Probe card substrate, probe card, and wafer test system

Abstract

The application discloses a probe card substrate, a probe card and a wafer testing system, and belongs to the technical field of wafer testing. Current technology cannot compensate for voltage loss generated during the process of connecting the power supply PAD of the probe card substrate to the power supply PAD of the wafer under test, resulting in inaccurate power supply voltage of the power supply PAD of the wafer under test. The application divides the power supply DPS of the testing machine into force terminals and sense terminals to provide voltage. At the same time, the power supply PAD of the probe card substrate and the respective corresponding power supply probes are divided into two groups that are not connected and are connected to the force terminals and the sense terminals respectively. During testing, the probes contact the wafer power supply PAD, and the force terminals and the sense terminals will be short-circuited at the wafer under test. At this time, the short-circuit point is closest to the connection point of the force terminal and the device under test, and the voltage provided by the force terminal to the device under test can be more accurate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wafer testing, and more particularly to a probe card substrate, a probe card and a wafer testing system. BACKGROUND

[0002] Wafer testing is an important part of integrated circuit design and manufacturing, and is used to ensure that the products of integrated circuit design and manufacturing meet the requirements of their specifications. A wafer is composed of a plurality of dies, and each die has a plurality of pads, including power pads, ground pads and input / output pads. A tester contacts the pads on the dies through probes and runs test software to test the dies. During the wafer testing stage, design defects and manufacturing defects of the products can be found in advance, which helps to improve product design and manufacturing and save packaging costs of defective products.

[0003] In wafer testing, the accuracy of the supply voltage provided by the tester to the power pads of the wafer under test is increasingly high. During the transmission of the supply voltage provided by the tester to the power pads of the wafer under test, the voltage drop caused by the resistance of the wire itself is large enough to be ignored, and this voltage drop will affect the test results, especially for low-voltage and high-current test items. Therefore, most testers use Kelvin connection, i.e., the DPS is divided into force terminals and sense terminals to provide voltage, wherein the force terminals are used to provide excitation, and the sense terminals feed back the line loss voltage drop generated during the transmission of the excitation to the device under test to the force terminals, and the force terminals adjust the excitation provided according to the feedback results to compensate for the line loss voltage drop. The force terminals and the sense terminals must be short-circuited, and the short-circuiting position thereof should be close to the connection point of the force terminals and the device under test. The closer the short-circuiting position is to the connection point, the more accurate the value to be compensated for by the sense terminals fed back to the force terminals, and the more accurate the voltage provided by the force terminals to the device under test. Therefore, the short-circuiting position of the force terminals and the sense terminals is very important.

[0004] The existing technical solutions short-circuit the force and the sense on the probe card substrate, so the sense cannot feed back the voltage loss generated during the transmission of the power pads of the probe card substrate to the power pads of the wafer under test, and the force terminals cannot compensate for the voltage loss generated in this section. This has little effect on ordinary test items, but for low-voltage and high-current test items that differ by tens of millivolts, the effect is great. SUMMARY

[0005] 1. Technical problem to be solved

[0006] In view of the problem that the voltage loss generated in the process from the power PAD of the probe card substrate to the power PAD of the wafer under test cannot be compensated in the prior art, the application provides a probe card substrate, a probe card and a wafer testing system, which can compensate the voltage loss generated in the process from the power PAD of the probe card substrate to the power PAD of the wafer under test, and can improve the voltage accuracy when the power supply DPS of the testing machine is transmitted to the power PAD of the wafer under test.

[0007] 2. Technical solution

[0008] To solve the above technical problems, the technical solution provided by the application is:

[0009] In a first aspect, a probe card substrate is provided.

[0010] The substrate includes a first surface and a second surface. The first surface faces the testing machine, and the second surface faces the surface to be tested of the wafer.

[0011] The power PADs on the substrate from the same power supply are divided into two groups that are independent and not connected to each other. The first group includes at least one power PAD, which is internally short-circuited together; the second group includes the remaining power PADs, which are also internally short-circuited together. Further, the power PADs in the first group are connected to the sense terminal of the power supply DPS of the testing machine, and the power PADs in the second group are connected to the force terminal of the power supply DPS of the testing machine.

[0012] The GND PAD of the substrate is connected to the GND resource of the testing machine.

[0013] The line width of the connection line of the substrate to the force terminal and the sense terminal is calculated according to the actual power supply current.

[0014] Preferably, the probe card substrate is a PCB board.

[0015] Preferably, the internal short-circuiting mode of the power PADs in the first group is that a first short-circuiting structure covers all the PADs in the first group; the internal short-circuiting mode of the power PADs in the second group is that a second short-circuiting structure covers all the power PADs in the second group; and the first short-circuiting structure and the second short-circuiting structure are independent of each other.

[0016] Preferably, the first short-circuiting structure is a first copper strip, and the second short-circuiting structure is a second copper strip.

[0017] In a second aspect, a probe card is provided, which includes the probe card substrate of the first aspect, probes and an insulating fixing material. One end of the probe is fixed to the second surface of the substrate by the insulating fixing material, which is a fixed end used to connect the PAD on the substrate; the other end of the probe is a free end used to contact the surface to be tested on the wafer under test during testing.

[0018] At least one of the probes of the probe card is used to connect the GND PAD on the wafer to the GND PAD on the substrate.

[0019] The probe connected to the power supply PAD of the substrate is a power supply probe, which is divided into two groups: the first group at least includes one probe, the fixed end of the probe of the first group is connected to the first group of power supply PAD on the substrate, is connected to the sense terminal, and is used to connect the sense terminal to the power supply PAD of the wafer; the second group is the remaining probe, the fixed end of the probe of the second group is connected to the second group of power supply PAD on the substrate, is connected to the force terminal, and is used to connect the force terminal to the power supply PAD of the wafer.

[0020] In a third aspect, the present application provides a wafer test system. The test system includes a tester and a probe card, and is used to test a wafer.

[0021] During the test, the free ends of all the probes on the probe card are in contact with the surface of the wafer to be tested, wherein the power supply probe is connected to the power supply PAD of the wafer. The PADs of the same power supply on a die of the wafer are connected in the internal structure of the wafer, at this time, the force and the sense of the tester are realized by short-circuiting at the wafer end via the power supply PAD of the substrate on the probe card, the probe and the power supply PAD of the wafer. The design avoids that the force and the sense are short-circuited together at the power supply PAD on the substrate, and the sense can feed back the voltage loss from the power supply PAD on the substrate to the power supply PAD at the wafer end to the force, and the force compensates the voltage loss according to the feedback result, so that the voltage of the power supply DPS of the tester transmitted to the power supply PAD at the wafer end is basically consistent with the voltage value expected to be set by the test program.

[0022] The technical solutions of the above three aspects are based on the single-die test design on the wafer, and the multi-die parallel test is only a repetition of the single-die scheme.

[0023] 3. Advantages

[0024] Compared with the prior art, the present application has the following advantages:

[0025] Because the force terminal and the sense terminal are short-circuited together at the wafer end, the voltage to be compensated fed back by the sense terminal to the force terminal is more accurate, the voltage of the power supply DPS of the tester transmitted to the power supply PAD at the wafer end is basically consistent with the voltage value expected to be set by the test program, the accuracy of the test result is improved, especially for the low-voltage and high-current test item which will greatly affect the accuracy of the test result by several tens of millivolts. The present application is realized only by changing the design of the probe card, is easy to implement, and does not increase the cost. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a schematic diagram of the prior art force and sense connection method;

[0027] Figure 2 is a schematic diagram of the prior art force and sense connection method of the probe card substrate connection method;

[0028] Figure 3 is a schematic diagram of the force and sense connection method of the present application;

[0029] Figure 4 is a schematic diagram of the force and sense connection method of the present application of the probe card substrate connection method.

[0030] Explanation of reference numerals in the drawings:

[0031] 1, tester; 2, force terminal; 3, sense terminal; 4, probe card substrate; 5, power supply PAD of the same power supply on the probe card substrate; 51, first group of power supply PADs on the probe card substrate; 52, second group of power supply PADs on the probe card substrate; 6, copper bar; 61, first copper bar; 62, second copper bar; 7, probe; 71, first group of probes; 72, second group of probes; 8, power supply PAD on the wafer under test; 9, wafer under test; 10, GND PAD on the wafer under test; 11, GND PAD on the probe card substrate; 12, GND resource; 13, a die on the wafer under test. DETAILED DESCRIPTION

[0032] The technical solutions in the present application will be described clearly and completely below in conjunction with the drawings.

[0033] In wafer testing, some test items have a higher requirement for the accuracy of the power supply voltage, and a difference of tens of millivolts will affect the test results, typical examples being low-voltage high-current test items.

[0034] The prior art solution is to realize short-circuiting of the force terminal and the sense terminal on the probe card substrate 4 to complete compensation for voltage loss. For example, Figure 1As shown, when the tester 1 provides the power supply DPS to the probe card substrate 4, all the power supply PADs 5 of the same power supply on the probe card substrate 4 are connected together by a copper bar 6, and here only 3 power supply PADs are drawn to be connected together by the copper bar 6. Then the force terminal 2 is connected to the copper bar 6, and the sense terminal is also connected to the copper bar 6, and the force terminal 2 and the sense terminal 3 are short-circuited on the copper bar 6 on the first surface of the probe card substrate 4, and the power supply PADs 5 of the probe card substrate 4 are connected from the second surface of the probe card substrate 4 to the fixed end of the probe 7, and finally the free end of the probe 7 is connected to the power supply PAD 8 on the wafer under test. The ground of the tester, i.e. the GND resource 12, is connected to the ground PAD 11, i.e. the GND PAD, on the first surface of the probe card substrate 4, the second surface of the probe card substrate 4, the probe 7 and the ground GND PAD 10 on the wafer under test in turn. At this time, the force terminal 2 and the sense terminal 3 are short-circuited on the power supply PADs 5 of the probe card substrate 4.

[0035] During testing, when the excitation provided by the force terminal 2 reaches the short-circuit point, a voltage loss is generated, and this loss can be fed back to the force terminal 2 through the sense terminal 3. However, the transmission loss between the power supply PADs 5 on the probe card substrate 4 and the power supply PADs 8 on the wafer under test cannot be fed back to the force terminal 2. Therefore, the force terminal 2 cannot compensate for the voltage transmission loss between the probe card and the wafer under test. This part of the loss will cause the actual voltage of the power supply PAD 8 on the wafer under test to be less than the supply voltage set by the test program, and for low-voltage and high-current test items, which have relatively high requirements for voltage, the test results will be directly affected.

[0036] Therefore, for low-voltage and high-current test items and other test items that require accurate power supply, the voltage transmission loss between the probe card and the wafer under test cannot be ignored and needs to be compensated.

[0037] The application provides a solution, which can compensate for the voltage transmission loss between the power supply PADs of the probe card substrate and the power supply PADs of the wafer under test, and can improve the voltage accuracy of the power supply DPS of the tester when transmitted to the power supply PADs on the wafer under test.

[0038] Embodiment 1

[0039] The application provides a probe card substrate, and preferably, a printed circuit board (PCB) is used.

[0040] As Figure 2As shown, taking the low-voltage large-current test item as an example, the power supply PADs of the low-voltage large-current test item on the probe card substrate 4 are divided into two groups that are not connected to each other: the first group is at least one power supply PAD 51, which is internally short-circuited together; the second group is the remaining power supply PADs 52, and the power supply PADs 52 in the second group are also internally short-circuited together. The internal short-circuiting of the power supply PADs can be performed by a short-circuiting structure covering all power supply PADs in the same group, and gold, copper, silver, aluminum or alloy conductive metals can be selected as the short-circuiting structure material.

[0041] To facilitate subsequent wiring, the preferred short-circuiting implementation is that the first short-circuiting structure is a first copper strip 61 covering all power supply PADs 51 in the first group, and the second short-circuiting structure is a second copper strip 62 covering all power supply PADs 52 in the second group.

[0042] Figure 2 is a schematic diagram, only 2 power supply PADs 52 are connected together by the second copper strip 62, and in actual application, the number of PADs can be increased as needed. Further, the width of the first copper strip 61 and the second copper strip 62 is determined according to the actual current size, and the greater the current, the greater the width of the copper strip, and vice versa, the line width can be reduced.

[0043] The first group of power supply PADs 51 is connected to the sense terminal 3 of the DPS provided by the test machine 1, and the second group of power supply PADs 52 is connected to the force terminal 2 of the DPS provided by the test machine 1, at which time the force terminal 2 and the sense terminal 3 are independent and not connected to each other on the probe card substrate 4.

[0044] The first surface of the probe card substrate 4 also includes a ground GND PAD 11 for connecting to the ground GND resource 12 of the test machine.

[0045] The probe card substrate is preferably a PCB (printed circuit board).

[0046] Embodiment 2

[0047] The application provides a probe card, which comprises the probe card substrate provided in the first embodiment, and further comprises probes 7 and insulating fixing materials. One end of the probe 7 is fixed to the second surface of the substrate through the insulating fixing material, which is a fixed end for connecting to the PAD on the substrate; the other end of the probe 7 is a free end for contacting a surface to be tested on a wafer during testing.

[0048] Among them, at least one probe 7 is used to connect the ground GND PAD 10 on the wafer to the ground GND PAD 11 on the substrate of the probe card substrate 4.

[0049] Each power supply probe 7 corresponds to a power supply PAD 8 of a low-voltage and high-current test item of the wafer under test. The power supply probes are divided into two groups, the first group of probes 71 includes at least one probe, and the second group of probes 72 includes the remaining probes. The fixed end of the first group of probes 71 is connected to the first group of power supply PADs 51 on the substrate, and is used to connect the sense terminal 3 to the power supply PAD 8 of the wafer; the fixed end of the second group of probes 72 is connected to the second group of power supply PADs 52 on the substrate, and is used to connect the force terminal 2 to the power supply PAD 8 of the wafer.

[0050] Embodiment 3

[0051] The application provides a wafer test system, which includes a test machine and the probe card provided in Embodiment 2, and is used for testing a wafer. The substrate of the probe card is selected from a printed circuit board (PCB).

[0052] The test machine 1 is used to provide a power supply DPS to the substrate 4 of the probe card. The test machine power supply DPS uses a Kelvin connection, that is, the DPS is divided into a force terminal and a sense terminal to provide a voltage, wherein the force terminal is used to provide an excitation, and the sense terminal feeds back a line loss voltage drop generated in the process of transmitting the excitation to the device under test to the force terminal, and the force terminal adjusts the excitation provided according to the feedback result to compensate for the line loss voltage drop.

[0053] Specifically, taking a low-voltage and high-current test item as an example, during the test, the probe 7 is in contact with the surface of the wafer under test, wherein the first group of at least one probe 71 connects at least one power supply PAD 8 of the wafer under test to the sense terminal 3, and the second group of other probes 72 connects the remaining power supply PADs 8 of the wafer under test to the force terminal 2.

[0054] The same power supply inside a die 13 on the wafer under test 9 is connected, so the PADs 8 on the wafer under test 9 connected by the probe 71 and the probe 72 are connected internally. Therefore, the force terminal 2 and the sense terminal 3 are short-circuited together at the power supply PAD on the wafer under test. During the process in which the force terminal 2 provides an excitation voltage to the power supply PAD 8 of the wafer under test 9, power supply loss is generated, and the loss can be fed back to the force terminal 2 through the sense terminal 3, and the force terminal 2 can adjust the excitation voltage provided according to the feedback value, so that the actual voltage of the power supply PAD 9 on the wafer is equal to the power supply voltage set by the test program, and the result accuracy of the low-voltage and high-current test item is improved.

[0055] In the application, the force terminal 2 and the sense terminal 3 are shorted together at the power PAD on the wafer only when all the free ends of the probes on the probe card contact the surface of the wafer to be tested, avoiding the power PADs on the substrate from being shorted together, so that the voltage loss from the power PAD on the substrate to the power PAD on the wafer can be fed back to the force terminal 2 by the sense terminal 2, and the force terminal 2 can compensate for the voltage loss according to the feedback result, so that the voltage transmitted from the test machine power supply DPS to the power PAD on the wafer is basically consistent with the voltage value set by the test program, and the accuracy of the test result is improved, especially for the low-voltage and high-current test items which will greatly affect the accuracy of the test result if the difference is tens of millivolts.

[0056] Embodiment 4

[0057] Another embodiment provided in the application is a wafer test system, including a test machine and a probe card, for testing a wafer. The test machine power supply DPS uses Kelvin connection, i.e., the DPS is divided into a force terminal and a sense terminal to provide voltage, wherein the force terminal is used to provide excitation, and the sense terminal feeds back the line loss voltage drop generated in the process of transmitting the excitation to the device under test to the force terminal, and the force terminal adjusts the excitation provided according to the feedback result to compensate for the line loss voltage drop.

[0058] Only the force terminal and the sense terminal need to be shorted at the wafer end to be tested, and the probe card structure as described in Embodiment 2 above is not required, only the state of shorting the force terminal and the sense terminal by the test system after the probes of the probe card contact the surface of the wafer during testing needs to be ensured.

[0059] The above describes the application and its embodiments in a schematic manner, which is not restrictive, and the application can be realized in other specific forms without departing from the spirit or essential characteristics of the application. The embodiments shown in the drawings are only one of the embodiments of the application, and the actual structure is not limited thereto, and any reference signs in the claims should not limit the claims involved. Therefore, if a person skilled in the art is inspired by this, without departing from the spirit of the application, similar structural forms and embodiments can be designed without creative design, which should belong to the protection scope of the patent. In addition, the word "comprising" does not exclude other elements or steps, and the word "one" before an element does not exclude "multiple" elements. Multiple elements stated in a product claim can also be realized by software or hardware. The words "first", "second", etc. are used to represent names, and do not represent any specific order.

Claims

1. A probe card, characterized in that, it comprises a probe card substrate, probes and an insulating fixing material, the probe card substrate comprises a first surface and a second surface; wherein the first surface faces a tester and the second surface faces a surface to be tested of a wafer; the power supply PADs on the substrate from the same power supply are divided into two groups; the first group of power supply PADs comprises one power supply PAD, and the second group of power supply PADs comprises the rest of the power supply PADs; wherein the first group of power supply PADs are internally short-circuited and used to connect to the sense terminal of the power supply DPS of the tester; the second group of power supply PADs are internally short-circuited and used to connect to the force terminal of the power supply DPS of the tester; the GND PAD of the substrate is connected to the GND resource of the tester; one end of the probe is a fixed end, which is fixed to the second surface of the substrate by the insulating fixing material, and is used to connect to the PAD on the substrate; the other end of the probe is a free end, which is used to contact the surface to be tested on the wafer to be tested during testing; the probe comprises at least one probe for connecting to the GND PAD of the substrate, a power supply probe for connecting to the power supply PAD of the probe card substrate; wherein the power supply probe is divided into two groups; the first group comprises one probe, which is used to connect to the first group of power supply PADs on the substrate and connect to the sense terminal; the second group comprises the rest of the probes, which are used to connect to the second group of power supply PADs on the probe card substrate and connect to the force terminal; during testing, the free ends of all the probes on the probe card contact the surface to be tested of the wafer to be tested, wherein the power supply probe is connected to the power supply PAD of the wafer; and the PADs of the same power supply on one die of the wafer are connected in the internal structure of the wafer; at this time, the force and the sense of the tester are short-circuited at the wafer end via the power supply PAD of the substrate on the probe card, the probe and the power supply PAD of the wafer.

2. A wafer test system including a tester and a probe card for testing a wafer; the tester power supply DPS uses a Kelvin connection to divide the DPS into a force terminal and a sense terminal to provide a voltage; the force terminal is used to provide a stimulus and the sense terminal is used to feed back to the force terminal a line loss voltage drop resulting from the process of transmitting the stimulus to a device under test, the force terminal then adjusts the stimulus provided to compensate for the line loss voltage drop; characterized by, the probe card of claim 1, during testing, the free ends of all the probes on the probe card contact the surface to be tested of the wafer to be tested, wherein the power supply probe is connected to the power supply PAD of the wafer; and the PADs of the same power supply on one die of the wafer are connected in the internal structure of the wafer; at this time, the force and the sense of the tester are short-circuited at the wafer end via the power supply PAD of the substrate on the probe card, the probe and the power supply PAD of the wafer.

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