Method of adjusting gate height

Abstract

The application provides a method for adjusting the height of a gate electrode, and provides a semiconductor substrate, a plurality of pseudo gate structures are formed on the semiconductor substrate, the pseudo gate structure is composed of a stack and a sidewall located on the sidewall of the stack, and then an etching stop layer is formed on the pseudo gate structure, the stack is composed of a pseudo gate polysilicon layer, a pseudo gate surface oxide layer, a pseudo gate hard mask nitride layer and a pseudo gate hard mask oxide layer which are stacked from bottom to top in sequence; an interlayer dielectric layer covering the etching stop layer is formed on the semiconductor substrate, and then the interlayer dielectric layer is ground to above the etching stop layer; the interlayer dielectric layer is ground to above the pseudo gate hard mask nitride layer, and then the height of the remaining pseudo gate structure on different regions of the semiconductor substrate is obtained; and the pressure grinding is adjusted according to the height of the remaining pseudo gate structure on different regions of the semiconductor substrate, so that the height of each pseudo gate polysilicon layer tends to a preset value. The application can make the heights of the gate electrodes consistent, and reduce defects caused by the excessively high height of the gate electrode in some positions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a method for adjusting gate height. BACKGROUND

[0002] In the HKMG finfet (high-k metal gate fin field effect transistor) process, the control of gate height is very important. The formation of the gate is also relatively complex. Generally, after the pseudo-gate etching and epitaxy are completed, three CMP polishing is needed to form a flat pattern. The pseudo-gate is removed by dry etching and wet cleaning method. Then the high-k material and the work function metal layer are deposited to form the gate. In this process, if the height of the pseudo-gate is not controlled well, defects such as pseudo-gate residues and interlayer dielectric layer cavities will be formed, which will affect the product yield. The inconsistent gate height will also affect the capacitance-resistance performance of the device, thereby affecting the performance of the device.

[0003] In order to solve the above problems, a new method for adjusting the height of the gate is needed. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for adjusting the height of the gate, which solves the problem that in the prior art, the height of the pseudo-gate is not controlled well, resulting in defects such as pseudo-gate residues and interlayer dielectric layer cavities, which affect the product yield; the inconsistent gate height also affects the capacitance-resistance performance of the device, thereby affecting the performance of the device.

[0005] To achieve the above-mentioned purposes and other related purposes, the present application provides a method for adjusting the height of the gate, comprising:

[0006] Step one, providing a semiconductor substrate, a plurality of pseudo-gate structures are formed on the semiconductor substrate, the pseudo-gate structure is composed of a stack and a sidewall located on the sidewall of the stack, then an etching stop layer is formed on the pseudo-gate structure, the stack is composed of a pseudo-gate polysilicon layer, a pseudo-gate surface oxide layer, a pseudo-gate hard mask nitride layer and a pseudo-gate hard mask oxide layer stacked from bottom to top;

[0007] Step two, forming an interlayer dielectric layer on the semiconductor substrate, the interlayer dielectric layer covers the etching stop layer, then the interlayer dielectric layer is polished to above the etching stop layer;

[0008] Step three, polishing the interlayer dielectric layer and the sidewall, the etching stop layer, the pseudo-gate hard mask oxide layer below the interlayer dielectric layer to above the pseudo-gate hard mask nitride layer, then obtaining the height of the remaining pseudo-gate structure on different regions of the semiconductor substrate;

[0009] Step four, according to the height of the remaining pseudo-gate structure on different regions of the semiconductor substrate, adjust the pressure to grind the pseudo-gate hard mask nitride layer, the pseudo-gate surface oxide layer, the etching stop layer, the side wall, the interlayer dielectric layer to the pseudo-gate polysilicon layer, so that the height of each pseudo-gate polysilicon layer tends to a preset value.

[0010] Preferably, the semiconductor substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator substrate.

[0011] Preferably, the material of the pseudo-gate hard mask nitride layer in step one is silicon nitride.

[0012] Preferably, the material of the pseudo-gate hard mask oxide layer in step one is silicon dioxide.

[0013] Preferably, the material of the etching stop layer in step one is silicon nitride.

[0014] Preferably, the material of the interlayer dielectric layer in step two is silicon dioxide.

[0015] Preferably, the grinding method in steps two to four is chemical mechanical planarization grinding.

[0016] Preferably, the pseudo-gate structure is ground by a grinding pad in steps two to four, and the area of the grinding pad is smaller than the semiconductor substrate.

[0017] As described above, the method for adjusting the height of the gate electrode of the present application has the following beneficial effects:

[0018] The present application can better control the height of the gate electrode, so that the height of each gate electrode tends to be consistent, and reduce defects caused by the height of the gate electrode being too high in some positions. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 The process flow diagram of the present application is shown;

[0020] Figure 2 The semiconductor substrate and the pseudo-gate structure thereon of the present application are shown schematically;

[0021] Figure 3 The formation of the etching stop layer and the interlayer dielectric layer of the present application is shown schematically;

[0022] Figure 4 The first grinding of the present application is shown schematically;

[0023] Figure 5 The second grinding of the present application is shown schematically;

[0024] Figure 6 The third grinding of the present application is shown schematically. Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] Please see Figure 1 The present invention provides a method for adjusting the gate height, comprising:

[0027] Step 1: A semiconductor substrate 101 is provided, and multiple dummy gate structures 102 are formed on the semiconductor substrate 101. Each dummy gate structure 102 consists of a stack and sidewalls 1021 located on the sidewalls of the stack. The sidewalls 1021 are typically made of materials such as silicon oxide or silicon nitride. Then, an etch stop layer 104 is formed on the dummy gate structures. The stack consists of a dummy gate polysilicon layer 1022, a dummy gate surface oxide layer (not shown in the figure), a dummy gate hard mask nitride layer 1023, and a dummy gate hard mask oxide layer 1024 stacked sequentially from bottom to top, forming a structure as shown in the figure. Figure 2 The structure shown.

[0028] In embodiments of the present invention, the semiconductor substrate 101 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0029] In an embodiment of the present invention, the material of the pseudo-gate hard mask nitride layer 1023 in step one is silicon nitride.

[0030] In an embodiment of the present invention, the material of the pseudo-gate hard mask oxide layer 1024 in step one is silicon dioxide.

[0031] In an embodiment of the present invention, the material of the etching barrier layer in step one is silicon nitride.

[0032] In an embodiment of the present invention, in step one, a pseudo-gate polysilicon layer 1022, a pseudo-gate hard mask nitride layer 1023, and a pseudo-gate hard mask oxide layer 1024 are formed on a semiconductor substrate 101 in a stacked manner from bottom to top. Typically, a protective layer (not shown in the figure) made of, for example, silicon nitride is also included under the pseudo-gate polysilicon layer 1022. Then, a photoresist layer is formed on the pseudo-gate hard mask oxide layer 1024. After that, photolithography is used to open the photoresist layer to expose the pseudo-gate hard mask oxide layer 1024 below it. Then, the exposed pseudo-gate hard mask oxide layer 1024 and the pseudo-gate hard mask nitride layer 1023 and pseudo-gate polysilicon layer 1022 below it are etched to form a stack. Then, an etch protection layer 1021 is formed on the stack. Then, the etch protection layer 1021 except for the sidewalls of the stack is removed by a back etch method, thereby forming a pseudo-gate structure 102.

[0033] Step two, an interlayer dielectric layer 103 covering the etch barrier layer 104 is formed on the semiconductor substrate 101. The etch barrier layer 104 is typically formed by chemical vapor deposition, forming a layer such as... Figure 3 The structure shown is then polished up to the top of the interlayer dielectric layer 103 and the etch barrier layer 104, forming a structure as shown. Figure 4 The structure shown.

[0034] In an embodiment of the present invention, the material of the interlayer dielectric layer 103 in step two is silicon dioxide.

[0035] Step 3: Polish the interlayer dielectric layer 103 and the sidewalls 1021, etching barrier layer 104, dummy gate hard mask oxide layer 1024, and above the dummy gate hard mask nitride layer 1023 to form a layer as shown in the figure. Figure 5 The structure shown is then used to obtain the height of the remaining pseudo-gate structure 102 (i.e., the remaining pseudo-gate polysilicon layer 1022 and the pseudo-gate hard mask nitride layer 1023 on it) in different regions of the semiconductor substrate 101. The height of the remaining pseudo-gate structure 102 can usually be monitored in real time online using a local testing machine.

[0036] Step four: Based on the height of the remaining dummy gate structures 102 in different regions of the semiconductor substrate 101, adjust the pressure-milled dummy gate hard mask nitride layer 1023, dummy gate surface oxide layer, etch stop layer 104, interlayer dielectric layer 103, sidewall 1021 to dummy gate polysilicon layer 1022, so that the height of each dummy gate polysilicon layer 1022 tends to a preset value, forming a structure as shown in the figure. Figure 6 The structure shown automatically adjusts the grinding pressure during the grinding process by using the difference between the height of the remaining pseudo-gate structure 102 and the preset value, so that the height of the pseudo-gate polysilicon layer 1022 in each region tends to be close to the preset value.

[0037] Specifically, when the polishing pad polishes the remaining dummy gate structure 102 in a certain area of ​​the semiconductor substrate 101, if the height of the remaining dummy gate structure 102 (i.e., the remaining dummy gate polysilicon layer 1022 and the dummy gate hard mask nitride layer 1023 on it) is greater than a preset value, then the polishing pad increases the polishing pressure on the remaining dummy gate in that area of ​​the semiconductor substrate 101, and the increase is determined by the difference between the remaining dummy gate structure 102 and the preset value; when the polishing pad polishes the remaining dummy gate structure 102 in a certain area of ​​the semiconductor substrate 101, if the height of the remaining dummy gate structure 102 (i.e., the remaining dummy gate polysilicon layer 1022 and the dummy gate hard mask nitride layer 1023 on it) is less than a preset value, then the polishing pad decreases the polishing pressure on the remaining dummy gate in that area of ​​the semiconductor substrate 101, and the decrease is determined by the difference between the remaining dummy gate structure 102 and the preset value.

[0038] In the embodiments of the present invention, the grinding methods in steps two to four are all chemical mechanical planarization grinding.

[0039] In an embodiment of the present invention, the pseudo-gate structure 102 is polished using a polishing pad in steps two to four, and the area of ​​the polishing pad is smaller than that of the semiconductor substrate 101.

[0040] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0041] In summary, this invention provides better control over gate height, ensuring greater uniformity across all gates and reducing defects caused by excessively high gate heights in certain locations. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses significant industrial applicability.

[0042] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for adjusting the gate height, characterized in that, At least including: Step 1: Provide a semiconductor substrate, and form multiple dummy gate structures on the semiconductor substrate. The dummy gate structure consists of a stack and sidewalls located on the sidewalls of the stack. Then, form an etch barrier layer on the dummy gate structure. The stack consists of a dummy gate polysilicon layer, a dummy gate surface oxide layer, a dummy gate hard mask nitride layer, and a dummy gate hard mask oxide layer stacked sequentially from bottom to top. Step 2: Form an interlayer dielectric layer covering the etch barrier layer on the semiconductor substrate, and then grind the interlayer dielectric layer up to the etch barrier layer; Step 3: Grind the interlayer dielectric layer and the sidewalls, etch stop layer, and dummy gate hard mask oxide layer below it up to the top of the dummy gate hard mask nitride layer, and then obtain the height of the remaining dummy gate structure in different regions of the semiconductor substrate; Step 4: According to the height of the remaining dummy gate structure in different regions of the semiconductor substrate, adjust the pressure to grind the dummy gate hard mask nitride layer, the dummy gate surface oxide layer, the etch stop layer, the sidewalls, the interlayer dielectric layer up to the dummy gate polysilicon layer, so that the height of each dummy gate polysilicon layer tends to a preset value; In steps two through four, the pseudo-gate structure is polished using a polishing pad, the area of ​​which is smaller than that of the semiconductor substrate.

2. The method for adjusting the gate height according to claim 1, characterized in that: The semiconductor substrate in step one includes a bulk semiconductor substrate or a silicon-on-insulator substrate.

3. The method for adjusting the gate height according to claim 1, characterized in that: The material of the pseudo-gate hard mask nitride layer in step one is silicon nitride.

4. The method for adjusting the gate height according to claim 1, characterized in that: The material of the pseudo-gate hard mask oxide layer in step one is silicon dioxide.

5. The method for adjusting the gate height according to claim 1, characterized in that: The material of the etching barrier layer in step one is silicon nitride.

6. The method for adjusting the gate height according to claim 1, characterized in that: The material of the interlayer dielectric layer in step two is silicon dioxide.

7. The method for adjusting the gate height according to claim 1, characterized in that: The grinding methods described in steps two through four are all chemical mechanical planarization grinding.

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