A charge pump with a wide matching range applied to a phase-locked loop system

Abstract

The present invention claims protection for a charge pump with a wide matching range applied to a phase-locked loop system, belonging to the field of microelectronics technology, including a charging current compensation circuit, a charge pump core circuit, and a discharging current compensation circuit. The present invention uses MOS transistors M13 to M15 and amplifier OP2 to form a charging current I in the low voltage region UP compensation circuit to improve the I in the low voltage region UP matching range, uses amplifier OP5, PMOS transistor M19, and transmission gate T1 to form a compensation circuit for I in the high voltage region UP to improve the I in the high voltage region UP matching range, uses MOS transistors M16 to M18 and amplifier OP3 to form a discharging current I compensation circuit in the high voltage region DN to improve the I in the high voltage region DN matching range, uses amplifier OP4, NMOS transistor M20, and transmission gate T6 to form a compensation circuit for I in the low voltage region DN to improve the I in the low voltage region DN matching range, thereby improving the charge / discharge current matching range and realizing a charge pump with a wide matching range.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and particularly relates to a charge pump with a wide matching range applied to a phase-locked loop system. Background Art

[0002] As an important form of clock generation circuit, the phase-locked loop is widely used in integrated circuits. The charge pump type phase-locked loop has characteristics such as high speed and low jitter, and is a commonly used phase-locked loop structure at present. The charge pump, as an important part of the charge pump type phase-locked loop, its performance directly affects the performance of the phase-locked loop, and further affects the performance characteristics of the clock generation circuit.

[0003] Figure 1 A traditional charge pump circuit mainly consists of a charging current source Iup, a charging switch S1, a discharging switch S2, and a discharging current source Idn. When the switch S1 is closed and the switch S2 is open, the charging current source Iup charges the subsequent filter capacitor through the charging switch S1; when the switch S1 is open and the switch S2 is closed, the subsequent filter capacitor discharges through the switch S2 and the discharging current source Idn. When both the switch S1 and the switch S2 are open, the voltage on the subsequent filter capacitor remains unchanged. Anyway, the traditional charge pump circuit has problems such as current mismatch and leakage current when turned off, which directly affect the performance characteristics of the phase-locked loop. Summary of the Invention

[0004] The present invention aims to solve the above problems of the prior art. A charge pump with a wide matching range applied to a phase-locked loop system is proposed. The technical solution of the present invention is as follows:

[0005] A charge pump with a wide matching range applied to a phase-locked loop system, which includes: a charging current compensation circuit (1), a charge pump core circuit (2), and a discharging current compensation circuit (3). Among them, the signal output end of the charging current compensation circuit (1) is connected to the signal input end of the charge pump core circuit (2), the signal output end of the charge pump core circuit (2) is respectively connected to the signal input end of the charging current compensation circuit (1) and the signal input end of the discharging current compensation circuit (3), the signal output end of the discharging current compensation circuit (3) is connected to the signal input end of the charge pump core circuit (2), the charging current compensation circuit (1) provides a charging compensation current for the charge pump core circuit (2), the discharging current compensation circuit (3) provides a discharging compensation current for the charge pump core circuit (2), and the charge pump core circuit (2) provides charging and discharging currents for the filter circuit of the phase-locked loop system.

[0006] Further, the charging current compensation circuit (1) includes: PMOS transistor M13, PMOS transistor M14, NMOS transistor M15, PMOS transistor M19, amplifier OP2, amplifier OP5, and transmission gate T1. The source of PMOS transistor M14 is connected to the source of PMOS transistor M13 and the external power supply VDD respectively. The gate of PMOS transistor M14 is connected to the gate of PMOS transistor M13, the drain of PMOS transistor M14, and the drain of NMOS transistor M15 respectively. The source of NMOS transistor M15 is connected to the output terminal and the inverting input terminal of amplifier OP2 respectively. The inverting input terminal of amplifier OP5 is connected to the output terminal of amplifier OP5 and the source of PMOS transistor M19 respectively. The drain of PMOS transistor M19 is connected to the input terminal of transmission gate T1. One control terminal of transmission gate T1 is connected to the signal control terminal UP, and the other control terminal of transmission gate T1 is connected to the signal control terminal connected.

[0007] Further, the charge pump core circuit (2) includes: current sources IR1 and IR2, NMOS transistors M1, M2, PMOS transistors M3, M4, M5, M6, NMOS transistors M7, M8, M9, M10, PMOS transistors M11, M12, transmission gates T2, T3, T4, T5, and amplifier OP1. One end of current source IR1 is connected to the sources of PMOS transistors M4, M5, M11, and M12 and the external power supply VDD respectively. The other end of power supply IR1 is connected to the drain, gate of NMOS transistor M1, and the gate of NMOS transistor M2 respectively. The drain of PMOS transistor M4 is connected to the source of PMOS transistor M3. The drain of PMOS transistor M3 is connected to the gates of PMOS transistors M4, M5, M13, and the drain of NMOS transistor M2 respectively. The gate of PMOS transistor M3 is connected to the gates of PMOS transistors M6, M19, M16, and the bias terminal VB1 respectively. The drain of PMOS transistor M5 is connected to the source of PMOS transistor M6. The drain of PMOS transistor M6 is connected to the non-inverting input terminal of amplifier OP5, the input terminal of transmission gate T2, and the input terminal of transmission gate T4 respectively. One control terminal of transmission gate T2 is connected to the signal control terminal DN, and the other control terminal of transmission gate T2 is connected to the signal control terminal connected. The output terminal of transmission gate T2 is connected to the output terminal of amplifier OP1, the inverting input terminal of amplifier OP1, and the input terminal of transmission gate T3 respectively. One control terminal of transmission gate T3 is connected to the signal control terminal UP, and the other control terminal of transmission gate T3 is connected to the signal control terminal is connected, one control terminal of transmission gate T4 is connected to signal control terminal UP, and the other control terminal of transmission gate T4 is connected to signal control terminal is connected. The output terminal of transmission gate T4 is respectively connected to the output terminal of transmission gate T1, the non-inverting input terminal of amplifier OP2, the non-inverting input terminal of amplifier OP1, the input terminal of transmission gate T5, the non-inverting input terminal of amplifier OP3, the input terminal of transmission gate T6, and charge pump output terminal VC. One control terminal of transmission gate T5 is connected to signal control terminal DN, and the other control terminal of transmission gate T5 is connected to signal control is connected. The output terminal of transmission gate T5 is respectively connected to the output terminal of transmission gate T3, the non-inverting input terminal of amplifier OP4, and the drain of NMOS transistor M7. The gate of NMOS transistor M7 is respectively connected to the gates of NMOS transistors M9, M20, M15, and bias terminal VB2. The source of NMOS transistor M7 is connected to the drain of NMOS transistor M8. The gate of NMOS transistor M8 is respectively connected to the gates of NMOS transistors M10, the drain of NMOS transistor M9, the drain of NMOS transistor M18, and the drain of PMOS transistor M11. The source of NMOS transistor M9 is connected to the drain of NMOS transistor M10. The gate of PMOS transistor M12 is respectively connected to the gates of PMOS transistors M11, the drain of PMOS transistor M12, and one end of current source IR2. The other end of current source IR2 is respectively connected to the sources of NMOS transistors M1, M2, M8, M10, and external ground wire GND.

[0008] Furthermore, the discharge current compensation circuit (3) includes: PMOS transistor M16, NMOS transistors M17, M18, M20, amplifier OP3, amplifier OP4, and transmission gate T6. The inverting input terminal of amplifier OP3 is respectively connected to the output terminal of amplifier OP3 and the source of PMOS transistor M16. The drain of PMOS transistor M16 is respectively connected to the drains of NMOS transistors M17, the gate of NMOS transistor M17, and the gate of NMOS transistor M18. The source of NMOS transistor M17 is respectively connected to the source of NMOS transistor M18 and external ground wire GND. One control terminal of transmission gate T6 is connected to signal control terminal DN, and the other control terminal of transmission gate T6 is connected to signal control terminal is connected. The output terminal of transmission gate T6 is connected to the drain of NMOS transistor M20. The source of NMOS transistor M20 is respectively connected to the output terminal of amplifier OP4 and the inverting input terminal of amplifier OP4.

[0009] Further, in the charging current compensation circuit (1), the PMOS transistor M13, the PMOS transistor M14, the NMOS transistor M15, and the amplifier OP2 constitute a compensation circuit for the charging current in the low voltage region, improving the matching range of the charging current in the low voltage region. The amplifier OP2 constitutes a unity gain negative feedback such that the source voltage of the NMOS transistor M15 is equal to the voltage V of the charge pump output terminal VC C , when the voltage V of the charge pump output terminal VC C is relatively low, the NMOS transistor M15 is turned on and its drain current where μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L) 15 is the channel width-to-length ratio of the NMOS transistor M15, V B2 is the voltage of the bias terminal VB2, V THn is the threshold voltage of the NMOS transistor. The PMOS transistor M13 and the PMOS transistor M14 are exactly the same. The drain current I 13 of the PMOS transistor M13 and the drain current I 14 of the PMOS transistor M14 have I 13 = I 14 = I 15 .

[0010] Further, in the charging current compensation circuit (1), the amplifier OP5, the PMOS transistor M19, and the transmission gate T1 constitute a compensation circuit for the charging current in the high voltage region, improving the matching range of the charging current in the high voltage region. When the voltage V of the charge pump output terminal VC C rises, the drain voltage V A of the PMOS transistor M6 in the charge pump core circuit (2) also rises. The amplifier OP5 constitutes a unity gain negative feedback such that the source voltage of the PMOS transistor M19 is equal to V A . When V A - V B1 >|V THP |, the PMOS transistor M19 is turned on, where V B1 is the voltage of the bias terminal VB1, V THP is the threshold voltage of the PMOS transistor. Then the drain current of the PMOS transistor M19 where μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, (W / L) 19 is the channel width-to-length ratio of the PMOS transistor M19

[0011] Further, in the charge pump core circuit (2), the currents flowing through the current source IR1 and the current source IR2 are the same and are both equal to I REF, the NMOS transistor M1 is identical to the NMOS transistor M2, the PMOS transistor M4 is identical to the PMOS transistor M5, and the PMOS transistor M3 is identical to the PMOS transistor M6. Then, the drain current I6 of the PMOS transistor M6 = I REF -I 15 , where I 15 is the drain current of the NMOS transistor M15; the PMOS transistor M11 is identical to the PMOS transistor M12, the NMOS transistor M8 is identical to the NMOS transistor M10, and the NMOS transistor M7 is identical to the NMOS transistor M9. Then, the drain current I7 of the NMOS transistor M7 = I REF -I 16 , where I 16 is the drain current of the PMOS transistor M16. The signal control terminal DN and the signal control terminal UP have opposite signals, the signal control terminal DN and the signal control terminal have opposite signals, and the signal control terminal UP and the signal control terminal have opposite signals. When the signal control terminal UP is at a high potential and the signal control terminal DN is at a low potential, the transmission gate T4 is turned on and the transmission gate T5 is turned off. The charge pump charging current I UP charges the filter circuit of the phase-locked loop system (and I UP = I6 + I 19 ), and the voltage V C at the output terminal VC of the charge pump gradually rises. Where I 19 is the drain current of the PMOS transistor M19. When the voltage V C is at a low voltage, the PMOS transistor M19 is cut off and the NMOS transistor M15 is turned on. The current I 15 of the NMOS transistor M15 compensates the charging current I UP to broaden the matching range in the low voltage region; when the voltage V C is at a high voltage, the NMOS transistor M15 is cut off and the PMOS transistor M19 is turned on. The current I 19 of the PMOS transistor M19 compensates the charging current I UP to broaden the matching range in the high voltage region.

[0012] Further, in the charge pump core circuit (2), when the signal control terminal UP is at a low potential and the signal control terminal DN is at a high potential, the charge pump discharge current I DN discharges the filter circuit of the phase-locked loop system, and I DN = I7 + I 20 , where I7 is the drain current of the NMOS transistor M7 and I 20 is the drain current of the NMOS transistor M20. The voltage V C at the output terminal VC of the charge pump gradually decreases. When the voltage V CWhen it is at a high potential, PMOS transistor M16 is turned on and NMOS transistor M20 is turned off. The current I of PMOS transistor M16 16 compensates for the discharge current I DN to broaden the matching range in the high-voltage region; when the voltage V C is at a low potential, PMOS transistor M16 is turned off and NMOS transistor M20 is turned on. The current I of NMOS transistor M20 20 compensates for the discharge current I DN to broaden the matching range in the low-voltage region.

[0013] Furthermore, in the discharge current compensation circuit (3), PMOS transistor M16, NMOS transistors M17 and M18, and amplifier OP3 form a compensation circuit for the discharge current in the high-voltage region, improving the matching range of the discharge current in the high-voltage region. Amplifier OP3 forms a unity-gain negative feedback, making the source voltage of PMOS transistor M16 equal to the voltage V of the output terminal VC of the charge pump C . When the voltage V of the output terminal VC of the charge pump C is relatively high, PMOS transistor M16 is turned on and its drain current where μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, (W / L) 16 is the channel width-to-length ratio of PMOS transistor M16, V B1 is the voltage of bias terminal VB1, V THP is the threshold voltage of the PMOS transistor. NMOS transistor M18 is identical to NMOS transistor M17, so the drain current I 18 of NMOS transistor M18 and the drain current I 17 of NMOS transistor M17 have I 18 =I 17 =I 16 .

[0014] Furthermore, in the discharge current compensation circuit (3), amplifier OP4, NMOS transistor M20, and transmission gate T6 form a compensation circuit for the discharge current in the low-voltage region, improving the matching range of the discharge current in the low-voltage region. When the voltage V of the output terminal VC of the charge pump C decreases, the drain voltage V B of NMOS transistor M7 in the charge pump core circuit (2) also decreases. Amplifier OP4 forms a unity-gain negative feedback, making the source voltage of NMOS transistor M20 equal to V B . When V B2 -V B >V THn , NMOS transistor M20 is turned on, and then the drain current of NMOS transistor M20 where μn is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L) 20 is the channel width-to-length ratio of NMOS transistor M20, V B2 is the voltage of bias terminal VB2, V THn is the threshold voltage of the NMOS transistor.

[0015] The advantages and beneficial effects of the present invention are as follows:

[0016] The present invention provides a charge pump with a wide matching range applied to a phase-locked loop system. A compensation circuit for the charging current in the low-voltage region is formed by PMOS transistor M13, PMOS transistor M14, NMOS transistor M15, and amplifier OP2 to improve the matching range of the charging current in the low-voltage region. A compensation circuit for the charging current in the high-voltage region is formed by amplifier OP5, PMOS transistor M19, and transmission gate T1 to improve the matching range of the charging current in the high-voltage region. A compensation circuit for the discharging current in the high-voltage region is formed by PMOS transistor M16, NMOS transistor M17, NMOS transistor M18, and amplifier OP3 to improve the matching range of the discharging current in the high-voltage region. A compensation circuit for the discharging current in the low-voltage region is formed by amplifier OP4, NMOS transistor M20, and transmission gate T6 to improve the matching range of the discharging current in the low-voltage region. Furthermore, the matching range of the charging current and the discharging current of the charge pump is improved, thereby realizing a charge pump with a wide matching range. Description of the Drawings

[0017] Figure 1 is the schematic diagram of a traditional charge pump circuit;

[0018] Figure 2 is the schematic diagram of a charge pump with a wide matching range applied to a phase-locked loop system according to a preferred embodiment provided by the present invention;

[0019] Figure 3 is the simulation diagram of the matching characteristics of a charge pump with a wide matching range applied to a phase-locked loop system according to a preferred embodiment provided by the present invention. Detailed Embodiments

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and detailedly described in conjunction with the drawings in the embodiments of the present invention. The described embodiments are only a part of the embodiments of the present invention.

[0021] The technical solution for the present invention to solve the above technical problems is:

[0022] The embodiment of the present application uses PMOS transistor M13, PMOS transistor M14, NMOS transistor M15, and amplifier OP2 to form a compensation circuit for the charging current in the low-voltage region, improving the matching range of the charging current in the low-voltage region. It uses amplifier OP5, PMOS transistor M19, and transmission gate T1 to form a compensation circuit for the charging current in the high-voltage region, improving the matching range of the charging current in the high-voltage region. It uses PMOS transistor M16, NMOS transistor M17, NMOS transistor M18, and amplifier OP3 to form a compensation circuit for the discharging current in the high-voltage region, improving the matching range of the discharging current in the high-voltage region. It uses amplifier OP4, NMOS transistor M20, and transmission gate T6 to form a compensation circuit for the discharging current in the low-voltage region, improving the matching range of the discharging current in the low-voltage region. Furthermore, the matching range of the charging current and the discharging current of the charge pump is improved, thereby realizing a charge pump with a wide matching range.

[0023] To better understand the above technical solution, the following will combine the accompanying drawings of the specification and specific implementation manners to elaborate on the above technical solution in detail.

[0024] Embodiment

[0025] A charge pump with a wide matching range applied to a phase-locked loop system, as Figure 2 shown, includes a charging current compensation circuit 1, a charge pump core circuit 2, and a discharging current compensation circuit 3;

[0026] Among them, the signal output terminal of the charging current compensation circuit 1 is connected to the signal input terminal of the charge pump core circuit 2. The signal output terminal of the charge pump core circuit 2 is respectively connected to the signal input terminal of the charging current compensation circuit 1 and the signal input terminal of the discharging current compensation circuit 3. The signal output terminal of the discharging current compensation circuit 3 is connected to the signal input terminal of the charge pump core circuit 2. The charging current compensation circuit 1 provides a charging compensation current for the charge pump core circuit 2. The discharging current compensation circuit 3 provides a discharging compensation current for the charge pump core circuit 2. The charge pump core circuit 2 provides charging and discharging currents for the filter circuit of the phase-locked loop system.

[0027] As a preferred technical solution, as Figure 2As shown, the charging current compensation circuit 1 includes: PMOS transistor M13, PMOS transistor M14, NMOS transistor M15, PMOS transistor M19, amplifier OP2, amplifier OP5, and transmission gate T1. The source of PMOS transistor M14 is connected to the source of PMOS transistor M13 and the external power supply VDD respectively. The gate of PMOS transistor M14 is connected to the gate of PMOS transistor M13, the drain of PMOS transistor M14, and the drain of NMOS transistor M15 respectively. The source of NMOS transistor M15 is connected to the output terminal and the inverting input terminal of amplifier OP2 respectively. The inverting input terminal of amplifier OP5 is connected to the output terminal of amplifier OP5 and the source of PMOS transistor M19 respectively. The drain of PMOS transistor M19 is connected to the input terminal of transmission gate T1. One control terminal of transmission gate T1 is connected to the signal control terminal UP, and the other control terminal of transmission gate T1 is connected to the signal control terminal UP.

[0028] The charge pump core circuit 2 includes: current source IR1, current source IR2, NMOS transistor M1, NMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M5, PMOS transistor M6, NMOS transistor M7, NMOS transistor M8, NMOS transistor M9, NMOS transistor M10, PMOS transistor M11, PMOS transistor M12, transmission gate T2, transmission gate T3, transmission gate T4, transmission gate T5, and amplifier OP1. One end of current source IR1 is connected to the source of PMOS transistor M4, the source of PMOS transistor M5, the source of PMOS transistor M11, the source of PMOS transistor M12, and the external power supply VDD respectively. The other end of power supply IR1 is connected to the drain of NMOS transistor M1, the gate of NMOS transistor M1, and the gate of NMOS transistor M2 respectively. The drain of PMOS transistor M4 is connected to the source of PMOS transistor M3. The drain of PMOS transistor M3 is connected to the gate of PMOS transistor M4, the gate of PMOS transistor M5, the drain of PMOS transistor M13, and the drain of NMOS transistor M2 respectively. The gate of PMOS transistor M3 is connected to the gate of PMOS transistor M6, the gate of PMOS transistor M19, the gate of PMOS transistor M16, and the bias terminal VB1 respectively. The drain of PMOS transistor M5 is connected to the source of PMOS transistor M6. The drain of PMOS transistor M6 is connected to the non-inverting input terminal of amplifier OP5, the input terminal of transmission gate T2, and the input terminal of transmission gate T4 respectively. One control terminal of transmission gate T2 is connected to the signal control terminal DN, and the other control terminal of transmission gate T2 is connected to the signal control terminal connected. The output terminal of transmission gate T2 is connected to the output terminal of amplifier OP1, the inverting input terminal of amplifier OP1, and the input terminal of transmission gate T3 respectively. One control terminal of transmission gate T3 is connected to the signal control terminal UP, and the other control terminal of transmission gate T3 is connected to the signal control terminal is connected, one control terminal of transmission gate T4 is connected to signal control terminal UP, and the other control terminal of transmission gate T4 is connected to signal control terminal is connected. The output terminal of transmission gate T4 is respectively connected to the output terminal of transmission gate T1, the non-inverting input terminal of amplifier OP2, the non-inverting input terminal of amplifier OP1, the input terminal of transmission gate T5, the non-inverting input terminal of amplifier OP3, the input terminal of transmission gate T6, and charge pump output terminal VC. One control terminal of transmission gate T5 is connected to signal control terminal DN, and the other control terminal of transmission gate T5 is connected to signal control is connected. The output terminal of transmission gate T5 is respectively connected to the output terminal of transmission gate T3, the non-inverting input terminal of amplifier OP4, and the drain of NMOS transistor M7. The gate of NMOS transistor M7 is respectively connected to the gates of NMOS transistors M9, M20, M15, and bias terminal VB2. The source of NMOS transistor M7 is connected to the drain of NMOS transistor M8. The gate of NMOS transistor M8 is respectively connected to the gates of NMOS transistors M10, the drain of NMOS transistor M9, the drain of NMOS transistor M18, and the drain of PMOS transistor M11. The source of NMOS transistor M9 is connected to the drain of NMOS transistor M10. The gate of PMOS transistor M12 is respectively connected to the gates of PMOS transistors M11, the drain of PMOS transistor M12, and one end of current source IR2. The other end of current source IR2 is respectively connected to the sources of NMOS transistors M1, M2, M8, M10, and external ground wire GND.

[0029] The discharge current compensation circuit 3 includes: PMOS transistor M16, NMOS transistors M17, M18, M20, amplifier OP3, amplifier OP4, and transmission gate T6. The inverting input terminal of amplifier OP3 is respectively connected to the output terminal of amplifier OP3 and the source of PMOS transistor M16. The drain of PMOS transistor M16 is respectively connected to the drains, gates of NMOS transistors M17, M18. The source of NMOS transistor M17 is respectively connected to the sources of NMOS transistors M18 and external ground wire GND. One control terminal of transmission gate T6 is connected to signal control terminal DN, and the other control terminal of transmission gate T6 is connected to signal control terminal is connected. The output terminal of transmission gate T6 is connected to the drain of NMOS transistor M20. The source of NMOS transistor M20 is respectively connected to the output terminal and the inverting input terminal of amplifier OP4.

[0030] In the charging current compensation circuit 1, the PMOS transistor M13, the PMOS transistor M14, the NMOS transistor M15, and the amplifier OP2 form a compensation circuit for the charging current in the low voltage region, improving the matching range of the charging current in the low voltage region. The amplifier OP2 forms a unity gain negative feedback such that the source voltage of the NMOS transistor M15 is equal to the voltage of the charge pump output terminal VC. When the voltage V C of the charge pump output terminal VC is relatively low, the NMOS transistor M15 is turned on and its drain current I 15 is

[0031]

[0032] In the formula, μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L) 15 is the channel width-to-length ratio of the NMOS transistor M15, V B2 is the voltage of the bias terminal VB2, V THn is the threshold voltage of the NMOS transistor. The PMOS transistor M13 and the PMOS transistor M14 are exactly the same. The drain current I 13 of the PMOS transistor M13 and the drain current I 14 of the PMOS transistor M14 have I 13 = I 14 = I 15 . The amplifier OP5, the PMOS transistor M19, and the transmission gate T1 form a compensation circuit for the charging current in the high voltage region, improving the matching range of the charging current in the high voltage region. When the voltage V C of the charge pump output terminal VC rises, the drain voltage V A of the PMOS transistor M6 in the charge pump core circuit 2 also rises. The amplifier OP5 forms a unity gain negative feedback such that the source voltage of the PMOS transistor M19 is equal to V A . When V A - V B1 >|V THP |, the PMOS transistor M19 is turned on, where V B1 is the voltage of the bias terminal VB1, V THP is the threshold voltage of the PMOS transistor. Then the drain current I 19 of the PMOS transistor M19 is

[0033]

[0034] In the formula, μ p is the hole mobility, (W / L) 19 is the channel width-to-length ratio of the PMOS transistor M19.

[0035] In the discharge current compensation circuit 3, the PMOS transistor M16, NMOS transistors M17 and M18, and the amplifier OP3 form a compensation circuit for the discharge current in the high-voltage region, improving the matching range of the discharge current in the high-voltage region. The amplifier OP3 forms a unity-gain negative feedback, making the source voltage of the PMOS transistor M16 equal to the voltage V of the output terminal VC of the charge pump. C When the voltage V of the output terminal VC of the charge pump C is relatively high, the PMOS transistor M16 is turned on and its drain current I 16 is

[0036]

[0037] In the formula, (W / L) 16 is the channel width-to-length ratio of the PMOS transistor M16. The NMOS transistor M18 is identical to the NMOS transistor M17, so the drain current I 18 of the NMOS transistor M18 and the drain current I 17 of the NMOS transistor M17 have 18 I 17 = I 16 . The amplifier OP4, the NMOS transistor M20, and the transmission gate T6 form a compensation circuit for the discharge current in the low-voltage region, improving the matching range of the discharge current in the low-voltage region. When the voltage V of the output terminal VC of the charge pump C decreases, the drain voltage V B of the NMOS transistor M7 in the charge pump core circuit 2 also decreases. The amplifier OP4 forms a unity-gain negative feedback, making the source voltage of the NMOS transistor M20 equal to V B . When V B2 - V B > V THn , the NMOS transistor M20 is turned on, and the drain current I 20 of the NMOS transistor M20 is

[0038]

[0039] In the formula, (W / L) 20 is the channel width-to-length ratio of the NMOS transistor M20.

[0040] In the charge pump core circuit 2, the current I R1 of the current source IR1 and the current I R2 of the current source IR2 have R1 I R2 = I REF, PMOS transistor M13 is identical to PMOS transistor M14, NMOS transistor M1 is identical to NMOS transistor M2, PMOS transistor M4 is identical to PMOS transistor M5, PMOS transistor M3 is identical to PMOS transistor M6, then the drain current I6 of PMOS transistor M6 = I REF -I 15 , PMOS transistor M11 is identical to PMOS transistor M12, NMOS transistor M8 is identical to NMOS transistor M10, NMOS transistor M7 is identical to NMOS transistor M9, then the drain current I7 of NMOS transistor M7 = I REF -I 16 , the signal control terminal DN and the signal control terminal UP have opposite signals, the signal control terminal DN and the signal control terminal have opposite signals, the signal control terminal UP and the signal control terminal have opposite signals. When the signal control terminal UP is at a high potential and the signal control terminal DN is at a low potential, the transmission gate T4 is turned on and the transmission gate T5 is turned off, and the charge pump charging current I UP charges the filter circuit of the phase-locked loop system, and I UP = I6 + I 19 , the voltage V C at the output terminal VC of the charge pump gradually rises. When the voltage V C is at a low voltage, PMOS transistor M19 is cut off and NMOS transistor M15 is turned on. The current I 15 of NMOS transistor M15 compensates for the charging current I UP to widen the matching range in the low voltage region; when the voltage V C is at a high voltage, NMOS transistor M15 is cut off and PMOS transistor M19 is turned on. The current I 19 of PMOS transistor M19 compensates for the charging current I UP to widen the matching range in the high voltage region. When the signal control terminal UP is at a low potential and the signal control terminal DN is at a high potential, the charge pump discharging current I DN discharges the filter circuit of the phase-locked loop system, and I DN = I7 + I 20 , the voltage V C at the output terminal VC of the charge pump gradually decreases. When the voltage V C is at a high potential, PMOS transistor M16 is turned on and NMOS transistor M20 is cut off. The current I 16 of PMOS transistor M16 compensates for the discharging current I DN to widen the matching range in the high voltage region; when the voltage V C is at a low potential, PMOS transistor M16 is cut off and NMOS transistor M20 is turned on. The current I 20 of NMOS transistor M20 compensates for the discharging current IDN Compensation is performed to broaden the matching range in the low-voltage region.

[0041] Figure 3 This is the simulation curve of the matching characteristics of a wide-matching-range charge pump applied to a phase-locked loop system according to the present invention. The abscissa is the output voltage V of the charge pump C , and the ordinate is the charge / discharge current of the charge pump. The power supply voltage is 1.8V, and the voltage V C In the range of 0.1 - 1.7V, the error between the charging current I UP and the discharging current is less than 1%.

[0042] In the above embodiments of the present application, a wide-matching-range charge pump applied to a phase-locked loop system includes a charging current compensation circuit, a charge pump core circuit, and a discharging current compensation circuit. In the embodiments of the present application, PMOS transistor M13, PMOS transistor M14, NMOS transistor M15, and amplifier OP2 are used to form a compensation circuit for the charging current in the low-voltage region to improve the matching range of the charging current in the low-voltage region. Amplifier OP5, PMOS transistor M19, and transmission gate T1 are used to form a compensation circuit for the charging current in the high-voltage region to improve the matching range of the charging current in the high-voltage region. PMOS transistor M16, NMOS transistor M17, NMOS transistor M18, and amplifier OP3 are used to form a compensation circuit for the discharging current in the high-voltage region to improve the matching range of the discharging current in the high-voltage region. Amplifier OP4, NMOS transistor M20, and transmission gate T6 are used to form a compensation circuit for the discharging current in the low-voltage region to improve the matching range of the discharging current in the low-voltage region. Furthermore, the matching range between the charging current and the discharging current of the charge pump is improved, thereby realizing a wide-matching-range charge pump.

[0043] It should also be noted that the term "including", "comprising", or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity, or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, commodity, or device. Without further limitations, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, commodity, or device including the said element.

[0044] The above embodiments should be understood as being only for illustrative purposes of the present invention and not for limiting the protection scope of the present invention. After reading the content recorded in the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A charge pump with a wide matching range for a phase-locked loop system, characterized in that, Including: A charging current compensation circuit (1), a charge pump core circuit (2), and a discharging current compensation circuit (3). Among them, the signal output terminal of the charging current compensation circuit (1) is connected to the signal input terminal of the charge pump core circuit (2), the signal output terminal of the charge pump core circuit (2) is respectively connected to the signal input terminal of the charging current compensation circuit (1) and the signal input terminal of the discharging current compensation circuit (3), the signal output terminal of the discharging current compensation circuit (3) is connected to the signal input terminal of the charge pump core circuit (2), the charging current compensation circuit (1) provides a charging compensation current for the charge pump core circuit (2) through a PMOS transistor M13 and a transmission gate T1, the discharging current compensation circuit (3) provides a discharging compensation current for the charge pump core circuit (2) through components including a transmission gate T6 and an NMOS transistor M18, and the charge pump core circuit (2) provides a charge and discharge current for the filter circuit of the phase-locked loop system through a transmission gate T4, a transmission gate T5, and a circuit output terminal VC; The charging current compensation circuit (1) includes: PMOS transistor M13, PMOS transistor M14, NMOS transistor M15, PMOS transistor M19, amplifier OP2, amplifier OP5, and transmission gate T1. The source of PMOS transistor M14 is connected to the source of PMOS transistor M13 and the external power supply VDD respectively. The gate of PMOS transistor M14 is connected to the gate of PMOS transistor M13, the drain of PMOS transistor M14, and the drain of NMOS transistor M15 respectively. The source of NMOS transistor M15 is connected to the output terminal and the inverting input terminal of amplifier OP2 respectively. The inverting input terminal of amplifier OP5 is connected to the output terminal of amplifier OP5 and the source of PMOS transistor M19 respectively. The drain of PMOS transistor M19 is connected to the input terminal of transmission gate T1. One control terminal of transmission gate T1 is connected to the signal control terminal UP, and the other control terminal of transmission gate T1 is connected to the signal control terminal is connected.

2. The wide matching range charge pump applied to a phase-locked loop system according to claim 1, wherein The charge pump core circuit (2) includes: current sources IR1 and IR2, NMOS transistors M1, M2, PMOS transistors M3, M4, M5, M6, NMOS transistors M7, M8, M9, M10, PMOS transistors M11, M12, transmission gates T2, T3, T4, T5, and amplifier OP1. One end of current source IR1 is connected to the source electrodes of PMOS transistors M4, M5, M11, and M12, and to the external power supply VDD. The other end of power supply IR1 is connected to the drain electrode, gate electrode of NMOS transistor M1, and the gate electrode of NMOS transistor M2. The drain electrode of PMOS transistor M4 is connected to the source electrode of PMOS transistor M3. The drain electrode of PMOS transistor M3 is connected to the gate electrodes of PMOS transistors M4, M5, the drain electrode of PMOS transistor M13, and the drain electrode of NMOS transistor M2. The gate electrode of PMOS transistor M3 is connected to the gate electrodes of PMOS transistors M6, M19, M16, and bias terminal VB1. The drain electrode of PMOS transistor M5 is connected to the source electrode of PMOS transistor M6. The drain electrode of PMOS transistor M6 is connected to the non-inverting input terminal of amplifier OP5, the input terminal of transmission gate T2, and the input terminal of transmission gate T4. One control terminal of transmission gate T2 is connected to signal control terminal DN, and the other control terminal of transmission gate T2 is connected to signal control terminal connected. The output terminal of transmission gate T2 is connected to the output terminal of amplifier OP1, the inverting input terminal of amplifier OP1, and the input terminal of transmission gate T3. One control terminal of transmission gate T3 is connected to signal control terminal UP, and the other control terminal of transmission gate T3 is connected to signal control terminal connected. One control terminal of transmission gate T4 is connected to signal control terminal UP, and the other control terminal of transmission gate T4 is connected to signal control terminal connected. The output terminal of transmission gate T4 is connected to the output terminal of transmission gate T1, the non-inverting input terminal of amplifier OP2, the non-inverting input terminal of amplifier OP1, the input terminal of transmission gate T5, the non-inverting input terminal of amplifier OP3, the input terminal of transmission gate T6, and the charge pump output terminal VC. One control terminal of transmission gate T5 is connected to signal control terminal DN, and the other control terminal of transmission gate T5 is connected to signal control are connected. The output terminal of transmission gate T5 is respectively connected to the output terminal of transmission gate T3, the non-inverting input terminal of amplifier OP4, and the drain of NMOS transistor M7. The gate of NMOS transistor M7 is respectively connected to the gates of NMOS transistors M9, M20, M15, and bias terminal VB2. The source of NMOS transistor M7 is connected to the drain of NMOS transistor M8. The gate of NMOS transistor M8 is respectively connected to the gates of NMOS transistors M10, the drain of NMOS transistor M9, the drain of NMOS transistor M18, and the drain of PMOS transistor M11. The source of NMOS transistor M9 is connected to the drain of NMOS transistor M10. The gate of PMOS transistor M12 is respectively connected to the gates of PMOS transistors M11, the drain of PMOS transistor M12, and one end of current source IR2. The other end of current source IR2 is respectively connected to the sources of NMOS transistors M1, M2, M8, M10, and external ground GND.

3. The wide matching range charge pump applied to a phase-locked loop system according to claim 1, wherein The discharge current compensation circuit (3) includes: a PMOS transistor M16, an NMOS transistor M17, an NMOS transistor M18, an NMOS transistor M20, an amplifier OP3, an amplifier OP4, and a transmission gate T6. The inverting input terminal of the amplifier OP3 is respectively connected to the output terminal of the amplifier OP3 and the source electrode of the PMOS transistor M16. The drain electrode of the PMOS transistor M16 is respectively connected to the drain electrode of the NMOS transistor M17, the gate electrode of the NMOS transistor M17, and the gate electrode of the NMOS transistor M18. The source electrode of the NMOS transistor M17 is respectively connected to the source electrode of the NMOS transistor M18 and an external ground wire GND. One control terminal of the transmission gate T6 is connected to the signal control terminal DN, and the other control terminal of the transmission gate T6 is connected to the signal control terminal connected. The output terminal of the transmission gate T6 is connected to the drain electrode of the NMOS transistor M20. The source electrode of the NMOS transistor M20 is respectively connected to the output terminal of the amplifier OP4 and the inverting input terminal of the amplifier OP4.

4. A wide matching range charge pump applied to a phase-locked loop system according to claim 1, characterized in that In the charging current compensation circuit (1), the PMOS transistor M13, the PMOS transistor M14, the NMOS transistor M15, and the amplifier OP2 form a compensation circuit for the charging current in the low voltage region, which improves the matching range of the charging current in the low voltage region. The amplifier OP2 forms a unity gain negative feedback such that the source voltage of its NMOS transistor M15 is equal to the voltage V of the charge pump output terminal VC. C , when the voltage V of the charge pump output terminal VC C is relatively low, the NMOS transistor M15 is turned on and its drain current where, μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L) 15 is the channel width-to-length ratio of the NMOS transistor M15, V B2 is the voltage of the bias terminal VB2, V THn is the threshold voltage of the NMOS transistor. The PMOS transistor M13 and the PMOS transistor M14 are exactly the same. The drain current I 13 of the PMOS transistor M13 and the drain current I 14 of the PMOS transistor M14 have I 13 = I 14 = I 15 .

5. The wide matching range charge pump applied to a phase-locked loop system according to claim 4, wherein In the charging current compensation circuit (1), the amplifier OP5, the PMOS transistor M19, and the transmission gate T1 form a compensation circuit for the charging current in the high-voltage region, improving the matching range of the charging current in the high-voltage region. When the voltage V of the output terminal VC of the charge pump C rises, the drain voltage V of the PMOS transistor M6 in the charge pump core circuit (2) A also rises. The amplifier OP5 forms a unity-gain negative feedback such that the source voltage of the PMOS transistor M19 is equal to V A . When |V A - V B1 | > |V THP |, the PMOS transistor M19 is turned on, where V B1 is the voltage of the bias terminal VB1, and V THP is the threshold voltage of the PMOS transistor. Then, the drain current of the PMOS transistor M19 where μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, and (W / L) 19 is the channel width-to-length ratio of the PMOS transistor M19.

6. The wide matching range charge pump applied to a phase-locked loop system according to claim 2, wherein In the charge pump core circuit (2), the currents flowing through current source IR1 and current source IR2 are the same and both equal to I REF , NMOS transistors M1 and M2 are exactly the same, PMOS transistors M4 and M5 are exactly the same, PMOS transistors M3 and M6 are exactly the same, then the drain current I6 of PMOS transistor M6 = I REF -I 15 , where I 15 is the drain current of NMOS transistor M15; PMOS transistors M11 and M12 are exactly the same, NMOS transistors M8 and M10 are exactly the same, NMOS transistors M7 and M9 are exactly the same, then the drain current I7 of NMOS transistor M7 = I REF -I 16 , where I 16 is the drain current of PMOS transistor M16, the signal control terminal DN and the signal control terminal UP have opposite signals, the signal control terminal DN and the signal control terminal have opposite signals, the signal control terminal UP and the signal control terminal have opposite signals. When the signal control terminal UP is at a high potential and the signal control terminal DN is at a low potential, transmission gate T4 is turned on and transmission gate T5 is turned off, and the charge pump charging current I UP charges the filter circuit of the phase-locked loop system (and I UP = I6 + I 19 ), and the voltage V C at the charge pump output terminal VC gradually rises, where I 19 is the drain current of PMOS transistor M19. When the voltage V C is at a low voltage, PMOS transistor M19 is cut off and NMOS transistor M15 is turned on, and the current I 15 of NMOS transistor M15 compensates the charging current I UP to broaden the matching range of the low voltage region; when the voltage V C is at a high voltage, NMOS transistor M15 is cut off and PMOS transistor M19 is turned on, and the current I 19 of PMOS transistor M19 compensates the charging current I UP to broaden the matching range of the high voltage region.

7. The wide matching range charge pump applied to a phase-locked loop system according to claim 6, characterized in that In the charge pump core circuit (2), when the signal control terminal UP is at a low potential and the signal control terminal DN is at a high potential, the charge pump discharge current I DN discharges the filter circuit of the phase-locked loop system, and I DN = I7 + I 20 , where I7 is the drain current of the NMOS transistor M7, and I 20 is the drain current of the NMOS transistor M20. The voltage V C at the charge pump output terminal VC gradually decreases. When the voltage V C is at a high potential, the PMOS transistor M16 is turned on and the NMOS transistor M20 is turned off. The current I 16 of the PMOS transistor M16 compensates for the discharge current I DN to broaden the matching range in the high voltage region; when the voltage V C is at a low potential, the PMOS transistor M16 is turned off and the NMOS transistor M20 is turned on. The current I 20 of the NMOS transistor M20 compensates for the discharge current I DN to broaden the matching range in the low voltage region.

8. A wide matching range charge pump applied to a phase-locked loop system according to claim 3, characterized in that In the discharge current compensation circuit (3), the PMOS transistor M16, the NMOS transistor M17, the NMOS transistor M18, and the amplifier OP3 form a compensation circuit for the discharge current in the high-voltage region, improving the matching range of the discharge current in the high-voltage region. The amplifier OP3 forms a unity-gain negative feedback, making the source voltage of the PMOS transistor M16 equal to the voltage V of the output terminal VC of the charge pump. C , when the voltage V of the output terminal VC of the charge pump C is relatively high, the PMOS transistor M16 is turned on and its drain current where μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, (W / L) 16 is the channel width-to-length ratio of the PMOS transistor M16, V B1 is the voltage of the bias terminal VB1, V THP is the threshold voltage of the PMOS transistor. The NMOS transistor M18 is exactly the same as the NMOS transistor M17. Then, the drain current I 18 of the NMOS transistor M18 and the drain current I 17 of the NMOS transistor M17 satisfy I 18 = I 17 = I 16 .

9. A wide matching range charge pump applied to a phase-locked loop system according to claim 8, characterized in that In the discharge current compensation circuit (3), the amplifier OP4, the NMOS transistor M20, and the transmission gate T6 constitute a compensation circuit for the discharge current in the low-voltage region, improving the matching range of the discharge current in the low-voltage region. When the voltage V C at the output terminal VC of the charge pump decreases, the drain voltage V B of the NMOS transistor M7 in the charge pump core circuit (2) also decreases. The amplifier OP4 forms a unity-gain negative feedback such that the source voltage of the NMOS transistor M20 is equal to V B . When V B2 - V B > V THn , the NMOS transistor M20 is turned on, and the drain current of the NMOS transistor M20 is where μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L) 20 is the channel width-to-length ratio of the NMOS transistor M20, V B2 is the voltage of the bias terminal VB2, and V THn is the threshold voltage of the NMOS transistor.

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