A method for manufacturing a chip and a chip

Abstract

The embodiment of the present invention provides a method for manufacturing a chip and the chip, the method comprising the following steps: S1, providing a substrate and an organic connection bridge each having a redistribution wire built therein; S2, placing the organic connection bridge on the surface of the substrate; S3, fixing at least two bare chips on the substrate, wherein the pins of each bare chip are connected to the connection points on the substrate and the organic connection bridge; S4, protecting the connection between the bare chip and the connection bridge. The method uses organic materials to prepare the connection bridge, reduces the stress on the connection bridge, and thus improves the reliability of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a method for manufacturing a chip and a chip. Background Art

[0002] In the prior art, embedded silicon bridge (EMIB) is usually used to embed a small passive bridge chip prepared on a silicon substrate into the substrate, which becomes a part of the substrate and is used to connect multiple sub-chips. This process is complex and requires the placement of a silicon bridge during the production of the substrate. In addition, during the production process, since the thermal expansion coefficient of silicon in the silicon bridge is small and the thermal expansion coefficient of the substrate material is large, the thermal expansion coefficient of the substrate is generally more than 6 times that of the silicon bridge. During the heating and cooling process, large stress will be generated, which will cause the copper through-hole connection connecting the silicon bridge to the surface sub-chip to break or the dielectric layer to delaminate. Summary of the invention

[0003] The purpose of the embodiments of the present invention is to provide a method for manufacturing a chip and the chip, wherein the method reduces the stress on the connecting bridge, thereby improving the reliability of the chip.

[0004] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a method for manufacturing a chip, which includes the following steps: S1, providing a substrate and an organic connection bridge, each of which has a redistribution conductor built in and a connection point externally arranged; S2, placing the organic connection bridge on the surface of the substrate; S3, fixing at least two bare chips on the substrate, wherein the pins of each bare chip are connected to the connection points on the substrate and the organic connection bridge; S4, protecting the connection points between the pins of the bare chip and the substrate and the organic connection bridge.

[0005] Optionally, for step S1, providing the organic connecting bridge includes: S21: providing a carrier, the carrier including a first part and a second part, the first part being the outer edge of one side of the carrier, and the second part being the side plane defined by the outer edge; S22: adding a release adhesive to the first part, adding a metal film to the second part, and curing the release adhesive; S23: adding a dielectric layer to the surface of the metal film; S24: preparing a redistribution wire layer on the dielectric layer; S25: removing the current first part, the current first part at least including the release adhesive attached thereto; and, S26: peeling off the current second part and cutting to form an organic connecting bridge.

[0006] Optionally, for step S2, grooves are formed on the surface of the substrate to embed the organic connecting bridges, or the organic connecting bridges are directly mounted on the surface of the substrate.

[0007] Optionally, the depth of the grooves of the substrate ranges from 5 to 30 microns.

[0008] Optionally, for step S4, the connection between the pins of the bare chip and the connection bridge is protected by plastic encapsulation molding and / or bottom filling.

[0009] Optionally, for step S3, connection points are provided on the surface of the substrate and on the organic connection bridge so that the bare chip is connected to the substrate and the organic connection bridge respectively through corresponding solder joints.

[0010] Optionally, the dielectric materials of the organic connecting bridge and the substrate are both organic materials, and the thermal expansion coefficients of the substrate and the organic connecting bridge match.

[0011] The present invention also proposes a chip, which includes: a substrate and an organic connecting bridge arranged on the surface of the substrate, wherein the substrate and the organic connecting bridge each have a redistribution wire built in and a connection point externally arranged; and at least two bare chips fixed on the surface of the substrate, wherein each bare chip pin is connected to the connection points on the substrate and the organic connecting bridge.

[0012] Optionally, the organic connection bridge is disposed in a groove on one side of the substrate, or the organic connection bridge is mounted on one side of the substrate.

[0013] Optionally, the depth of the grooves of the substrate ranges from 5 to 30 microns.

[0014] The method of the embodiment of the present invention enables the chips to transmit signals through the organic connecting bridge. The organic connecting bridge matches the thermal expansion coefficient of the substrate and there is no stress caused by thermal expansion, thereby improving the reliability of the chip.

[0015] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0017] Figure 1 It is a schematic flow chart of a method for manufacturing a chip of the present invention;

[0018] Figure 2 It is a schematic flow chart of a method for making a connecting bridge of the present invention;

[0019] Figure 3a-3d It is a schematic diagram of a method for manufacturing a connecting bridge of the present invention;

[0020] Figure 4is a schematic diagram of an embodiment of a method for manufacturing a chip of the present invention;

[0021] Figure 5 is a schematic diagram of another embodiment of a method for manufacturing a chip according to the present invention;

[0022] Figure 6 and Figure 7 It is a schematic diagram of a connection bridge connection method of multiple chips of the present invention.

[0023] Description of Reference Numerals

[0024] 101-first sub-chip;

[0025] 102-second sub-chip;

[0026] 103-organic connecting bridge;

[0027] 104-Substrate;

[0028] 105-the third sub-chip;

[0029] 106- the fourth sub-chip;

[0030] 203-First connecting bridge;

[0031] 303-Second connecting bridge;

[0032] 403-Third connecting bridge;

[0033] 503-The fourth connecting bridge. DETAILED DESCRIPTION

[0034] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0035] Figure 1 FIG. 1 is a flow chart of a method for making a chip according to the present invention. Figure 1 As shown, the method for making a chip of the present invention comprises:

[0036] Step S1: Provide a substrate 104 and an organic connection bridge 103 each having a redistribution wire built therein. The dielectric materials of the organic connection bridge 103 and the substrate 104 are both organic materials. When designing the organic connection bridge, a suitable organic material and wiring structure can be selected to match the thermal expansion coefficient of the organic connection bridge 103 and the substrate 104. The organic connection bridge 103 with this design can avoid stress caused by thermal expansion.

[0037] With respect to step S1, providing the organic connecting bridge 103 includes: Figure 2As shown: S21, providing a carrier, the carrier includes a first part and a second part, the first part is the outer edge of one side of the carrier, and the second part is the side plane defined by the outer edge; S22, adding a release adhesive to the first part; S23, adding a metal film to the second part, and curing the release adhesive; S24, adding a dielectric layer on the surface of the metal film; S25, preparing a redistribution wire layer on the dielectric layer; S26, removing the current first part, the current first part at least includes the release adhesive attached thereto; and S27, peeling off the current second part, cutting to form an organic connection bridge 103. Specifically, as Figure 3a-3d As shown, providing a carrier includes: providing a carrier prepared by at least one of silicon, glass, metal and organic plastic. A multilayer redistribution conductor is prepared by photolithography and electroplating processes to generate an intermediate layer structure. Finally, the carrier is peeled off to obtain the organic connecting bridge 103. In this preparation process, glass glue is only provided on the edge of the carrier, and no peeling glue is provided in the area where the organic connecting bridge 103 is prepared. The middle area is laminated on the carrier in a vacuum and then the edge is sealed to form the carrier, so the carrier can be peeled off without high temperature and stress. This solution can peel off the organic connecting bridge 103 less than 30 microns.

[0038] The present invention uses mature packaging and wafer back-end processes to make the interposer. The line width and line spacing can be made less than 1-2um, and high-density and high-bandwidth I / O channels can be prepared. In addition, the method selects an organic material that matches the thermal expansion coefficient of the substrate 104 to prepare the bridge chip, and finally removes the carrier. The entire connecting bridge is composed of organic dielectric materials and copper wiring, and there is no material with a smaller thermal expansion coefficient (such as silicon). The stress on the organic connecting bridge 103 caused by the substrate 104, bottom filling or plastic packaging can be avoided, thereby improving the reliability of the chip.

[0039] Step S2: placing the organic connection bridge 103 on the surface of the substrate 104. According to a specific embodiment, a groove is made on the surface of the substrate 104 to embed the organic connection bridge 103, or the organic connection bridge 103 is directly mounted on the surface of the substrate 104. When the chip design allows for a larger spacing and a higher connection point (e.g., the chip and the substrate 104 are connected at a height greater than 70 microns), the organic connection bridge 103 can be directly mounted on the reserved area of ​​the substrate 104 without making any changes to the substrate 104. Alternatively, if the bump used to connect the chip to the substrate 104 is less than 70 microns after connection, the reserved area of ​​the substrate 104 can be modified, and a groove can be reserved when preparing the substrate 104. The thickness of this groove and the surface passivation layer (such as solder resist) is close to less than 30 microns. It is only necessary to reserve the organic connection bridge 103 area during the last passivation layer lithography, remove the surface passivation layer, or use laser grooving to remove a portion of the surface passivation layer to accommodate the organic connection bridge 103. Preferably, the depth of the grooves of the substrate 104 is in the range of 5-30 microns, which can be designed according to the height of the connection point between the chip and the substrate 104. Solder points are provided on the surface of the substrate 104 and on the organic connection bridge 103, for connecting the sub-chip to the substrate 104 and the organic connection bridge 103 respectively.

[0040] Figure 4 In order to groove the surface of the substrate 104 to embed the organic connection bridge 103, it specifically includes: grooves are made on the substrate 104, and the size of the grooves is determined according to the size of the organic connection bridge 103. Adhesive is applied to the inner wall of the groove, and the organic connection bridge 103 is placed to make it adhere to the adhesive. Redistribution wires are provided in both the substrate 104 and the organic connection bridge 103, and the redistribution wires of the two are led out to the surface to the soldering points, and finally the sub-chips (the first sub-chip 101 and the second sub-chip 102) are arranged. The surface grooves can be prepared in advance on the substrate 104, or laser grooves can be used later. The depth of the grooves can also be flexibly optimized according to the height of the soldering points and the thickness of the organic connection bridge 103. The step height of the bridge chip on the surface after connection will also vary between 0 and 30 microns depending on the design.

[0041] Figure 5 The schematic diagram is for directly mounting the organic connection bridge on the surface of the substrate, specifically including directly mounting the organic connection bridge 103 on the substrate 104, both the substrate 104 and the organic connection bridge 103 are provided with redistribution wires, the redistribution wires of the two are led out to the surface to be soldered, and finally the sub-chips (the first sub-chip and the second sub-chip 102) are arranged.

[0042] Step S3: fix at least two sub-chips on the substrate 104, wherein the pins of each sub-chip are connected to the substrate 104 and the redistribution wires in the organic connecting bridge 103. The present application can also be used to connect multiple small sub-chips, for example, four sub-chips with a size of 15mm x 15mm can be connected into a large chip of 30mm x 30mm, such as Figure 7 shown.

[0043] Step S4: Protect the connection between the pins of the bare chip and the connection bridge 103. For step S4, the protection can be achieved by plastic molding and / or bottom filling (such as Figure 4 and Figure 5 After this step, the chip can be connected to the main board or other circuits through the connection points on the other side of the substrate 104. Solder balls, contact pads or needles can be set on the connection points. This conventional setting will not be repeated.

[0044] The present invention also provides a chip, which includes: a substrate 104 and an organic connection bridge 103 arranged on the surface of the substrate 104, wherein the substrate 104 and the organic connection bridge 103 each have a redistribution wire built in and a connection point externally arranged; and at least two sub-chips fixed on the surface of the substrate 104, wherein each sub-chip pin is connected to the substrate 104 and the connection point on the organic connection bridge 103, and signals are transmitted between chips through the redistribution wires. The organic connection bridge 103 is arranged in a groove on one side of the substrate 104, or the organic connection bridge 103 is mounted on one side of the substrate 104. Figure 6 and Figure 7 As shown, Figure 6 The first sub-chip 101 and the second sub-chip 102 are connected by an organic connecting bridge 103, a groove is opened on the surface of the substrate 104 to embed the organic connecting bridge 103, or the organic connecting bridge 103 is directly mounted on the surface of the substrate 104, and all three are arranged on the substrate 104. Figure 7The first sub-chip 101 and the second sub-chip 102 are connected by the first connecting bridge 203, the first sub-chip 101 and the fourth sub-chip 106 are connected by the fourth connecting bridge 503, the second sub-chip 102 and the third sub-chip 105 are connected by the second connecting bridge 303, and the third sub-chip 105 and the fourth sub-chip 106 are connected by the third connecting bridge 403. Grooves are made on the surface of the substrate to embed the connecting bridges (i.e., organic connecting bridges, including the first connecting bridge 203, the second connecting bridge 303, the third connecting bridge 403, and the fourth connecting bridge 503), or the connecting bridges (i.e., organic connecting bridges, including the first connecting bridge 203, the second connecting bridge 303, the third connecting bridge 403, and the fourth connecting bridge 503) are directly mounted on the surface of the substrate 104. The depth of the grooves of the substrate 104 ranges from 5 to 30 microns.

[0045] Since the chip manufacturing method of the present invention only uses an organic dielectric layer and a wire to prepare the organic connecting bridge 103, a suitable organic dielectric layer can be selected to match the thermal expansion coefficient of the substrate 104, and multiple high-power chips (such as CPU, GPU, AI chip) can be connected together to generate a higher performance chip. When this high-performance chip generates heat, the material in the chip will expand and contract. This method will not generate stress on the connecting bridge due to different thermal expansion coefficients, and the produced chips have higher reliability.

[0046] The optional implementation modes of the embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above implementation modes. Within the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical scheme of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention.

[0047] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the present invention will not further describe various possible combinations.

[0048] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0049] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A method for manufacturing a chip, characterized in that: The method comprises the following steps: S1: providing a substrate and an organic connection bridge each having a redistribution conductor built in and a connection point externally disposed; S2: placing the organic connecting bridge on the surface of the substrate; S3: fixing at least two bare chips on the substrate, wherein the pins of each bare chip are connected to the substrate and the connection points on the organic connection bridge; S4: protecting the connection between the bare chip and the connection bridge; With respect to step S1, providing the organic connecting bridge comprises: S21: providing a carrier board, the carrier board comprising a first portion and a second portion, the first portion being an outer edge of one side of the carrier board, and the second portion being a side plane defined by the outer edge; S22: adding a release adhesive to the first portion, adding a metal film to the second portion, and curing the release adhesive; S23: adding a dielectric layer on the surface of the metal film; S24: preparing a redistribution conductor layer on the dielectric layer; S25: removing the current first part, where the current first part at least includes the release adhesive attached thereto; and S26: peeling off the second part of the current without high temperature and stress, cutting to form an organic connecting bridge; The method further comprises: No release adhesive is provided in the region where the organic connecting bridge is prepared, and the middle region is laminated on the carrier in vacuum and then the edges are sealed to form the carrier.

2. The method according to claim 1, characterized in that With respect to step S2 , grooves are formed on the surface of the substrate to embed the organic connecting bridges, or the organic connecting bridges are directly mounted on the surface of the substrate.

3. The method according to claim 2, characterized in that The depth of the grooves of the substrate ranges from 5 to 30 microns.

4. The method according to claim 1, characterized in that With respect to step S4, the connection between the bare chip and the connection bridge is protected by plastic encapsulation molding and / or bottom filling.

5. The method according to claim 1, characterized in that With respect to step S3, connection points are provided on the surface of the substrate and on the organic connection bridge so that the bare chip is connected to the substrate and the organic connection bridge respectively through corresponding solder joints.

6. The method according to claim 1, characterized in that The dielectric materials of the organic connecting bridge and the substrate are both organic materials, and the thermal expansion coefficients of the substrate and the organic connecting bridge match each other.

7. A chip, characterized in that: Chips include: A substrate and an organic connection bridge disposed on a surface of the substrate, wherein the substrate and the organic connection bridge each have a built-in redistribution wire; as well as at least two bare chips fixed to the surface of the substrate, wherein each bare chip lead is connected to a connection point on the substrate and the organic connecting bridge; The method for preparing the organic connecting bridge comprises: S21: providing a carrier board, the carrier board comprising a first portion and a second portion, the first portion being an outer edge of one side of the carrier board, and the second portion being a side plane defined by the outer edge; S22: adding a release adhesive to the first portion, adding a metal film to the second portion, and curing the release adhesive; S23: adding a dielectric layer on the surface of the metal film; S24: preparing a redistribution conductor layer on the dielectric layer; S25: removing the current first part, where the current first part at least includes the release adhesive attached thereto; and S26: peeling off the second part of the current without high temperature and stress, cutting to form an organic connecting bridge; The preparation method further comprises: No release adhesive is provided in the region where the organic connecting bridge is prepared, and the middle region is laminated on the carrier in vacuum and then the edges are sealed to form the carrier.

8. The chip according to claim 7, characterized in that: The organic connecting bridge is arranged in a groove on one side of the substrate, or, The organic connecting bridge is mounted on one side of the substrate.

9. The chip according to claim 7, characterized in that: The depth of the grooves of the substrate ranges from 5 to 30 microns.

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