Circuit board

Abstract

The circuit board according to an embodiment includes: an insulating layer; a first circuit pattern disposed on a first surface of the insulating layer; a first solder resist disposed on the first surface of the insulating layer; and a first barrier layer including a 1-1 portion disposed between the first solder resist and the first circuit pattern and a 1-2 portion disposed between the insulating layer and the first circuit pattern, wherein the 1-1 portion of the first barrier layer includes a 1-1 gold (Au) layer disposed on a bottom surface of the first circuit pattern and a 1-1 palladium (Pd) layer disposed on a bottom surface of the 1-1 gold (Au) layer, the 1-2 portion of the first barrier layer includes a 1-2 gold (Au) layer surrounding a side surface and an upper surface of the first circuit pattern and a 1-2 palladium (Pd) layer surrounding the 1-2 gold (Au) layer, and the 1-1 portion and the 1-2 portion of the first barrier layer secure the first circuit pattern from being in contact with the first solder resist and the insulating layer.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a circuit board. BACKGROUND

[0002] As the miniaturization, weight reduction, and integration of electronic components are accelerated, the line width of a circuit has become small. Specifically, since a semiconductor chip is designed to be integrated at a nanometer level, the circuit line width of a package substrate or a printed circuit board on which the semiconductor chip is mounted has become small to below several micrometers.

[0003] Various methods have been proposed to increase the circuit integration of a printed circuit board, that is, to reduce the circuit line width. For the purpose of preventing the loss of the circuit line width in an etching step of forming a pattern after copper plating, a semi-additive process (SAP) method and a modified semi-additive process (MSAP) have been proposed.

[0004] For this, an embedded trace substrate (hereinafter referred to as "ETS") method for embedding a copper foil in an insulating layer to realize a fine circuit pattern has been used in the industry. In the ETS method, instead of forming a copper foil circuit on the surface of an insulating layer, a copper foil circuit is manufactured in an embedded form in the insulating layer, and thus there is no circuit loss due to etching, and it is advantageous in that the circuit pitch becomes small.

[0005] Meanwhile, recently, there have been efforts to develop an improved 5G (5th-Generation) communication system or a communication system before 5G to meet the demand for wireless data traffic. Here, the 5G communication system uses an ultra-high frequency (mmWave) band (6 GHz or less, 28 GHz, 38 GHz, or a frequency higher than 38 GHz) to achieve a high data transmission rate.

[0006] In addition, in the 5G communication system, integration technologies such as beamforming, massive multi-input multi-output (massive MIMO), and array antennas have been developed to reduce the path loss of radio waves and increase the transmission distance of radio waves in an ultra-high frequency band. Since the antenna system can be composed of several hundred active antennas whose wavelengths are in these frequency bands, the antenna system is relatively large.

[0007] Since such an antenna and an AP module are patterned or mounted on a printed circuit board, low loss of the printed circuit board is very important. This means that several substrates constituting an active antenna system, that is, an antenna substrate, an antenna feed substrate, a transceiver substrate, and a baseband substrate, should be integrated into one small unit.

[0008] In addition, the above-described circuit board applied to the 5G communication system is manufactured according to the trend of being light, thin, and compact, and thus the circuit pattern gradually becomes finer.

[0009] However, the interval between patterns in a circuit board including a conventional fine circuit pattern becomes narrow as the interval between the patterns becomes small, and thus a reliability problem occurs. Specifically, at the time of reliability evaluation, the metal material constituting the circuit pattern in the conventional circuit board migrates, thereby causing a reliability problem. SUMMARY

[0010] TECHNICAL PROBLEM

[0011] Embodiments provide a circuit board having a novel structure and a manufacturing method thereof.

[0012] In addition, embodiments provide a circuit board capable of suppressing migration of a metal material constituting a circuit pattern to an insulating layer and a manufacturing method thereof.

[0013] In addition, embodiments provide a circuit board capable of suppressing migration of a metal material constituting a circuit pattern to a solder resist and a manufacturing method thereof.

[0014] The technical problems addressed by the proposed embodiments are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by a person skilled in the art to which the embodiments proposed below belong.

[0015] TECHNICAL SOLUTION

[0016] The circuit board according to an embodiment includes an insulating layer, a first circuit pattern disposed on a first surface of the insulating layer, a first solder resist disposed on the first surface of the insulating layer, and a first barrier layer including a first-first portion disposed between the first solder resist and the first circuit pattern and a first-second portion disposed between the insulating layer and the first circuit pattern, wherein the first-first portion of the first barrier layer includes a first-first gold (Au) layer disposed below a lower surface of the first circuit pattern and a first-first palladium (Pd) layer disposed below a lower surface of the first-first gold (Au) layer, wherein the first-second portion of the first barrier layer includes a first-second gold (Au) layer disposed to surround a side surface and an upper surface of the first circuit pattern and a first-second palladium (Pd) layer disposed to surround the first-second gold (Au) layer, and wherein the first circuit pattern is not in contact with the first solder resist and the insulating layer through the first-first portion and the first-second portion of the first barrier layer.

[0017] In addition, the first-first gold (Au) layer has a first width, and the lower surface of the first circuit pattern has a second width smaller than the first width.

[0018] Further, the lower surface of the first-first gold (Au) layer includes a first region in contact with the lower surface of the first circuit pattern, a second region in contact with the first-second palladium (Pd) layer, and a third region in contact with the first-second gold (Au) layer.

[0019] Further, the first circuit pattern is buried in a lower region of the insulating layer.

[0020] Further, the lower surface of the first circuit pattern is in the same plane as the lower surface of the insulating layer, and the first-first portion of the first barrier layer is disposed to protrude downward from the lower surface of the insulating layer.

[0021] Further, the circuit board further includes a second circuit pattern disposed on a second surface of the insulating layer, a second solder resist disposed on the second surface of the insulating layer, and a second barrier layer including a second-first portion disposed between the insulating layer and the second circuit pattern and a second-second portion disposed between the second solder resist and the second circuit pattern.

[0022] Further, the second-first portion of the second barrier layer includes a second-first gold (Au) layer disposed below a lower surface of the second circuit pattern and a second-first palladium (Pd) layer disposed between a lower surface of the second-first gold (Au) layer and an upper surface of the insulating layer, wherein the second-second portion of the second barrier layer includes a second-second gold (Au) layer disposed around a side surface and an upper surface of the second circuit pattern and a second-second palladium (Pd) layer disposed around the second-second gold (Au) layer, and wherein the second circuit pattern is not in contact with the insulating layer and the second solder resist through the second-first portion and the second-second portion of the second barrier layer.

[0023] Further, the second-first gold (Au) layer has a first width, and the lower surface of the second circuit pattern has a second width that is less than the first width.

[0024] Further, the lower surface of the second-first gold (Au) layer includes a first region in contact with the lower surface of the second circuit pattern, a second region in contact with the second-second palladium (Pd) layer, and a third region in contact with the second-second gold (Au) layer.

[0025] Further, the second circuit pattern is disposed to protrude above the upper surface of the insulating layer.

[0026] On the other hand, the method of manufacturing a circuit board according to the embodiment includes: preparing a support plate; forming a first-first portion of a first barrier layer on the support plate; forming a first circuit pattern on the first-first portion of the first barrier layer; forming a first-second portion of the first barrier layer on the first circuit pattern; forming an insulating layer covering the first circuit pattern on the first-first portion of the first barrier layer; forming a second-first portion of a second barrier layer on a lower surface of the insulating layer; forming a second circuit pattern on the second-first portion of the second barrier layer; forming a second-second portion of the second barrier layer on the second circuit pattern; removing the support plate; forming a first solder resist under the lower surface of the insulating layer; and forming a second solder resist on an upper surface of the insulating layer, wherein the first-first portion of the first barrier layer includes: a first-first gold (Au) layer disposed under a lower surface of the first circuit pattern; and a first-first palladium (Pd) layer disposed under a lower surface of the first-first gold (Au) layer, wherein the first-second portion of the first barrier layer includes: a first-second gold (Au) layer disposed to surround a side surface and an upper surface of the first circuit pattern; and a first-second palladium (Pd) layer disposed to surround the first-second gold (Au) layer, wherein the second-first portion of the second barrier layer includes: a second-first gold (Au) layer disposed under a lower surface of the second circuit pattern; and a second-first palladium (Pd) layer disposed between the lower surface of the second-first gold (Au) layer and the upper surface of the insulating layer, and wherein the second-second portion of the second barrier layer includes: a second-second gold (Au) layer disposed to surround a side surface and an upper surface of the second circuit pattern; and a second-second palladium (Pd) layer disposed to surround the second-second gold (Au) layer.

[0027] Further, the first circuit pattern is not in contact with the first solder resist and the insulating layer through the first-first portion and the first-second portion of the first barrier layer, and the second circuit pattern is not in contact with the insulating layer and the second solder resist through the second-first portion and the second-second portion of the second barrier layer.

[0028] Further, the first-first gold (Au) layer or the second-first gold (Au) layer has a first width, and the lower surface of the first circuit pattern or the lower surface of the second circuit pattern has a second width smaller than the first width.

[0029] Further, the lower surface of the first-first gold (Au) layer includes: a first region in contact with the lower surface of the first circuit pattern; a second region in contact with the first-second palladium (Pd) layer; and a third region in contact with the first-second gold (Au) layer.

[0030] Further, the lower surface of the first circuit pattern is on the same plane as the lower surface of the insulating layer, and the first-first portion of the first barrier layer is disposed to protrude downward from the lower surface of the insulating layer.

[0031] Advantageous Effects

[0032] Embodiments provide a circuit board including an insulating layer and a circuit pattern. In this case, the circuit pattern contains a metal material. Also, the circuit pattern containing the metal material is not in direct contact with the insulating layer. To this end, a barrier layer is provided to surround the circuit pattern. Accordingly, embodiments can prevent the metal material constituting the circuit pattern from penetrating into the insulating layer, thereby improving the conductivity and / or physical reliability of the circuit board.

[0033] For example, when the circuit pattern contains copper, the barrier layer includes a metal layer of gold provided to surround the circuit pattern and containing gold (Au), and a metal layer of palladium provided to surround the metal layer of gold and containing palladium (Pd). The metal layer of palladium can prevent copper constituting the circuit pattern from penetrating into the insulating layer, and thus can improve reliability by inhibiting the occurrence of copper migration. Also, the metal layer of gold is provided between the metal layer of palladium and the circuit pattern to form the metal layer of palladium. In this case, the metal layer of gold containing gold (Au) has a grain size greater than that of the other layers, and thus can stably form the metal layer of palladium. For example, when indium tin oxide (ITO) is used as the barrier layer, the ITO can be a non-metallic conductive oxide. Also, when silver (Ag) is used for the circuit pattern, the barrier layer can prevent silver (Ag) constituting the circuit pattern from penetrating into the insulating layer.

[0034] Also, in embodiments, the barrier layer is further formed on the circuit pattern provided on the outermost layer among the circuit patterns in the circuit board. This can prevent copper constituting the circuit pattern of the outermost layer from migrating to the solder resist.

[0035] Also, a portion of the barrier layer is provided on the surface of a buried pattern of an embedded trace substrate (ETS) structure of embodiments. In this case, the barrier layer is provided to protrude on the surface of the buried pattern, and it can be used as a mounting pad on which a solder layer for mounting a device is provided. That is, the buried pattern of a conventional ETS structure is formed as a fine pattern, and thus it cannot be used as a mounting pad having only a simple pattern, and thus a separate mounting pad having a structure in which it is buried in the insulating layer or protrudes above the surface of the insulating layer must be formed. At this time, when the mounting pad is buried in the insulating layer, the interval between the fine patterns is widened by the width of the mounting pad, and thus there is a problem in the degree of integration of the circuit. Also, when a structure in which the mounting pad protrudes above the insulating layer is applied, a separate process is required to form the mounting pad. On the other hand, when the barrier layer is formed on the buried pattern, embodiments allow a portion of the barrier layer to have a structure in which it protrudes above the surface of the insulating layer, and thus the barrier layer can be used as a mounting pad, thereby simplifying the manufacturing process. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a view illustrating a circuit board according to embodiments.

[0037] Figure 2 is a view showing a circuit board including a via according to an embodiment.

[0038] Figures 3 to 15 is a view showing a manufacturing method of a circuit board shown in Figure 1 FIG. 10 in order of steps. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0040] However, the spirit and scope of the present application are not limited to the described part of the embodiments, but can be implemented in various other forms, and one or more elements of the embodiments can be selectively combined and replaced with each other and used within the spirit and scope of the present application.

[0041] In addition, unless explicitly defined and described otherwise, the terms used in the embodiments of the present application, including technical and scientific terms, can be interpreted the same as the meanings commonly understood by those skilled in the art to which the present application pertains and the terms (for example, terms defined in a generally used dictionary) can be interpreted as having meanings consistent with the meanings in the context of the related art. In addition, the terms used in the embodiments of the present application are used to describe the embodiments, and are not intended to limit the present application.

[0042] In the present specification, unless specifically stated and described otherwise in the wording, the singular form can also include the plural form, and when described as "at least one of A (and) B and C (or more)", it can include at least one of all combinations that can be combined with A, B, and C. In addition, in describing elements of the embodiments of the present application, terms such as first, second, A, B, (a), and (b) can be used.

[0043] These terms are used only to distinguish the elements from each other, and the terms do not limit the substance, order, or sequence of the elements. In addition, when one element is described as being "connected", "coupled", or "contacted" with another element, it can not only include the case where the element is directly "connected", "coupled", or "contacted" with the other element, but also include the case where the element is "connected", "coupled", or "contacted" with the other element through another element therebetween.

[0044] In addition, when described as being "on (above)" or "under (below)" each element, "on (above)" or "under (below)" can not only include the case where the two elements are directly connected with each other, but also include the case where one or more other elements are formed or disposed between the two elements. In addition, when expressed as "on (above)" or "under (below)", based on one element, it can not only include the upward direction, but also include the downward direction.

[0045] Figure 1 is a view showing a circuit board according to an embodiment.

[0046] Before describing the present application, as the recent development of 5G technology, interest in a circuit board capable of reflecting the technology is increasing. At this time, in order to apply the 5G technology, the circuit board must have a high multi-layer structure, and thus a circuit pattern must be miniaturized. However, although the comparative example can form a fine pattern, there is a problem that it cannot be stably protected. For example, a circuit pattern applied to a circuit board for 5G has a narrow line width, and thus a gap between patterns becomes narrow. However, although the prior art can form a fine pattern, when a metal material constituting the fine pattern migrates, the migration cannot be suppressed, and thus there is a reliability problem. Accordingly, the embodiment provides a circuit board having a new structure capable of solving the reliability problem.

[0047] In detail, referring to Figure 1 , the circuit board includes an insulating layer 140, a first circuit pattern 130, a first barrier layer 120 and 130, a second circuit pattern 160, a second barrier layer 150 and 170, a first protection layer 180, and a second protection layer 185.

[0048] Before describing Figure 1 , the circuit board according to the embodiment can have a multi-layer structure based on an insulating layer. That is, although the circuit board in Figure 1 is shown as including a single insulating layer, the embodiment is not limited thereto. For example, the circuit board of the embodiment can include a plurality of insulating layers. For example, Figure 1 The insulating layer 140 of Figure 1 may represent a second outermost insulating layer among a plurality of insulating layers, and the second circuit pattern 160 can represent a second outer layer circuit pattern embedded in the first outermost insulating layer.

[0049] The insulating layer 140 can represent any particular layer among a plurality of stacked structures. The insulating layer 140 is a substrate on which a circuit capable of changing a wiring is formed, and can include a printed circuit board, a wiring board, and an insulating substrate made of an insulating material capable of forming a circuit pattern on a surface.

[0050] For example, the insulation layer 140 can be rigid or flexible. For example, the insulation layer 140 can include glass or plastic. Specifically, the insulation layer 140 can include chemically tempered / half-tempered glass (e.g., soda-lime glass, aluminosilicate glass, etc.), tempered or flexible plastic (e.g., polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), etc.), or sapphire.

[0051] Further, the insulation layer 140 can include an optically isotropic film. As an example, the insulation layer 140 can include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic PC, an optically isotropic polymethyl methacrylate (PMMA), etc.

[0052] Further, the insulation layer 140 can be partially bent while having a curved surface. That is, the insulation layer 140 can partially have a plane, and can be partially bent while having a curved surface. Specifically, an end portion of the insulation layer 140 can be bent while having a curved surface, or can be bent or folded while having a surface including a random curvature. Accordingly, the circuit board of the embodiment can be applied to electronic devices having various shapes.

[0053] Further, the insulation layer 140 can be a flexible substrate having flexibility. Further, the insulation layer 140 can be a bent or folded substrate. At this time, the insulation layer 140 can form a wiring layout for electrical wiring based on connection of circuit components, and a conductive body can be disposed on the insulating material. Further, the electrical components can be mounted on the insulation layer 140, a wiring configured to connect the electrical components to constitute a circuit can be formed, and in addition to the function of electrically connecting the components, these components can be mechanically fixed.

[0054] The circuit pattern can be disposed on a surface of the insulation layer 140.

[0055] For example, the first circuit pattern 130 can be disposed under a lower surface of the insulation layer 140.

[0056] Further, the second circuit pattern 160 can be disposed on an upper surface of the insulation layer 140.

[0057] The first circuit pattern 130 can be formed in a manner of being buried in a lower portion of the insulation layer 140. A side surface of the first circuit pattern 130 can be surrounded by the insulation layer 140. However, the side surface of the first circuit pattern 130 can not be in contact with the insulation layer 140. That is, the first-second portion 120 of the first barrier layer can be located between the side surface of the first circuit pattern 130 and the insulation layer 140. Accordingly, the side surface of the first circuit pattern 130 can be spaced apart from the insulation layer 140 by a thickness of the first-second portion 120 of the first barrier layer.

[0058] In addition, the upper surface of the first circuit pattern 130 can be positioned in the insulating layer 140. Specifically, the upper surface of the first circuit pattern 130 can be positioned higher than the lower surface of the insulating layer 140. Meanwhile, the upper surface of the first circuit pattern 130 can not be in contact with the insulating layer 140. That is, the first-second portion 120 of the first barrier layer can be positioned between the upper surface of the first circuit pattern 130 and the insulating layer 140. Accordingly, the upper surface of the first circuit pattern 130 can be spaced apart from the insulating layer 140 by the thickness of the first-second portion 120 of the first barrier layer.

[0059] The lower surface of the first circuit pattern 130 can be positioned on the same plane as the lower surface of the insulating layer 140.

[0060] As described above, the upper surface, the lower surface, and the side surface of the first circuit pattern 130 are not in contact with the insulating layer 140. Accordingly, the embodiment can solve the problem of migration of the metal material constituting the first circuit pattern 130 to the insulating layer 140.

[0061] That is, although the first circuit pattern 130 is buried in the lower portion of the insulating layer 140, it can not be in direct contact with the insulating layer 140 through the first-second portion 120 of the first barrier layer. That is, the first-second portion 120 of the first barrier layer can be positioned between the side surface and the upper surface of the first circuit pattern 130 and the insulating layer 140. Accordingly, the side surface and the upper surface of the first circuit pattern 130 can be spaced apart from the insulating layer 140 by the thickness of the first-second portion 120 of the first barrier layer.

[0062] The second circuit pattern 160 is disposed to protrude on the upper surface of the insulating layer 140. In this case, the second circuit pattern 160 can not be in contact with the insulating layer 140. That is, the lower surface of the second circuit pattern 160 can be spaced apart from the upper surface of the insulating layer 140 by a predetermined gap. That is, the lower surface of the second circuit pattern 160 can be positioned higher than the upper surface of the insulating layer 140. Specifically, the second-first portion 150 of the second barrier layer can be positioned between the lower surface of the first circuit pattern 130 and the upper surface of the insulating layer 140. Accordingly, the lower surface of the second circuit pattern 160 can be spaced apart from the insulating layer 140 by the thickness of the second-first portion 150 of the second barrier layer.

[0063] That is, although the second circuit pattern 160 is disposed on the upper surface of the insulating layer 140, it can not be in direct contact with the insulating layer 140 through the second-first portion 150 of the second barrier layer. That is, the second-first portion 150 of the second barrier layer can be located between the lower surface of the second circuit pattern 160 and the upper surface of the insulating layer 140. Accordingly, the lower surface of the second circuit pattern 160 can be spaced apart from the insulating layer 140 by the thickness of the first portion of the second barrier layer.

[0064] The first circuit pattern 130 and the second circuit pattern 160 described above are wirings for transmitting electrical signals, and can be formed of a metal material having high conductivity. Preferably, the first circuit pattern 130 and the second circuit pattern 160 can be formed of copper (Cu) having high conductivity and being relatively inexpensive.

[0065] Further, by forming the first circuit pattern 130 and the second circuit pattern 160 of copper, migration of copper ions penetrating into the insulating layer 140 can occur. In this case, in the embodiment, the first barrier layer is disposed between the first circuit pattern 130 and the insulating layer 140. Further, in the embodiment, the second barrier layer is disposed between the second circuit pattern 160 and the insulating layer 140. Accordingly, the embodiment can prevent the migration of copper ions from penetrating into the insulating layer 140, thereby improving the reliability of the fine pattern.

[0066] Meanwhile, the first protective layer 180 is disposed below the lower surface of the insulating layer 140. Further, the second protective layer 185 is disposed on the upper surface of the insulating layer 140.

[0067] The first protective layer 180 and the second protective layer 185 can be formed of at least one layer using any one or more of a solder resist (SR), an oxide, and Au. Preferably, the first protective layer 180 and the second protective layer 185 can be a solder resist.

[0068] The first protective layer 180 can be disposed below the lower surface of the insulating layer 140 to protect the first circuit pattern 130.

[0069] For example, the first protective layer 180 can protect the lower surface of the first circuit pattern 130. In this case, the first protective layer 180 can not be in direct contact with the first circuit pattern 130.

[0070] The second protective layer 185 can be disposed to cover the second circuit pattern 160. That is, side surfaces of the second circuit pattern 160 can be surrounded by the second protective layer 185. However, the side surfaces of the second circuit pattern 160 can not be in contact with the second protective layer 185. That is, the second-second portion 170 of the second barrier layer can be located between the side surfaces of the second circuit pattern 160 and the second protective layer 185. Accordingly, the side surfaces of the second circuit pattern 160 can be spaced apart from the second protective layer 185 by a thickness of the second-second portion 170 of the second barrier layer.

[0071] In addition, at least a portion of an upper side of the second circuit pattern 160 can be covered by the second protective layer 185. That is, an upper surface of the second circuit pattern 160 can be located at a lower position than an upper surface of the second protective layer 185. In this case, the upper surface of the second circuit pattern 160 can not be in contact with the second protective layer 185. That is, the second-second portion 170 of the second barrier layer can be located between the upper surface of the second circuit pattern 160 and the second protective layer 185. Accordingly, the upper surface of the second circuit pattern 160 can be spaced apart from the second protective layer 185 by a thickness of the second-second portion 170 of the second barrier layer.

[0072] A lower surface of the second circuit pattern 160 can be located at a higher position than an upper surface of the insulating layer 140 and at a higher position than a lower surface of the second protective layer 185.

[0073] As described above, the upper surface, the lower surface, and the side surfaces of the second circuit pattern 160 are not in contact with the insulating layer 140 and the second protective layer 185. Accordingly, the embodiment can solve a problem in which copper ions constituting the second circuit pattern 160 migrate to the second protective layer 185.

[0074] That is, the second circuit pattern 160 protrudes on the upper surface of the insulating layer 140 and is covered by the second protective layer 185. However, the second circuit pattern 160 can not be in direct contact with the second protective layer 185 through the second-second portion 170 of the second barrier layer. That is, the second-second portion 170 of the second barrier layer can be located between the side surfaces and the upper surface of the second circuit pattern 160 and the second protective layer 185. Accordingly, the side surfaces and the upper surface of the second circuit pattern 160 can be spaced apart from the second protective layer 185 by a thickness of the second-second portion 170 of the second barrier layer.

[0075] Hereinafter, the first barrier layer and the second barrier layer will be described.

[0076] The first barrier layer can be disposed between the first circuit pattern 130 and the insulating layer 140. In addition, the first barrier layer can be disposed between the first circuit pattern 130 and the first protective layer 180.

[0077] Specifically, the first barrier layer includes a first-first portion 110 disposed between the first circuit pattern 130 and the first protective layer 180. Also, the first barrier layer includes a first-second portion 120 disposed between the first circuit pattern 130 and the insulating layer 140.

[0078] Each of the first-first portion 110 and the first-second portion 120 of the first barrier layer can include a plurality of layers.

[0079] That is, the first-first portion 110 of the first barrier layer includes a first-first metal layer 111. The first-first metal layer 111 can be formed of a metal material including palladium (Pd). The first-first metal layer 111 can function to prevent migration of copper ions constituting the first circuit pattern 130 to the first protective layer 180.

[0080] Also, the first-first portion 110 of the first barrier layer includes a first-second metal layer 112 disposed between a lower surface of the first circuit pattern 130 and the first-first metal layer 111. The first-second metal layer 112 can be a seed layer of the first-first metal layer 111. Also, the first-second metal layer 112 can function to largely block migration of copper ions constituting the first circuit pattern 130. Accordingly, in an embodiment, gold (Au) having a relatively large grain size is used to form the first-second metal layer 112 between the first circuit pattern 130 and the first-first metal layer 111. In this case, the first-first metal layer 111 can be referred to as a first-first palladium layer. Also, the first-second metal layer 112 can be referred to as a first-first gold layer.

[0081] The first-second metal layer 112 can be disposed to have a first width below the lower surface of the first circuit pattern 130. In this case, the first width of the first-second metal layer 112 can be greater than a second width of the lower surface of the first circuit pattern 130. Accordingly, the first circuit pattern 130 can not be in contact with the first protective layer 180.

[0082] The first-first metal layer 111 can be disposed to have the same first width as the first-second metal layer 112 below a lower surface of the first-second metal layer 112.

[0083] That is, the first-second portion 120 of the first barrier layer includes a second-first metal layer 121. The second-first metal layer 121 can be formed of a metal material including palladium (Pd). The second-first metal layer 121 can function to prevent migration of copper ions constituting the first circuit pattern 130 to the insulating layer 140.

[0084] Further, the first-second portion 120 of the first barrier layer includes a second-second metal layer 122 disposed between the side surface and the upper surface of the first circuit pattern 130 and the second-first metal layer 121. The second-second metal layer 122 can be a seed layer of the second-first metal layer 121.

[0085] Accordingly, in an embodiment, the second-second metal layer 122 made of a metal including gold (Au) having a relatively large grain size is formed on the side surface and the upper surface of the first circuit pattern 130. The second-first metal layer 121 can be formed by electroplating the second-second metal layer 122 as a seed layer. In this case, the second-first metal layer 121 can be referred to as a first-second palladium layer. Further, the second-second metal layer 122 can be referred to as a first-second gold layer.

[0086] The second-second metal layer 122 can be disposed to surround the side surface and the upper surface of the first circuit pattern 130. Further, the second-first metal layer 121 can be disposed to surround the second-second metal layer 122.

[0087] Meanwhile, the upper surface of the first-second metal layer 112 can include a first region in contact with the lower surface of the first circuit pattern 130. Further, the upper surface of the first-second metal layer 112 can include a second region in contact with the second-first metal layer 121. Further, the upper surface of the first-second metal layer 112 can include a third region in contact with the second-second metal layer 122. Accordingly, the first-first metal layer 111 of the embodiment can not be in contact with the first circuit pattern 130, the second-first metal layer 121, and the second-second metal layer 122.

[0088] The second barrier layer can be disposed between the second circuit pattern 160 and the insulating layer 140. Further, the second barrier layer can be disposed between the second circuit pattern 160 and the second protective layer 185.

[0089] Specifically, the second barrier layer includes a second-first portion 150 disposed between the second circuit pattern 160 and the insulating layer 140. Further, the second barrier layer includes a second-second portion 170 disposed between the second circuit pattern 160 and the second protective layer 185.

[0090] Each of the second-first portion 150 and the second-second portion 170 of the second barrier layer can include a plurality of layers.

[0091] That is, the second-first portion 150 of the second barrier layer includes a third-first metal layer 151. The third-first metal layer 151 can be formed of a metal material including palladium (Pd). The third-first metal layer 151 can function to prevent copper ions constituting the second circuit pattern 160 from migrating to the insulating layer 140.

[0092] In addition, the second-first portion 150 of the second barrier layer includes a third-second metal layer 152 disposed between the lower surface of the second circuit pattern 160 and the third-first metal layer 151. The third-second metal layer 152 can be a seed layer of the third-first metal layer 151. Accordingly, the third-second metal layer 152 of the embodiment contains gold (Au) having a relatively large grain size and is formed on the lower surface of the second circuit pattern 160. In addition, the third-first metal layer 151 can be formed by electroplating with the third-second metal layer 152 as a seed layer. In this case, the third-first metal layer 151 can be referred to as a second-first palladium layer. In addition, the third-second metal layer 152 can be referred to as a second-first gold layer.

[0093] The third-second metal layer 152 can be disposed to have a first width below the lower surface of the second circuit pattern 160. In this case, the first width of the third-second metal layer 152 can be greater than a second width of the lower surface of the second circuit pattern 160. Accordingly, the second circuit pattern 160 can not be in contact with the insulating layer 140.

[0094] The third-first metal layer 151 can be disposed below the lower surface of the third-second metal layer 152 to have the same first width as the third-second metal layer 152.

[0095] That is, the second-second portion 170 of the second barrier layer includes a fourth-first metal layer 171. The fourth-first metal layer 171 can be formed of a metal material containing palladium (Pd). The second-first metal layer 121 can serve to prevent copper ions constituting the second circuit pattern 160 from migrating to the second protective layer 185.

[0096] In addition, the second-second portion 170 of the second barrier layer includes a fourth-second metal layer 172 disposed between the side surface and the upper surface of the second circuit pattern 160 and the fourth-first metal layer 171. The fourth-second metal layer 172 can be a seed layer of the fourth-first metal layer 171. In the embodiment, the fourth-second metal layer 172 of the embodiment contains gold (Au) having a relatively large grain size and is formed on the side surface and the upper surface of the second circuit pattern 160. In addition, the fourth-first metal layer 171 can be formed by electroplating with the fourth-second metal layer 172 as a seed layer. In this case, the fourth-first metal layer 171 can be referred to as a second-second palladium layer. In addition, the fourth-second metal layer 172 can be referred to as a second-second gold layer.

[0097] The fourth-second metal layer 172 can be disposed to surround the side surface and the upper surface of the second circuit pattern 160. Also, the fourth-first metal layer 171 can be disposed to surround the fourth-second metal layer 172.

[0098] Meanwhile, the upper surface of the third-second metal layer 152 can include a first region in contact with the lower surface of the second circuit pattern 160. Also, the upper surface of the third-second metal layer 152 can include a second region in contact with the fourth-first metal layer 171. Also, the upper surface of the third-second metal layer 152 can include a third region in contact with the fourth-second metal layer 172. Accordingly, the third-first metal layer 151 of the embodiment can not be in contact with the second circuit pattern 160, the fourth-first metal layer 171, and the fourth-second metal layer 172.

[0099] Embodiments such as the above provide a circuit board including an insulating layer and a circuit pattern. In this case, the circuit pattern is formed of a metal material including copper. In this case, the circuit pattern formed of the metal material including copper is not in direct contact with the insulating layer. To this end, a barrier layer is disposed around the circuit pattern. For example, the embodiment includes a metal layer of gold including gold (Au) disposed around the circuit pattern, and a metal layer of palladium including palladium (Pd) disposed around the metal layer of gold. The metal layer of palladium can prevent copper constituting the circuit pattern from penetrating into the insulating layer, and thus, it is possible to improve reliability by suppressing copper migration from occurring. Also, the metal layer of gold is disposed between the metal layer of palladium and the circuit pattern to form the metal layer of palladium. In this case, the metal layer of gold includes gold (Au) having a larger grain size than other layers, and thus, it is possible to stably form the metal layer of palladium.

[0100] Also, in the embodiment, the barrier layer is also formed on the circuit pattern disposed in the outermost layer among the circuit patterns. This can prevent copper constituting the circuit pattern of the outermost layer from migrating to the solder resist.

[0101] Further, a portion of the barrier layer is disposed on a surface of a buried pattern of the embedded wiring substrate (ETS) structure of the embodiment. In this case, the barrier layer is disposed to protrude on the surface of the buried pattern, and it can be used as a mounting pad on which a solder layer for mounting a device is disposed. That is, the buried pattern of the conventional ETS structure is formed as a fine pattern, and thus it cannot be used as a mounting pad having only a simple pattern, and thus a separate mounting pad having a structure of being buried in an insulating layer or protruding above a surface of the insulating layer must be formed. At this time, when the mounting pad is buried in the insulating layer, the interval between the fine patterns is widened by the width of the mounting pad, and thus there is a problem of circuit integration. Further, when the structure in which the mounting pad protrudes above the insulating layer is applied, a separate process is required to be processed to form the mounting pad. On the other hand, when the barrier layer is formed on the buried pattern, the embodiment allows a portion of the barrier layer to have a structure of protruding above the surface of the insulating layer, and thus the barrier layer can be used as a mounting pad, thereby simplifying the manufacturing process.

[0102] Figure 2 FIG. 1 is a view showing a circuit board including a via according to an exemplary embodiment.

[0103] Meanwhile, although only a circuit pattern is described in Figure 1 , the circuit board 100A according to the embodiment can include a via 190 disposed in the insulating layer 140.

[0104] Referring to Figure 2 , the via 190 can be formed to pass through the insulating layer 140. Specifically, the via 190 can be electrically connected between the first circuit pattern 130 and the second circuit pattern 160. In this case, the via 190 can be formed of a metal material including copper. Thus, copper ions constituting the via 190 can migrate to the insulating layer 140. Accordingly, the via 190 of the embodiment can have a three-layer structure in a horizontal direction. That is, the via 190 can be formed by electroplating a metal material in a via hole (not shown) passing through the insulating layer 140.

[0105] At this time, when the via hole is formed, the fifth-first metal layer 191 of the embodiment is preferably formed on an inner wall of the via hole. The fifth-first metal layer 191 can be formed of a metal including palladium.

[0106] Further, the via 190 can include a fifth-second metal layer 192 formed on an inner surface of the fifth-first metal layer 191. The fifth-second metal layer 192 can include gold.

[0107] Further, the via 190 can include a fifth-third metal layer 193. The fifth-third metal layer 193 can include copper. The fifth-third metal layer 193 can be formed to fill the inside of the via hole. That is, the via hole of the present embodiment is not entirely filled with the fifth-third metal layer 193, and the fifth-third metal layer 193 is formed after the fifth-first metal layer 191 and the fifth-second metal layer 192 are formed. Accordingly, it is possible to prevent copper ions constituting the fifth-third metal layer 193 from migrating to the insulating layer 140.

[0108] Hereinafter, a method of manufacturing a circuit board according to an embodiment will be described. Figures 3 to 15 is a view illustrating a method of manufacturing a circuit board according to an embodiment. Figure 1 is a view illustrating a method of manufacturing a circuit board according to an embodiment.

[0109] Referring to Figure 3 , a carrier plate 210 serving as a base material is prepared to manufacture a circuit board. The carrier plate 210 can include an insulating member 211 and a metal layer 212 disposed on the insulating member 211.

[0110] In this case, although the metal layer 212 is illustrated as being disposed only on one surface of the insulating member 211 in the drawings, the embodiment is not limited thereto. That is, the metal layer 212 can be disposed on both sides of the insulating member 211, and thus a plurality of circuit boards can be simultaneously manufactured on both sides of the insulating member 212.

[0111] Next, referring to Figure 4 , a first-first portion 110 constituting a first barrier layer is formed on the carrier plate 210.

[0112] That is, the first-first portion 110 of the first barrier layer can include a first-first metal layer 111 disposed on the carrier plate 210 and a first-second metal layer 112 disposed on the first-first metal layer 111.

[0113] The first-first metal layer 111 can include palladium. Further, the first-second metal layer 112 can include gold. The first-first metal layer 111 and the first-second metal layer 112 can be formed by a chemical copper plating process.

[0114] Next, referring to Figure 5 , a first mask M1 of the embodiment is formed on the first-first portion 110 of the first barrier layer. The first mask M1 can include an opening (not shown) exposing an area in which a first circuit pattern 130 is to be formed.

[0115] Further, the first circuit pattern 130 filling the opening of the first mask M1 of the embodiment is formed by electroplating with the first portion of the first barrier layer as a seed layer.

[0116] Next, referring toFigure 6 The first mask M1 is removed, and a second mask M2 is formed on the first-first portion 110 of the first barrier layer. The second mask M2 can include an opening (not shown) that exposes an area where a second-second metal layer 122 is to be formed in the first-second portion 120 of the first barrier layer.

[0117] Then, the second-second metal layer 122 filling the opening of the second mask M2 of the embodiment is formed by electroplating the first-first portion 110 of the first barrier layer as a seed layer.

[0118] Next, referring to Figure 7 The second mask M2 is removed, and a third mask M3 is formed on the first-first portion 110 of the first barrier layer. The third mask M3 can include an opening (not shown) that exposes an area where a second-first metal layer 121 is to be formed in the first-second portion 120 of the first barrier layer.

[0119] Then, the second-first metal layer 121 filling the opening of the third mask M3 of the embodiment is formed by electroplating the first-first portion 110 of the first barrier layer as a seed layer.

[0120] Next, referring to Figure 8 An insulating layer 140 covering the first circuit pattern 130 is formed on the first barrier layer.

[0121] Next, referring to Figure 9 A second-first portion 150 constituting a second barrier layer is formed on the insulating layer 140.

[0122] That is, the second-first portion 150 of the second barrier layer includes a third-first metal layer 151 disposed on the insulating layer 140 and a third-second metal layer 152 disposed on the third-first metal layer 151.

[0123] The third-first metal layer 151 can include palladium. In addition, the third-second metal layer 152 can include gold. The third-first metal layer 151 and the third-second metal layer 152 can be formed by a chemical copper plating process.

[0124] Next, referring to Figure 10 A second circuit pattern 160 is formed on the second-first portion 150 of the second barrier layer by sequentially repeating the processes of Figures 5 to 7 A second-second portion 170 of the second barrier layer is formed on the second circuit pattern 160. The second-second portion 170 of the second barrier layer includes a fourth-first metal layer 171 and a fourth-second metal layer 172.

[0125] Next, referring to Figure 11A process of removing a portion of the second-first portion 150 of the second barrier layer can be performed.

[0126] Next, referring to FIG. 1C, Figure 12 A process of removing the carrier plate 210 can be performed.

[0127] Next, referring to FIG. 1D, Figure 13 A process of removing a portion of the first-first portion 110 of the first barrier layer can be performed.

[0128] Next, referring to FIG. 1E, Figure 14 A process of forming the first protection layer 180 on a lower surface of the insulation layer 140 and forming the second protection layer 185 on an upper surface of the insulation layer 140 can be performed.

[0129] That is, the first protection layer 180 is disposed under the lower surface of the insulation layer 140. In addition, the second protection layer 185 is disposed on the upper surface of the insulation layer 140.

[0130] The first protection layer 180 and the second protection layer 185 can be formed of at least one layer using any one or more of a solder resist (SR), an oxide, and Au. Preferably, the first protection layer 180 and the second protection layer 185 can be a solder resist.

[0131] Meanwhile, referring to FIG. 1F, Figure 15 According to another embodiment, the first protection layer 180A can include an opening (not shown) that exposes a portion of the first-first portion 110 of the first barrier layer.

[0132] In addition, the second protection layer 185A according to another exemplary embodiment can include an opening that exposes a portion of the second-second portion 170 of the second barrier layer.

[0133] Accordingly, in the embodiment, the first barrier layer surrounding the first circuit pattern 130 and the second barrier layer surrounding the second circuit pattern 160 can be formed.

[0134] The features, structures, effects, and the like described in the above-described embodiments are included in at least one embodiment of the present application, and are not limited to only one embodiment. In addition, a person skilled in the art to which the embodiments pertain can combine or modify the features, structures, and effects, and the like described in each of the embodiments for other embodiments. Therefore, it should be understood that matters related to such combinations and changes should be interpreted as included in the scope of the embodiments.

[0135] In the foregoing, the embodiments have been described primarily with respect to examples, but these examples are merely illustrative and not limiting of the embodiments, and it will be understood by those skilled in the art that various changes and applications can be made without departing from the basic features of the embodiments. For example, individual components specifically shown in the embodiments can be implemented by modifications. And differences related to these modifications and these applications should be interpreted as being included in the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board comprising: a first protective layer; a first circuit pattern disposed on the first protective layer; an insulating layer disposed on the first protective layer and the first circuit pattern; and a first barrier layer surrounding an upper surface, a side surface, and a lower surface of the first circuit pattern and disposed in the first protective layer and the insulating layer, wherein the first barrier layer includes a first portion disposed in the first protective layer and a second portion disposed in the insulating layer, wherein the first portion of the first barrier layer includes: a first metal layer disposed below the lower surface of the first circuit pattern; and a second metal layer disposed below a lower surface of the first metal layer and including a different metal material from the first metal layer, wherein the second portion of the first barrier layer includes: a third metal layer disposed to surround the side surface and the upper surface of the first circuit pattern and including a same metal material as the first metal layer; and a fourth metal layer disposed to surround the third metal layer and including a same metal material as the second metal layer. the first metal layer and the third metal layer include gold (Au), and 2. The circuit board of claim 1, wherein, wherein the second metal layer and the fourth metal layer include palladium (Pd). each of the upper surface, the side surface, and the lower surface of the first circuit pattern is not in contact with the insulating layer and the first protective layer.

3. The circuit board of claim 1, wherein, a width of the first metal layer is greater than a width of the first circuit pattern.

4. The circuit board of claim 1, wherein, an upper surface of the first metal layer includes:

5. The circuit board of claim 4, wherein, a first region in contact with the first circuit pattern; a second region in contact with the third metal layer; and a third region in contact with the fourth metal layer. the first circuit pattern is buried in a lower region of the insulating layer.

6. The circuit board of claim 1, wherein, the lower surface of the first circuit pattern is on a same plane as a lower surface of the insulating layer, and 7. The circuit board of claim 6, wherein, wherein the first portion of the first barrier layer protrudes downward from the lower surface of the insulating layer. 8.The circuit board of claim 1, further comprising: a second circuit pattern disposed on the insulating layer; a second barrier layer surrounding an upper surface, a lower surface, and a side surface of the second circuit pattern and disposed on the insulating layer; and a second protective layer disposed on the second barrier layer. the second barrier layer includes: a third portion disposed between an upper surface of the insulating layer and the lower surface of the second circuit pattern; and 9. The circuit board of claim 8, wherein, a fourth portion disposed on the third portion to surround the upper surface and the side surface of the second circuit pattern. the third portion of the second barrier layer includes: a fifth metal layer disposed on the insulating layer; 10. The circuit board of claim 9, wherein, a sixth metal layer disposed on the fifth metal layer and including a different metal material from the fifth metal layer, and wherein the second circuit pattern is disposed on the sixth metal layer. the fifth metal layer includes palladium, and wherein the sixth metal layer includes gold.

11. The circuit board of claim 10, wherein, the fourth portion of the second barrier layer includes: ​ 12. The circuit board of claim 10, wherein, ​ a seventh metal layer disposed to surround the upper surface and the side surface of the second circuit pattern and including the same metal material as the sixth metal layer; and an eighth metal layer disposed to surround the seventh metal layer and including the same metal material as the fifth metal layer.

13. The circuit board of claim 12, wherein, Each of the upper surface, the side surface, and the lower surface of the second circuit pattern is not in contact with the insulating layer and the second protective layer.

14. The circuit board of claim 12, wherein, A width of the sixth metal layer is greater than a width of the second circuit pattern.

15. The circuit board of claim 14, wherein, An upper surface of the sixth metal layer includes: a first region in contact with the lower surface of the second circuit pattern; a second region in contact with the seventh metal layer; and a third region in contact with the eighth metal layer.

16. The circuit board of claim 15, wherein, The lower surface of the second circuit pattern is located at a higher position than an upper surface of the insulating layer and a lower surface of the second protective layer.

17. The circuit board of claim 1, wherein, The first protective layer includes a first opening overlapping at least a portion of the first portion of the first barrier layer in a vertical direction.

18. The circuit board of claim 9, wherein, The second protective layer includes a second opening overlapping at least a portion of the fourth portion of the second barrier layer in a vertical direction.

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