Data Transmission Method, Apparatus, Device and Storage Medium for Multi-Bit Signals

Abstract

The present invention provides a data transmission method for multi-bit signals, which is applied to the field of communication technology. For each single-bit signal of the multi-bit signal, the method includes converting the single-bit signal into a state signal of a first state machine, performing one-hot encoding on the state signal of the first state machine to obtain a one-hot encoded signal of the first state machine, and transmitting the one-hot encoded signal of the first state machine across clocks to a second state machine. The present invention also provides a data transmission device, an electronic device, and a storage medium for multi-bit signals, which ensure the stability of the cross-clock signal, and at the same time ensure that only one bit is valid when multiple cross-clock signals change simultaneously, avoiding the occurrence of errors in the aggregation of multiple cross-clock signals at the same logic gate.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to a data transmission method, apparatus, device, and storage medium for multi-bit signals. Background Art

[0002] In the design of communication interfaces, most of the parts involving cross-clock data transfer use asynchronous FIFOs. An asynchronous FIFO has a structure of Gray code plus dual-port RAM and can meet the cross-clock data transfer. When there is data verification in the interface design and the data transfer is controlled according to the verification result of the data, using an asynchronous FIFO in this case will make the design complex. In addition, it is difficult for an asynchronous FIFO to meet the scenario where the asynchronous clock frequencies differ greatly.

[0003] Storing data in a dual-port RAM and using a state control signal for cross-clock domain transfer to replace the Gray code can avoid the defects of using an asynchronous FIFO. The state control signal uses a handshake method for cross-clock transfer, but the traditional handshake protocol is only suitable for the transfer of single-bit state control signals. When a multi-bit signal uses the traditional handshake protocol for cross-clock transfer, if each bit of data is handshake separately, when there are multi-bit synchronous signals in the design that pass through synchronizers and then pass through different numbers of registers and finally converge at the same logic gate, it will lead to an incorrect state. Summary of the Invention

[0004] The main objective of the present invention is to provide a data transmission method, apparatus, device, and storage medium for multi-bit signals, aiming to solve the technical problem that errors are likely to occur in the existing multi-bit signal transmission.

[0005] To achieve the above objective, in a first aspect of an embodiment of the present invention, a data transmission method for multi-bit signals is provided. For each single-bit signal of the multi-bit signals, the method includes:

[0006] Converting the single-bit signal into a state signal of a first state machine;

[0007] Performing one-hot encoding on the state signal of the first state machine to obtain a one-hot encoded signal of the first state machine;

[0008] Transmitting the one-hot encoded signal of the first state machine across a clock domain to a second state machine.

[0009] In an embodiment of the present disclosure, after transmitting the one-hot encoded signal of the first state machine across a clock domain to the second state machine, the method further includes:

[0010] Determining the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine;

[0011] Transfer the one-hot encoded signal of the second state machine across clocks to the first state machine;

[0012] Switch the state signal of the first state machine to the single-bit signal transmission completion state.

[0013] In an embodiment of the present disclosure, the conversion of the single-bit signal into the state signal of the first state machine includes:

[0014] Obtain the valid state of the single-bit signal;

[0015] When the valid state of the single-bit signal is correct, switch the state signal of the first state machine to the single-bit signal sending state;

[0016] The one-hot encoding of the state signal of the first state machine to obtain the one-hot encoded signal of the first state machine includes:

[0017] Perform one-hot encoding on the single-bit signal sending state of the first state machine to obtain the one-hot encoded signal of the first state machine.

[0018] In an embodiment of the present disclosure, before determining the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine, it further includes:

[0019] Judge whether the received one-hot encoded signal of the first state machine is correct;

[0020] When the received one-hot encoded signal of the first state machine is correct, perform the operation of determining the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine.

[0021] In an embodiment of the present disclosure, the determination of the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine includes:

[0022] Switch the state signal of the second state machine to the single-bit signal receiving state;

[0023] Perform one-hot encoding on the single-bit signal receiving state of the second state machine to obtain the one-hot encoded signal of the second state machine.

[0024] In an embodiment of the present disclosure, after transferring the one-hot encoded signal of the second state machine across clocks to the first state machine, it further includes:

[0025] Judge whether the one-hot encoded signal of the second state machine is correct;

[0026] When the one-hot encoded signal of the second state machine is correct, perform an operation to switch the state signal of the first state machine to the single-bit signal transmission completion state.

[0027] In an embodiment of the present disclosure, determining whether the received one-hot encoded signal of the first state machine is correct includes:

[0028] Determine whether the received one-hot encoded signal of the first state machine has only one high-level signal;

[0029] Determining whether the one-hot encoded signal of the second state machine is correct includes:

[0030] Determine whether the one-hot encoded signal of the second state machine has only one high-level signal.

[0031] A second aspect of an embodiment of the present invention provides a data transmission device for multi-bit signals, where the multi-bit signals include a plurality of single-bit signals, and the device includes:

[0032] A conversion module for converting a single-bit signal into a state signal of a first state machine;

[0033] A first one-hot encoding module for performing one-hot encoding on the state signal of the first state machine to obtain the one-hot encoded signal of the first state machine;

[0034] A first transfer module for transferring the one-hot encoded signal of the first state machine across clocks to a second state machine.

[0035] In an embodiment of the present disclosure, the data transmission device further includes:

[0036] A second one-hot encoding module for determining the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine;

[0037] A second transfer module for transferring the one-hot encoded signal of the second state machine across clocks to the first state machine;

[0038] A switching module for switching the state signal of the first state machine to the single-bit signal transmission completion state.

[0039] In an embodiment of the present disclosure, the conversion module includes:

[0040] An acquisition sub-module for acquiring the valid state of the single-bit signal;

[0041] A switching sub-module for switching the state signal of the first state machine to the single-bit signal transmission state when the valid state of the single-bit signal is correct;

[0042] The first one-hot encoding module is specifically configured to perform one-hot encoding on the single-bit signal transmission state of the first state machine to obtain the one-hot encoding signal of the first state machine.

[0043] In an embodiment of the present disclosure, the data transmission device further includes:

[0044] A judgment module, configured to judge whether the received one-hot encoding signal of the first state machine is correct;

[0045] When the received one-hot encoding signal of the first state machine is correct, the second one-hot encoding module is executed.

[0046] In an embodiment of the present disclosure, the second one-hot encoding module includes:

[0047] A second switching sub-module, configured to switch the state signal of the second state machine to a single-bit signal receiving state;

[0048] An one-hot encoding sub-module, configured to perform one-hot encoding on the single-bit signal receiving state of the second state machine to obtain the one-hot encoding signal of the second state machine.

[0049] In an embodiment of the present disclosure, the second one-hot encoding module further includes:

[0050] A judgment sub-module, configured to judge whether the one-hot encoding signal of the second state machine is correct;

[0051] When the one-hot encoding signal of the second state machine is correct, the switching module is executed.

[0052] In an embodiment of the present disclosure, the judgment module is specifically configured to judge whether there is only one high-level signal in the received one-hot encoding signal of the first state machine;

[0053] The judgment sub-module is specifically configured to judge whether there is only one high-level signal in the one-hot encoding signal of the second state machine.

[0054] A third aspect of the embodiments of the present invention provides an electronic device, including:

[0055] One or more processors;

[0056] A storage device, configured to store one or more programs,

[0057] Wherein, when the one or more programs are executed by the one or more processors, the one or more processors are caused to execute the data transmission for multi-bit signals provided in the first aspect of the embodiments of the present invention.

[0058] A fourth aspect of an embodiment of the present invention provides a computer-readable storage medium, on which executable instructions are stored. When the instructions are executed by a processor, the processor executes the data transmission for multi-bit signals provided in the first aspect of the embodiment of the present invention.

[0059] As can be seen from the above embodiments of the present invention, the data transmission method, apparatus, electronic device and storage medium provided by the present invention for multi-bit signals, and the data transmission method for multi-bit signals. For each single-bit signal of the multi-bit signal, the method includes converting the single-bit signal into a state signal of a first state machine, performing one-hot encoding on the state signal of the first state machine to obtain a one-hot encoded signal of the first state machine, and transmitting the one-hot encoded signal of the first state machine across clocks to a second state machine. Using two state machines to complete the cross-clock transmission of multi-bit signals not only ensures the stability of the cross-clock signals, but also ensures that only one bit is valid when multiple cross-clock signals change simultaneously. The one-hot code method is used to avoid the error of multiple cross-clock signals aggregating in the same logic gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0061] Figure 1 Schematically shows a flowchart of a data transmission method for multi-bit signals according to an embodiment of the present invention;

[0062] Figure 2 Schematically shows a flowchart of a data transmission method for multi-bit signals according to an embodiment of the present invention;

[0063] Figure 3 Schematically shows a state transition diagram of a first state machine according to an embodiment of the present invention;

[0064] Figure 4 Schematically shows a state transition diagram of a second state machine according to an embodiment of the present invention;

[0065] Figure 5 Schematically shows a cross-clock handshake diagram of a first state machine and a second state machine according to an embodiment of the present invention;

[0066] Figure 6 Schematically shows a structural block diagram of a data transmission apparatus for multi-bit signals according to an embodiment of the present disclosure;

[0067] Figure 7A block diagram of an electronic device for a data transmission method for a multi-bit signal according to an embodiment of the present invention is schematically shown. Detailed implementation manners

[0068] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present invention. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0069] The terms used herein are merely for describing specific embodiments and are not intended to limit the present invention. The terms "including", "comprising", etc. used herein indicate the presence of the feature, step, operation, and / or component, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0070] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0071] In the case of using expressions such as "at least one of A, B, and C", generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include, but is not limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C).

[0072] Embodiments of the present invention provide a data transmission method for a multi-bit signal. For each single-bit signal of the multi-bit signal, the method includes converting the single-bit signal into a state signal of a first state machine, performing one-hot encoding on the state signal of the first state machine to obtain a one-hot encoded signal of the first state machine, and transmitting the one-hot encoded signal of the first state machine across a clock to a second state machine. Using two state machines to complete the multi-bit signal cross-clock transmission not only ensures the stability of the cross-clock signal, but also ensures that only one bit is valid when multiple cross-clock signals change simultaneously. The one-hot code method is used to avoid the error of multiple cross-clock signals aggregating at the same logic gate.

[0073] Figure 1 A flowchart of a data transmission method for a multi-bit signal according to an embodiment of the present invention is schematically shown.

[0074] As Figure 1 shown, for each single-bit signal of the multi-bit signal, the data transmission method for the multi-bit signal includes operation S101 to operation S103.

[0075] In operation S101, convert the single-bit signal into a state signal of a first state machine.

[0076] In operation S102, perform one-hot encoding on the state signal of the first state machine to obtain a one-hot encoded signal of the first state machine.

[0077] In operation S103, transfer the one-hot encoded signal of the first state machine across clocks to a second state machine.

[0078] In an embodiment of the present disclosure, operation S101 converting the single-bit signal into a state signal of the first state machine includes: obtaining the valid state of the single-bit signal, and when the valid state of the single-bit signal is correct, switching the state signal of the first state machine to the single-bit signal transmission state.

[0079] In an example, the multi-bit data to be transmitted includes data0, data1, data2, and data3. Correspondingly, the multi-bit signal includes four single-bit signals: data0_valid_aclk, data1_valid_aclk, data2_valid_aclk, and data3_valid_clk. The first state machine sync_fsm_aclk operates in the A clock domain, and the second state machine sync_fsm_bclk operates in the B clock domain. As Figure 2 shown, the four single-bit signals data0_valid_aclk, data1_valid_aclk, data2_valid_aclk, and data3_valid_clk represent the signals to be transferred across clocks from the A clock domain to the B clock domain. After the state machine starts working, the first state machine sync_fsm_aclk in the A clock domain works in the idle state idle_aclk, and the second state sync_fsm_bclk in the B clock domain works in the idle state idle_bclk.

[0080] In the present disclosure, taking the transfer of the single-bit signal data0_valid_aclk across clock domains as an example, when it is checked that the valid state of the single-bit signal data0_valid_aclk is correct, the first state machine sync_fsm_aclk switches to the single-bit signal transmission state data0_s_aclk, that is, data0 is transmitted.

[0081] Understandably, if the first state machine sync_fsm_aclk is in the idle state idle_aclk, and if the single-bit signal data0_valid_aclk is detected to be valid, the first state machine sync_fsm_aclk switches from the idle state idle_aclk to the single-bit signal transmission state data0_s_aclk.

[0082] In an embodiment of the present disclosure, operation S102 performs one-hot encoding on the state signal of the first state machine to obtain the one-hot encoded signal of the first state machine, including: performing one-hot encoding on the single-bit signal transmission state of the first state machine to obtain the one-hot encoded signal of the first state machine.

[0083] Continuing to refer to the above example, the first state machine sync_fsm_aclk performs one-hot encoding on the single-bit signal transmission state data0_s_aclk to generate the one-hot encoded signal load_data_aclk of the first state machine with only one bit at a high level. Since the one-hot code of the single-bit signal transmission state data0_s_aclk is 0001, the corresponding one-hot encoded signal load_data_aclk of the first state machine is also 0001.

[0084] Thereafter, the one-hot encoded signal load_data_aclk of the first state machine is transmitted from the current A clock domain to the second state machine sync_fsm_bclk in the B clock domain.

[0085] According to the embodiments of the present disclosure, the single-bit signal is converted into the state signal of the first state machine, the state signal of the first state machine is one-hot encoded to obtain the one-hot encoded signal of the first state machine, and the one-hot encoded signal of the first state machine is transmitted across the clock to the second state machine. Using two state machines to complete the multi-bit signal cross-clock transmission not only ensures the stability of the cross-clock signal, but also ensures that only one bit is valid when multiple cross-clock signals change simultaneously. The one-hot code method is used to avoid the error of multiple cross-clock signals aggregating in the same logic gate.

[0086] Figure 2 Schematically shows a flowchart of a data transmission method for multi-bit signals according to an embodiment of the present invention. Figure 3 Schematically shows a state transition diagram of a first state machine according to an embodiment of the present invention. Figure 4 Schematically shows a state transition diagram of a second state machine according to an embodiment of the present invention. Figure 5 Schematically shows a cross-clock handshake diagram of a first state machine and a second state machine according to an embodiment of the present invention.

[0087] As Figure 2As shown, for each single-bit signal of the multi-bit signal, the data transmission method for the multi-bit signal includes operations S201 to S206.

[0088] In operation S201, convert the single-bit signal into a state signal of the first state machine.

[0089] In operation S202, perform one-hot encoding on the state signal of the first state machine to obtain the one-hot encoded signal of the first state machine.

[0090] In operation S203, transfer the one-hot encoded signal of the first state machine across clocks to the second state machine.

[0091] In operation S204, determine the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine.

[0092] In operation S205, transfer the one-hot encoded signal of the second state machine across clocks to the first state machine.

[0093] In operation S206, switch the state signal of the first state machine to the single-bit signal transmission completion state.

[0094] The above operations S201 to S203 are the same as operations S101 to S103 shown above. For specific details, please refer to Figure 1 the description, which will not be elaborated here. Figure 1 In an embodiment of the present disclosure, before operation S204 determines the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine,

[0095] the method shown further includes: determining whether the received one-hot encoded signal of the first state machine is correct. If the received one-hot encoded signal of the first state machine is correct, perform operation S204 to determine the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine. Figure 2 Continuing to refer to the example shown, the one-hot encoded signal load_data_aclk of the first state machine in the A clock domain is transferred to the B clock domain through a cross-clock synchronizer. The received one-hot encoded signal load_data_bclk of the first state machine transferred across the clock domain is determined. If the received one-hot encoded signal load_data_bclk of the first state machine in the B clock domain is correct, perform operation S204 to determine the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine.

[0096] Continue to refer to Figure 1 the example shown. The one-hot encoded signal load_data_aclk of the first state machine in the A clock domain is transferred to the B clock domain through a cross-clock synchronizer. The received one-hot encoded signal load_data_bclk of the first state machine transferred across the clock domain is determined. If the received one-hot encoded signal load_data_bclk of the first state machine in the B clock domain is correct, perform operation S204 to determine the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine.

[0097] It is understandable that, when the one-hot encoded signal of the first state machine received is incorrect, the operation of determining the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine is not performed, and the state of the second state machine remains unchanged.

[0098] In an embodiment of the present disclosure, determining whether the received one-hot encoded signal of the first state machine is correct includes: determining whether there is only one high-level signal in the received one-hot encoded signal of the first state machine. For example, if the one-hot encoded signal load_data_bclk of the first state machine received in the B clock domain is 0001, then the one-hot encoded signal load_dara_bclk of the first state machine received in the B clock domain is correct, indicating that the single-bit signal data0_valid_aclk in the A clock domain has been successfully transferred across the clock to the B clock domain. Another example, if the one-hot encoded signal load_data_bclk of the first state machine received in the B clock domain is 0011 or 0111, etc., then the one-hot encoded signal load_data_bclk of the first state machine received in the B clock domain is incorrect, indicating that the single-bit signal data0_valid_aclk in the A clock domain has not been successfully transferred across the clock to the B clock domain.

[0099] In an embodiment of the present disclosure, operation S204 determining the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine includes: switching the state signal of the second state machine to the single-bit signal receiving state, and performing one-hot encoding on the single-bit signal receiving state of the second state machine to obtain the one-hot encoded signal of the second state machine.

[0100] Continuing with the above example, switch the second state machine sync_fsm_bclk to the single-bit signal receiving state data0_s_blck, indicating that 1-bit data has been transferred from the A clock domain to the B clock domain. At the same time, perform one-hot encoding on the single-bit signal receiving state data0_s_blck of the second state machine in the B clock domain to generate the one-hot encoded signal data_ready_bclk of the second state machine with only one bit of high level. Since the one-hot code corresponding to data0_s_blck is 0001, the corresponding one-hot encoded signal data_ready_bclk of the second state machine is also 0001. The one-hot encoded signal data_ready_bclk of the second state machine is the READY signal sent to the A clock domain, indicating the signal that the data transfer across the clock is completed. The one-hot encoded signal data_ready_bclk of the second state machine in the B clock domain is transferred to the A clock domain through a cross-clock synchronizer (sync).

[0101] In an embodiment of the present disclosure, after operation S205 transfers the one-hot encoded signal of the second state machine across the clock to the first state machine,Figure 2 The method further includes: determining whether the one-hot encoded signal of the second state machine is correct, and when the one-hot encoded signal of the second state machine is correct, performing operation S206 to switch the state signal of the first state machine to the single-bit signal transmission completion state.

[0102] Continuing to refer to the above example, the A clock domain receives the one-hot encoded signal data_ready_aclk of the second state machine in the B clock domain for cross-clock transmission, and performs one-hot logic determination. When it is determined that data_ready_aclk is 0001, that is, the one-hot encoded signal data_ready_aclk of the second state machine is correct, then the state signal of the first state machine is switched to the single-bit signal transmission completion state data0_ready_aclk, and data0_ready_aclk will be 1, indicating that the single-bit signal data0_valid_aclk has successfully been transmitted across the clock to the B clock domain. Next, other single-bit signals can be transmitted across the clock.

[0103] In an embodiment of the present disclosure, determining whether the one-hot encoded signal of the second state machine is correct includes determining whether there is only one high-level signal in the one-hot encoded signal of the second state machine. For example, if the one-hot encoded signal data_ready_aclk of the second state machine received by the A clock domain is 0001, then the one-hot encoded signal data_ready_aclk of the second state machine received by the A clock domain is correct, indicating that the single-bit signal transmission completion state data0_ready_aclk in the B clock domain has been transmitted across the clock to the A clock domain. Another example is that if the one-hot encoded signal data_ready_aclk of the second state machine received by the A clock domain is 0011 or 0111, etc., then the one-hot encoded signal data_ready_aclk of the second state machine received by the A clock domain is incorrect, indicating that the single-bit signal transmission completion state data0_ready_aclk in the B clock domain has not been successfully transmitted across the clock to the A clock domain, and at this time, the next single-bit data signal is not transmitted continuously.

[0104] In the present disclosure, when the single-bit signal data0_valid_aclk in the A clock domain is valid, after the first state machine sync_fsm_aclk switches to the single-bit signal transmission state data0_s_aclk, it will remain in this state until it switches to the single-bit signal transmission completion state data0_ready_aclk, indicating that the data data0, that is, the single-bit signal data0_valid_aclk, has completed cross-clock transfer. According to the embodiments of the present disclosure, by analogy, thereafter, when the single-bit signal data1_valid_aclk is in a valid state correctly, the first state machine sync_fsm_aclk switches to the single-bit signal transmission state data1_s_aclk to perform cross-clock transfer on the single-bit signal data1_valid_aclk. If the single-bit signal data2_valid_aclk is in a valid state correctly, the first state machine sync_fsm_aclk switches to the single-bit signal transmission state data2_s_aclk. If the single-bit signal data3_valid_aclk is in a valid state correctly, the first state machine sync_fsm_aclk switches to the single-bit signal transmission state data3_s_aclk. If there is no valid signal to be transferred, or the valid states of all single-bit signals are incorrect, the first state machine switches to the idle state idle_aclk.

[0105] According to the embodiments of the present disclosure, the jump condition of the state machine is set by the valid state of the current single-bit signal and the cross-clock completion signal of the previous bit to perform the jump of the state machine. The states of the state machine are first one-hot encoded and then the one-hot codes are transferred across clocks. After the one-hot codes are cross-clock synchronized, one-hot code logical judgment is performed. In this way, even if multi-bit cross-clock signals pass through synchronizers and then pass through different numbers of registers and finally converge at the same logic gate, the error signals will be masked.

[0106] Based on the data transmission method for multi-bit signals, the present disclosure also provides a data transmission device for multi-bit signals. The following will be combined with Figure 6 to describe this device in detail.

[0107] Figure 6 Schematically shows a structural block diagram of a data transmission device for multi-bit signals according to an embodiment of the present disclosure.

[0108] As Figure 6 shown, the data transmission device 600 for multi-bit signals in this embodiment includes a conversion module 610, a first one-hot encoding module 620, and a first transfer module 630.

[0109] The conversion module 610 is used to convert the single-bit signal into the state signal of the first state machine. In one embodiment, the conversion module 610 can be used to perform the operation S101 described above, which will not be elaborated here.

[0110] The first one-hot encoding module 620 is used to perform one-hot encoding on the state signal of the first state machine to obtain the one-hot encoding signal of the first state machine. In one embodiment, the first one-hot encoding module 620 can be used to perform the operation S102 described above, which will not be elaborated here.

[0111] The first transfer module 630 is used to transfer the one-hot encoding signal of the first state machine across clocks to the second state machine. In one embodiment, the first transfer module 630 can be used to perform the operation S103 described above, which will not be elaborated here.

[0112] In one embodiment of the present disclosure, the data transmission device 600 further includes:

[0113] The second one-hot encoding module is used to determine the one-hot encoding signal of the second state machine based on the one-hot encoding signal of the first state machine. In one embodiment, the second one-hot encoding module can be used to perform the operation S204 described above, which will not be elaborated here.

[0114] The second transfer module is used to transfer the one-hot encoding signal of the second state machine across clocks to the first state machine. In one embodiment, the second transfer module can be used to perform the operation S205 described above, which will not be elaborated here.

[0115] The switching module is used to switch the state signal of the first state machine to the single-bit signal transmission completion state. In one embodiment, the switching module can be used to perform the operation S206 described above, which will not be elaborated here.

[0116] In one embodiment of the present disclosure, the conversion module 610 includes:

[0117] The acquisition sub-module is used to acquire the valid state of the single-bit signal;

[0118] The switching sub-module is used to switch the state signal of the first state machine to the single-bit signal sending state when the valid state of the single-bit signal is correct;

[0119] The first one-hot encoding module 620 is specifically used to perform one-hot encoding on the single-bit signal sending state of the first state machine to obtain the one-hot encoding signal of the first state machine.

[0120] In one embodiment of the present disclosure, the data transmission device 600 further includes:

[0121] A judgment module, configured to judge whether the one-hot encoded signal of the received first state machine is correct;

[0122] When the one-hot encoded signal of the received first state machine is correct, execute the second one-hot encoding module.

[0123] In an embodiment of the present disclosure, the second one-hot encoding module includes:

[0124] A second switching sub-module, configured to switch the state signal of the second state machine to a single-bit signal receiving state;

[0125] A one-hot encoding sub-module, configured to perform one-hot encoding on the single-bit signal receiving state of the second state machine to obtain the one-hot encoded signal of the second state machine.

[0126] In an embodiment of the present disclosure, the second one-hot encoding module further includes:

[0127] A judgment sub-module, configured to judge whether the one-hot encoded signal of the second state machine is correct;

[0128] When the one-hot encoded signal of the second state machine is correct, execute the switching module.

[0129] In an embodiment of the present disclosure, the judgment module is specifically configured to judge whether there is only one high-level signal in the one-hot encoded signal of the received first state machine;

[0130] The judgment sub-module is specifically configured to judge whether there is only one high-level signal in the one-hot encoded signal of the second state machine.

[0131] According to an embodiment of the present invention, any plurality of modules among the conversion module 610, the first one-hot encoding module 620, and the first transfer module 630 may be combined and implemented in one module, or any one of them may be split into multiple modules. Alternatively, at least part of the functions of one or more of these modules may be combined with at least part of the functions of other modules and implemented in one module. According to an embodiment of the present invention, at least one of the conversion module 610, the first one-hot encoding module 620, and the first transfer module 630 may be at least partially implemented as a hardware circuit, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or any other reasonable manner that can integrate or package circuits, etc., implemented by hardware or firmware, or implemented in any one of the three implementation manners of software, hardware, and firmware, or in an appropriate combination of any several of them. Alternatively, at least one of the conversion module 610, the first one-hot encoding module 620, and the first transfer module 630 may be at least partially implemented as a computer program module, and when the computer program module is run, the corresponding functions may be executed.

[0132] Figure 7 A block diagram of an electronic device for a multi-bit signal data transmission method according to an embodiment of the present invention is schematically shown.

[0133] As Figure 7 shown, the electronic device 700 according to an embodiment of the present invention includes a processor 701, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage section 708 into a random access memory (RAM) 703. The processor 701 may include, for example, a general-purpose microprocessor (such as a CPU), an instruction set processor, and / or a related chipset, and / or a dedicated microprocessor (such as an application-specific integrated circuit (ASIC)), etc. The processor 701 may also include on-board memory for caching purposes. The processor 701 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0134] In the RAM 703, various programs and data required for the operation of the electronic device 700 are stored. The processor 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. The processor 701 performs various operations of the method flow according to the embodiments of the present invention by executing the programs in the ROM 702 and / or the RAM 703. It should be noted that the programs may also be stored in one or more memories other than the ROM 702 and the RAM 703. The processor 701 may also perform various operations of the method flow according to the embodiments of the present invention by executing the programs stored in the one or more memories.

[0135] According to an embodiment of the present invention, the electronic device 700 may further include an input / output (I / O) interface 705, and the input / output (I / O) interface 705 is also connected to the bus 704. The electronic device 700 may further include one or more of the following components connected to the I / O interface 705: an input portion 706 including a keyboard, a mouse, etc.; an output portion 707 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc. and a speaker, etc.; a storage portion 708 including a hard disk, etc.; and a communication portion 709 including a network interface card such as a LAN card, a modem, etc. The communication portion 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 705 as needed. A removable medium 711, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 710 as needed so that a computer program read from it can be installed into the storage portion 708 as needed.

[0136] The present invention also provides a computer-readable storage medium, which may be included in the device / device / system described in the above embodiments; or may exist separately without being assembled into the device / device / system. The above computer-readable storage medium carries one or more programs, and when the one or more programs are executed, the method according to the embodiments of the present invention is implemented.

[0137] According to an embodiment of the present invention, the computer-readable storage medium may be a non-volatile computer-readable storage medium, for example, it may include but is not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In the present invention, the computer-readable storage medium may be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present invention, the computer-readable storage medium may include the above-described ROM 702 and / or RAM 703 and / or one or more memories other than ROM 702 and RAM 703.

[0138] An embodiment of the present invention also includes a computer program product, which includes a computer program that contains program code for executing the method shown in the flowchart. When the computer program product runs in a computer system, the program code is used to enable the computer system to implement the item recommendation method provided by the embodiment of the present invention.

[0139] When the computer program is executed by the processor 701, it executes the above functions defined in the system / apparatus of the embodiment of the present invention. According to an embodiment of the present invention, the above-described systems, apparatuses, modules, units, etc. can be implemented by computer program modules.

[0140] In one embodiment, the computer program can rely on tangible storage media such as optical storage devices and magnetic storage devices. In another embodiment, the computer program can also be transmitted and distributed in the form of a signal on a network medium, and be downloaded and installed through the communication part 709, and / or be installed from the removable medium 711. The program code contained in the computer program can be transmitted by any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0141] In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 709, and / or be installed from the removable medium 711. When the computer program is executed by the processor 701, it executes the above functions defined in the system of the embodiment of the present invention. According to an embodiment of the present invention, the above-described systems, devices, apparatuses, modules, units, etc. can be implemented by computer program modules.

[0142] According to embodiments of the present invention, program code for executing the computer programs provided by the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computing programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. The programming languages include, but are not limited to, such as Java, C++, Python, the "C" language, or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device can be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (e.g., by connecting through the Internet using an Internet service provider).

[0143] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a portion of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and combinations of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0144] Those skilled in the art can understand that the features recited in the various embodiments and / or claims of the present invention can be combined or / and combined in various ways, even if such combinations or combinations are not explicitly recited in the present invention. In particular, without departing from the spirit and teachings of the present invention, the features recited in the various embodiments and / or claims of the present invention can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present invention.

[0145] The embodiments of the present invention have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present invention.

Claims

1. A data transmission method for multi-bit signals, characterized in that, for each single-bit signal of the multi-bit signal, the method includes: converting the single-bit signal into a state signal of a first state machine; performing one-hot encoding on the state signal of the first state machine to obtain a one-hot encoded signal of the first state machine; transmitting the one-hot encoded signal of the first state machine across a clock to a second state machine, where the second state machine is configured to keep its current state unchanged when the received one-hot encoded signal does not meet the single high-level condition; determining the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine; transmitting the one-hot encoded signal of the second state machine across a clock to the first state machine; wherein, the converting the single-bit signal into a state signal of a first state machine includes: obtaining the valid state of the single-bit signal; when the valid state of the single-bit signal is correct, switching the state signal of the first state machine to the single-bit signal transmission state.

2. The data transmission method according to claim 1, characterized in that, after transmitting the one-hot encoded signal of the first state machine across a clock to the second state machine, it further includes: switching the state signal of the first state machine to the single-bit signal transmission completion state.

3. The data transmission method according to claim 1, characterized in that, the performing one-hot encoding on the state signal of the first state machine to obtain a one-hot encoded signal of the first state machine includes: performing one-hot encoding on the single-bit signal transmission state of the first state machine to obtain a one-hot encoded signal of the first state machine.

4. The data transmission method according to claim 2, characterized in that, before determining the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine, it further includes: judging whether the received one-hot encoded signal of the first state machine is correct; when the received one-hot encoded signal of the first state machine is correct, performing the operation of determining the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine.

5. The data transmission method according to claim 2 or 3, characterized in that, the determining the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine includes: switching the state signal of the second state machine to the single-bit signal reception state; performing one-hot encoding on the single-bit signal reception state of the second state machine to obtain a one-hot encoded signal of the second state machine.

6. The data transmission method according to claim 3, characterized in that, after transmitting the one-hot encoded signal of the second state machine across a clock to the first state machine, it further includes: judging whether the one-hot encoded signal of the second state machine is correct; when the one-hot encoded signal of the second state machine is correct, performing the operation of switching the state signal of the first state machine to the single-bit signal transmission completion state.

7. The data transmission method according to claim 6, characterized in that, Determining whether the one-hot encoded signal of the received first state machine is correct includes: Determining whether there is only one high-level signal in the received one-hot encoded signal of the first state machine; Determining whether the one-hot encoded signal of the second state machine is correct includes: Determining whether there is only one high-level signal in the one-hot encoded signal of the second state machine.

8. A data transmission device for multi-bit signals, characterized in that the multi-bit signal includes a plurality of single-bit signals, and the device includes: a conversion module for converting the single-bit signal into a state signal of a first state machine; a first one-hot encoding module for performing one-hot encoding on the state signal of the first state machine to obtain the one-hot encoded signal of the first state machine; a first transfer module for transferring the one-hot encoded signal of the first state machine across clocks to a second state machine, and the second state machine is configured to keep the current state unchanged when the received one-hot encoded signal does not meet the single high-level condition; a second one-hot encoding module for determining the one-hot encoded signal of the second state machine based on the one-hot encoded signal of the first state machine; a second transfer module for transferring the one-hot encoded signal of the second state machine across clocks to the first state machine; wherein, converting the single-bit signal into the state signal of the first state machine includes: obtaining the valid state of the single-bit signal; when the valid state of the single-bit signal is correct, switching the state signal of the first state machine to the single-bit signal transmission state.

9. An electronic device, including: one or more processors; a storage device for storing one or more programs, wherein, when the one or more programs are executed by the one or more processors, the one or more processors are caused to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, on which executable instructions are stored, and when the instructions are executed by a processor, the processor is caused to execute the method according to any one of claims 1 to 7.

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