A three-dimensional integrated circuit stacking structure and a preparation method thereof

Abstract

The present application provides a three-dimensional integrated circuit stacking structure and a manufacturing method thereof. The manufacturing method includes: providing a plurality of wafer packages, the plurality of crystal packages are arranged opposite to each other through electrodes on the same side to form a stacked structure in which two are connected to each other. Between two adjacent wafer packages in the stacked structure, temporary bonding is performed through a passivation layer, so that the electrodes on the same side of the two adjacent wafer packages are aligned with each other; heating and decomposing the passivation layer to permanently bond the wafer packages in the stacked structure, so that signal paths penetrating the stacked structure are formed between the wafer packages in the stacked structure through their respective electrodes, and the production of the device stacking structure is completed. The present application can effectively simplify the production process to improve production efficiency and reduce production costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated applications, and particularly to a three-dimensional integrated circuit stacking structure and a manufacturing method thereof. Background Art

[0002] With the overall development of semiconductor technology, the research hotspots of various companies, institutions and universities have gradually focused on how to increase the number of components per unit area and improve the microscopic precision. The traditional 2D planar integration process has reached the density limit. In order to improve chip performance and integrate more transistors, three-dimensional stacking technology has emerged.

[0003] Three-dimensional integrated circuits are an extension of traditional two-dimensional integrated circuits from planar integration to vertical three-dimensional integration. The advantages of three-dimensional integrated circuits are as follows: The multi-layer device overlapping structure doubles the chip integration density; The through-silicon via structure greatly improves the transmission speed of electrical signals; The multi-layer stacking structure makes it possible to process parallel signals; A variety of integrated circuit design processes diversify the circuit functions.

[0004] Currently, the mainstream three-dimensional stacking manufacturing process adopts the wafer-level bonding method. First, the target device wafer is thinned, and the device wafer is temporarily bonded to the carrier wafer with an intermediate material by using temporary bonding. After processes such as back thinning, backside wiring, and microbump fabrication are completed, the device wafer is separated from the carrier wafer by using a debonding process. The thinned device wafer is permanently bonded multiple times, and then the three-dimensional stacking is completed. In the microbump fabrication process, there is usually a time interval from the preparation of the clean microbump surface to bonding. The surface of the microbump is easily oxidized during this storage time, resulting in a decrease in bonding quality. When the surface of the microbump is oxidized, a greater bonding pressure, a higher bonding temperature, and a longer bonding time need to be applied to break the oxide layer. However, excessive bonding pressure may reduce the performance of three-dimensional integrated circuits. Summary of the Invention

[0005] In view of the above problems existing in the prior art, the present application proposes a manufacturing method for a three-dimensional integrated circuit stacking structure, mainly solving the problems of complex bonding processes and long debonding time, which in turn affect the manufacturing efficiency.

[0006] To achieve the above and other purposes, the technical solutions adopted by the present invention are as follows. The present application provides a manufacturing method for a three-dimensional integrated circuit stacking structure, including:

[0007] Providing a plurality of wafer packages, wherein the plurality of crystal packages are relatively arranged with the same-side electrodes to form a stacked structure in which two-by-two are connected. Between two adjacent wafer packages in the stacked structure, temporary bonding is performed through a passivation layer, so that the same-side electrodes of the two adjacent wafer packages are aligned with each other;

[0008] Thermally decomposing the passivation layer permanently bonds the wafer packages in the stacked structure, enabling signal paths that penetrate the stacked structure to be formed between the wafer packages in the stacked structure through their respective electrodes, thereby completing the fabrication of the device stacked structure.

[0009] In one embodiment of the present application, the wafer package includes:

[0010] A substrate;

[0011] A microcircuit encapsulation layer disposed on one side of the substrate;

[0012] A metal interconnect layer disposed on the side of the microcircuit encapsulation layer facing away from the substrate, and a first electrode is disposed on the side of the metal connection layer facing away from the substrate;

[0013] A microbump structure disposed on the side of the substrate facing away from the microcircuit encapsulation layer, and the microbump structure and the first electrode serve as the electrodes of the wafer package;

[0014] A via for connecting the microbump structure and the first electrode of the metal interconnect layer.

[0015] In one embodiment of the present application, a plurality of wafer packages are provided, and the plurality of crystal packages are oppositely disposed through the same-side electrodes to form a stacked structure that is connected pairwise, including:

[0016] Select one wafer package as the initial package;

[0017] Coat a layer of temporary bonding adhesive on the surface of the metal interconnect layer of the initial package to form the passivation layer;

[0018] Fabricate the metal interconnect layer, microcircuit encapsulation layer, substrate, and via of another wafer package on the side of the passivation layer facing away from the metal interconnect layer of the initial package;

[0019] After thinning the substrate of the another wafer package, fabricate the corresponding microbump structure to obtain the second wafer package;

[0020] Coat a layer of temporary bonding adhesive on the surface of the microbump structure of the second wafer package to form a passivation layer, and form a new wafer package on the basis of the passivation layer, and repeat the foregoing steps to form the stacked structure.

[0021] In one embodiment of the present application, a plurality of wafer packages are provided, and the plurality of crystal packages are oppositely disposed through the same-side electrodes to form a stacked structure that is connected pairwise, including:

[0022] Select one wafer package as the initial package;

[0023] Coat a layer of temporary bonding adhesive on the surface of the micro-bump structure of the initial package to form the passivation layer;

[0024] Fabricate the micro-bump structure, substrate, and vias of another wafer package on the side of the passivation layer facing away from the micro-bump structure of the initial package;

[0025] After thinning the substrate of the other wafer package, fabricate the corresponding microcircuit package layer and metal interconnection layer to obtain the second wafer package;

[0026] Coat a layer of temporary bonding adhesive on the surface of the micro-bump structure of the second wafer package to form a passivation layer, and form a new wafer package on the basis of the passivation layer. Repeat the foregoing steps to form the stacked structure.

[0027] In an embodiment of the present application, multiple wafer packages are provided. The multiple crystal packages are arranged in a stacked structure where the same-side electrodes are oppositely arranged and are in contact with each other in pairs, including:

[0028] Select one wafer package as the initial package;

[0029] Coat a layer of temporary bonding adhesive on the surface of the micro-bump structure and the surface of the metal interconnection layer of the initial package to form the passivation layers on both sides;

[0030] Fabricate a second wafer package and a third package on both sides of the passivation layer facing away from the initial package so that the same-side electrodes of the two wafer packages connected by the passivation layer are oppositely arranged;

[0031] Form the passivation layer on the side of the second wafer package and the third package facing away from the initial package, and form a new wafer package on the basis of the passivation layer. Repeat the foregoing steps to form the stacked structure.

[0032] In an embodiment of the present application, the temporary bonding adhesive includes polypropylene (PET), polyoxymethylene (POM), polymethyl methacrylate (PMMA), polybutylene terephthalate (PBT), and polyethylene (PE).

[0033] In an embodiment of the present application, before the two adjacent wafer packages in the stacked structure are temporarily bonded through the passivation layer, it further includes:

[0034] Set a layer of antioxidant layer on the surface of the micro-bump structure of the wafer package.

[0035] The present application also provides a three-dimensional integrated circuit stacked structure, including:

[0036] Multiple wafer packages;

[0037] A passivation layer is disposed between two adjacent wafer packages so that the electrodes on the same side of the two adjacent wafer packages are relatively arranged and aligned with each other, and the multiple wafer packages form a stacked structure.

[0038] This application also provides a three-dimensional integrated circuit stacked device, including:

[0039] Multiple wafer packages, the multiple wafer packages form a stacked structure, and the electrodes on the same side of two adjacent wafer packages in the stacked structure are relatively arranged and connected, so that each wafer package forms a signal path penetrating the stacked structure through its own electrode.

[0040] As described above, a three-dimensional integrated circuit stacked structure and a preparation method thereof proposed in this application have the following beneficial effects.

[0041] A stacked structure is formed by multiple wafer packages, the adjacent wafer packages are butted through a passivation layer, and the permanent bonding of the stacked structure of multiple wafer packages is realized by heating and decomposing the passivation layer, which simplifies the bonding process, improves production efficiency, and has a simple structure and convenient operation. Description of the Drawings

[0042] Figure 1 It is a schematic flow chart of a preparation method of a three-dimensional integrated circuit stacked structure in an embodiment of this application.

[0043] Figure 2 It is a schematic structural diagram of a wafer package in an embodiment of this application.

[0044] Figure 3 It is a schematic diagram of a stacked structure formed by two wafer packages in an embodiment of this application.

[0045] Figure 4 It is a schematic diagram of a three-dimensional stacked structure in an embodiment of this application.

[0046] Figure 5 It is a schematic structural diagram of a three-dimensional integrated circuit stacked device in an embodiment of this application. Detailed Embodiments

[0047] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0048] It should be noted that the illustrations provided in the following embodiments only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0049] Please refer to Figure 1 , this application provides a method for manufacturing a three-dimensional integrated circuit stacking structure, including the following steps.

[0050] Step S100, provide a plurality of wafer packages. The plurality of crystal packages are oppositely arranged through the same-side electrodes to form a stacked structure that is connected pairwise. Between two adjacent wafer packages in the stacked structure, temporary bonding is performed through a passivation layer, so that the same-side electrodes of the two adjacent wafer packages are aligned with each other.

[0051] Please refer to Figure 2 , Figure 2 , which is a schematic structural diagram of a wafer package in an embodiment of this application. In one embodiment, more than two wafer packages can be stacked to form a stacked structure. The structure of the wafer package can include:

[0052] Substrate 02;

[0053] Microcircuit packaging layer 04, arranged on one side of the substrate;

[0054] Metal interconnect layer 05, arranged on the side of the microcircuit packaging layer 04 away from the substrate. A first electrode 06 is arranged on the side of the metal connection layer 05 away from the substrate 02;

[0055] Microbump structure 01, arranged on the side of the substrate away from the microcircuit packaging layer 04. The microbump structure 01 and the first electrode 06 serve as the electrodes of the wafer package;

[0056] Through-hole 03, used to connect the microbump structure 01 and the first electrode 06 of the metal interconnect layer 05.

[0057] Please refer to Figure 3 , Figure 3 , which is a schematic diagram of a stacked structure formed by two wafer packages in an embodiment of this application. In one embodiment, taking two wafer packages as an example, the two wafer packages can be docked through the metal interconnect layer 05, and the first electrodes 06 of the two metal interconnect layers 05 are aligned with each other in the passivation layer 10. It is also possible to relatively arrange the two microbump structures 01 in the passivation layer 10, and the microbump structures 01 of the two wafer packages are aligned with each other. Of course, the number of wafer packages used to form the stacked structure can also be three or more, and the specific quantity can be set according to actual application requirements, which is not limited here.

[0058] In one embodiment, a plurality of wafer packages are provided, wherein the plurality of wafer packages are arranged opposite to each other through electrodes on the same side to form a stacked structure connected in pairs, including:

[0059] Selecting a wafer package as an initial package;

[0060] Coating a layer of temporary bonding glue on the surface of the metal interconnection layer of the initial package to form the passivation layer;

[0061] Fabricate the metal interconnect layer, microcircuit packaging layer, substrate and through-hole of another wafer package on the side of the passivation layer away from the metal interconnect layer of the initial package;

[0062] After thinning the substrate of the other wafer package, a corresponding micro-bump structure is manufactured to obtain a second wafer package;

[0063] A layer of temporary bonding glue is coated on the surface of the micro-bump structure of the second wafer package to form a passivation layer, a new wafer package is formed on the basis of the passivation layer, and the above steps are repeated to form the stacking structure.

[0064] Specifically, taking the formation of a stacked structure of three wafer packages as an example, a wafer package structure can be pre-made as an initial package, and a stacked structure including the remaining two wafer packages can be made on the basis of the initial package. The specific process of making the initial package is a conventional means in the art, which will not be repeated here. After obtaining the initial package, a layer of temporary bonding glue can be coated on the surface of the metal interconnection layer of the initial package. The specific thickness of the temporary bonding glue can be set according to actual production requirements, which is not limited here. After the temporary bonding glue is cured, a passivation layer is obtained. A metal interconnection layer of another wafer package can be made on the surface of the passivation layer, and a microcircuit packaging layer is made on the side of the metal interconnection layer away from the initial package. The circuit structure of the microcircuit packaging layer can be set according to the specific chip structure and functional requirements, which is not limited. Further, a substrate is grown on the side of the microcircuit packaging layer away from the metal interaction layer. After the substrate is made, the substrate can be thinned so that the substrate thickness meets the wafer package size requirements. The specific thinning process is not limited here. After the thinning is completed, a micro-bump structure can be made on the thinned side to obtain a new wafer package. Furthermore, a wafer package can be made based on the micro-bump structure of the new wafer package to form a stacked structure of three wafer packages, in which the metal interconnection layers of two wafer packages are arranged relative to each other through a passivation layer, and the micro-bump structures of two wafer packages are arranged relative to each other through a passivation layer. Furthermore, based on the stacked structure formed by three wafer packages, the same method and steps as above can be used to continue stacking more wafer packages through a passivation layer.

[0065] In one embodiment, a plurality of wafer packages are provided. The plurality of crystal packages are oppositely arranged through electrodes on the same side to form a stacked structure in which two packages are connected to each other, including:

[0066] Select one wafer package as the initial package;

[0067] Coat a layer of temporary bonding glue on the surface of the microbump structure of the initial package to form the passivation layer;

[0068] On the side of the passivation layer facing away from the microbump structure of the initial package, fabricate the microbump structure, substrate, and through holes of another wafer package;

[0069] After thinning the substrate of the other wafer package, fabricate the corresponding microcircuit package layer and metal interconnection layer to obtain the second wafer package;

[0070] Coat a layer of temporary bonding glue on the surface of the microbump structure of the second wafer package to form a passivation layer, and form a new wafer package on the basis of the passivation layer. Repeat the foregoing steps to form the stacked structure.

[0071] Specifically, taking the formation of a stacked structure of three wafer packages as an example, a wafer package structure can be pre-fabricated as the initial package, and a stacked structure including the remaining two wafer packages can be fabricated on the basis of the initial package. The specific process of fabricating the initial package is a conventional means in the art and will not be elaborated here. After obtaining the initial package, a layer of temporary bonding glue can be coated on the surface of the microbump structure of the initial package. The specific thickness of the temporary bonding glue can be set according to actual production requirements and is not limited here. After the temporary bonding glue is cured, the passivation layer is obtained. The microbump structure of another wafer package can be fabricated on the surface of the passivation layer, and the substrate and through holes can be fabricated on the side of the microbump structure facing away from the initial package. After the substrate fabrication is completed, the substrate can be thinned so that the substrate thickness meets the size requirements of the wafer package. The specific thinning process is not limited here. After thinning, the microcircuit package layer and metal interconnection layer can be fabricated on the thinned side to obtain a new wafer package. Further, a wafer package can be fabricated on the basis of the metal interconnection layer of the new wafer package to form a stacked structure of three wafer packages. In this stacked structure, the metal interconnection layers of two wafer packages are oppositely arranged through the passivation layer, and the microbump structures of two wafer packages are oppositely arranged through the passivation layer. Further, on the basis of the stacked structure formed by three wafer packages, more wafer packages can be stacked through the passivation layer using the same method steps as described above.

[0072] In one embodiment, a plurality of wafer packages are provided. The plurality of crystal packages are oppositely arranged through electrodes on the same side to form a stacked structure in which two packages are connected to each other, including:

[0073] Select a wafer package as the initial package;

[0074] Coat a layer of temporary bonding adhesive on the surface of the microbump structure and the surface of the metal interconnect layer of the initial package respectively to form the passivation layers on both sides;

[0075] Fabricate a second wafer package and a third package on both sides of the passivation layer facing away from the initial package respectively so that the electrodes on the same side of the two wafer packages connected through the passivation layer are arranged oppositely;

[0076] Form the passivation layer on the side of the second wafer package and the third package facing away from the initial package, and form a new wafer package on the basis of the passivation layer. Repeat the foregoing steps to form the stacked structure.

[0077] Specifically, corresponding wafer packages can be fabricated on the opposite sides of the initial package respectively by the foregoing method so that the electrodes on the same side of the three wafer packages are arranged oppositely, specifically, the microbump structures are arranged oppositely or the first electrodes of the metal interconnect layers are arranged oppositely, and the corresponding electrodes are aligned through the passivation layer.

[0078] In one embodiment, the temporary bonding adhesive used for the passivation layer may include polypropylene (PET), polyoxymethylene (POM), polymethyl methacrylate (PMMA), polybutylene terephthalate (PBT), and polyethylene (PE), etc.

[0079] In one embodiment, in the formed stacked structure, an antioxidant layer can be provided on the surface of the microbump structure of each of the multiple wafer packages. In the embodiments of the present application, the stacked structure can be formed by multiple wafer packages in an air environment. To prevent the electrodes from being oxidized due to reaction with the air in the environment during the formation of the stacked structure, an antioxidant layer can be provided. The antioxidant layer can also be made of polypropylene material. During the bonding heating, the antioxidant layer is decomposed into a protective atmosphere to further prevent the microbumps from being oxidized during the bonding process. The microbumps will be oxidized during the preparation process. The deoxidized layer can be removed and then an antioxidant layer can be added. In one embodiment, the antioxidant layer can also be made of polycarbonate propylene.

[0080] Step S101, heat and decompose the passivation layer to permanently bond the wafer packages in the stacked structure so that

[0081] Signal paths passing through the stacked structure are formed between the wafer packages in the stacked structure through their respective electrodes, and the fabrication of the device 5 stacked structure is completed.

[0082] In one embodiment, the passivation layer can be decomposed by heating. During the decomposition of the passivation layer, the air between the two wafer packages is extruded, and the aligned electrodes are connected. The micro-bump structure of the wafer package is connected to the first electrode of the metal interconnection layer through a through-hole. After the two wafer packages are interconnected, a signal path penetrating the two wafer packages can be formed. The passivation layer three-dimensional integrated circuit bonding system can perform thermal slip debonding at a temperature below 240°C.

[0083] 0 In one embodiment, an antioxidant layer can be covered on the micro-bump structures of the two wafer packages. During the bonding process, the micro-bump structures are prevented from being oxidized by the antioxidant

[0084] layer. The antioxidant layer can also be made of polypropylene. When heated during bonding, the antioxidant layer is decomposed into a protective atmosphere to further prevent the micro-bumps from being oxidized during the bonding process. The micro-bump structures are oxidized during the manufacturing process. The oxide layer can be removed and then the antioxidant layer is added. In one embodiment, the antioxidant layer can also be made of polycarbonate propylene.

[0085] 5 Further, the backside of the wafer package after temporary bonding can be thinned and wired on the backside. Specifically, through the

[0086] ultra-thin wafer dicing process, the device is thinned to a thickness of 50 μm to 100 μm; the required chips and other peripheral components are integrated on the diced wafer package using an ultra-low arc wire bonding process. After wiring and thinning, temporary bonding is performed again.

[0087] In one embodiment, a passivation layer is used as a sacrificial layer. The melting point of polypropylene is 200 - 250°C, and it thermally decomposes into a protective atmosphere during the permanent bonding

[0088] process. The two wafer packages are stacked using a reflow soldering process, and the electrical signals are interconnected up and down through the silicon through-holes and the micro-0 bump structures. A cleaning process is performed to complete the stacking process of the two-layer device wafers.

[0089] Please refer to Figure 4 , this application also provides a three-dimensional integrated circuit stacking structure, including: a plurality of wafer packages 11;

[0090] A passivation layer 10 is disposed between two adjacent wafer packages 11 to make the same-side electrodes of the two adjacent wafer packages 11 face each other and be aligned. The plurality of wafer packages 11 form a stacking structure. The passivation layer 10 can be made of polypropylene, and the melting point of polypropylene is 200 - 250°C. It thermally decomposes into a protective atmosphere during the permanent bonding process.

[0091] 5 Please refer to Figure 5 , Figure 5This is a schematic structural diagram of a three-dimensional integrated circuit stacked device in an embodiment of the present application. The present application also

[0092] provides a three-dimensional integrated circuit stacked device, including a plurality of wafer packages 11, the plurality of wafer packages form a stacked structure, and the same-side electrodes of two adjacent wafer packages in the stacked structure are oppositely arranged and connected, so that each wafer package forms a signal path passing through the stacked structure through its respective electrodes.

[0093] Based on the above technical solutions, an antioxidant layer is provided on the surface of the microbumps to prevent the microbumps from being oxidized during storage. One of polypropylene, polyoxymethylene, polymethyl methacrylate, polybutylene terephthalate, and polyethylene is selected as the passivation layer, and bonding can be completed through simple hot pressing, simplifying the production process, thereby improving production efficiency and reducing costs, and effectively solving the problems of low productivity, high cost, and poor repeatability caused by the need for special equipment in existing three-dimensional integration.

[0094] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a three-dimensional integrated circuit stacking structure, characterized in that, include: A plurality of wafer packages are provided, wherein the plurality of wafer packages are arranged opposite to each other by electrodes on the same side to form a stacked structure connected in pairs, wherein two adjacent wafer packages in the stacked structure are temporarily bonded by a passivation layer so that the electrodes on the same side of the two adjacent wafer packages are aligned with each other; The wafer package comprises: a substrate; a microcircuit packaging layer, which is arranged on one side of the substrate; a metal interconnection layer, which is arranged on the side of the microcircuit packaging layer away from the substrate, and a first electrode is arranged on the side of the metal interconnection layer away from the substrate; a micro-bump structure, which is arranged on the side of the substrate away from the microcircuit packaging layer, and the micro-bump structure and the first electrode serve as electrodes of the wafer package; a through hole, which is used to connect the micro-bump structure and the first electrode of the metal interconnection layer; providing a plurality of wafer packages, wherein the plurality of wafer packages are arranged oppositely through electrodes on the same side to form a stacked structure connected in pairs, including: selecting a wafer package as an initial package; A layer of temporary bonding glue is applied on the surface of the metal interconnection layer of the initial package to form the passivation layer; a metal interconnection layer, a microcircuit packaging layer, a substrate and a through hole of another wafer package are manufactured on the side of the passivation layer away from the metal interconnection layer of the initial package; a corresponding micro-bump structure is manufactured after thinning the substrate of the other wafer package to obtain a second wafer package; a layer of temporary bonding glue is applied on the surface of the micro-bump structure of the second wafer package to form a passivation layer, a new wafer package is formed on the basis of the passivation layer, and the aforementioned steps are repeated to form the stacked structure; The passivation layer is heated and decomposed to permanently bond the wafer packages in the stacked structure, so that the wafer packages in the stacked structure form a signal path penetrating the stacked structure through their respective electrodes, thereby completing the manufacture of the device stacked structure.

2. The manufacturing method of the three-dimensional integrated circuit stacking structure according to claim 1, characterized in that A plurality of wafer packages are provided, wherein the plurality of wafer packages are arranged opposite to each other through electrodes on the same side to form a stacked structure connected in pairs, including: Selecting a wafer package as an initial package; Coating a layer of temporary bonding glue on the surface of the micro-bump structure of the initial package to form the passivation layer; Fabricate a micro-bump structure, a substrate and a through hole of another wafer package on a side of the passivation layer away from the micro-bump structure of the initial package; After thinning the substrate of the other wafer package, a corresponding microcircuit package layer and a metal interconnection layer are manufactured to obtain a second wafer package; A layer of temporary bonding glue is coated on the surface of the micro-bump structure of the second wafer package to form a passivation layer, a new wafer package is formed on the basis of the passivation layer, and the above steps are repeated to form the stacking structure.

3. The manufacturing method of the three-dimensional integrated circuit stacking structure according to claim 1, wherein A plurality of wafer packages are provided, wherein the plurality of wafer packages are arranged opposite to each other through electrodes on the same side to form a stacked structure connected in pairs, including: Selecting a wafer package as an initial package; Coating a layer of temporary bonding glue on the surface of the micro-bump structure and the surface of the metal interconnection layer of the initial package body to form the passivation layer on both sides; On both sides of the passivation layer facing away from the initial package, a second wafer package and a third package are respectively fabricated so that the electrodes on the same side of the two wafer packages connected by the passivation layer are disposed opposite to each other. On the side of the second wafer package and the third package facing away from the initial package, the passivation layer is formed. On the basis of the passivation layer, a new wafer package is formed. The foregoing steps are repeated to form the stacked structure.

4. The manufacturing method of the three-dimensional integrated circuit stacking structure according to any one of claims 1-3, characterized in that, The temporary bonding adhesive includes polystyrene (PET), polyoxymethylene (POM), polymethyl methacrylate (PMMA), polybutylene terephthalate (PBT), and polyethylene (PE).

5. The manufacturing method of the three-dimensional integrated circuit stacking structure according to claim 1, characterized in that Before the two adjacent wafer packages in the stacked structure are temporarily bonded through the passivation layer, it further includes: A layer of antioxidant layer is disposed on the surface of the micro-bump structure of the wafer package.

6. A three-dimensional integrated circuit stack structure using the manufacturing method of the three-dimensional integrated circuit stack structure according to any one of claims 1-5, characterized in that, Including: Multiple wafer packages; A passivation layer, disposed between two adjacent wafer packages, so that the electrodes on the same side of the adjacent two wafer packages are disposed opposite to each other and aligned with each other. The multiple wafer packages form a stacked structure.

7. A three-dimensional integrated circuit stacked device using the manufacturing method of the three-dimensional integrated circuit stacked structure according to any one of claims 1-5, characterized in that, Including: Multiple wafer packages, the multiple wafer packages form a stacked structure. The electrodes on the same side of the two adjacent wafer packages in the stacked structure are disposed opposite to each other and connected, so that each wafer package forms a signal path penetrating the stacked structure through its respective electrode.

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