A physically unclonable function circuit based on ring oscillation

Abstract

The present invention relates to the technical field of digital integrated circuits, and discloses a physical unclonable function circuit based on ring oscillation, comprising a controller, wherein the controller is connected to a decoder, a multiplexer and a measuring module, wherein the decoder and the multiplexer are connected to an entropy source array; the entropy source array comprises a plurality of groups of special-shaped rings, wherein the input end of the special-shaped rings is connected to the decoder, and the output end of the special-shaped rings is connected to the multiplexer; a clock generator and a timer are arranged inside the controller; the measuring module comprises a level counter, a cycle counter, a divider, a buffer and a comparator, and the controller is connected to the level counter, the cycle counter and the comparator. The duty cycle of the periodic signal generated by the special-shaped ring of the present invention is more sensitive to process deviation, and is less sensitive to changes in operating voltage and ambient temperature, resulting in a higher reliability of the output response of the physical unclonable function circuit.

Description

Technical Field

[0001] The invention relates to the technical field of digital integrated circuits, and in particular to a physical unclonable function circuit based on ring oscillation. Background Art

[0002] With the rapid development of the Internet of Things (IoT), a large amount of data is stored in embedded devices at user terminals in an unprecedented way. Although this has brought indisputable benefits to human society, there are serious hidden dangers in the information security of devices deployed in the electronic world. Private data is stored in non-volatile memory on the device, which can be stolen through reverse engineering, maliciously attacked or forged. Therefore, technologies to ensure hardware security and trust have attracted attention. As a low-cost, high-security hardware primitive, the physical unclonable function circuit enhances resistance to reverse engineering and other physical attacks by extracting random physical changes generated during the manufacturing process of integrated circuits as a unique fingerprint. For mature processes, wafer fabs must control manufacturing deviations within a very limited range. Therefore, the process deviation that can be used for the physical unclonable function circuit in a specific circuit is actually very small, which makes it difficult to obtain a stable response under circuit noise, especially under voltage and temperature changes. Designing a highly reliable PUF primitive is a very critical challenge.

[0003] Physically Unclonable Function (PUF) circuits based on ring oscillators are one of the most popular architectures in academia and industry because they are easy to implement on FPGA or ASIC platforms. The response of the PUF circuit is obtained by measuring the period difference between two identical ring oscillators. This mechanism of accumulating the number of oscillations within the sampling time will effectively eliminate the interference of random circuit noise. However, the main disadvantage of the PUF circuit based on ring oscillators is that its reliability is significantly affected by voltage and temperature changes and counter accuracy. To solve this problem, a PUF circuit that measures the duty cycle of the ring oscillator instead of the period has been proposed. However, this method of comparing the duty cycle of the traditional ring oscillator as the output response is very inefficient in extracting process deviations. As a result, this circuit often fails to obtain the expected reliability results when implemented under mature manufacturing processes, but instead increases the complexity of the design and hardware resource overhead. Therefore, the efficiency of extracting process deviations is critical to the reliability of the PUF circuit. It becomes a severe challenge to ensure the effective extraction of process deviations while improving the circuit's ability to resist voltage and temperature changes. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a physical unclonable function circuit based on ring oscillation to better balance the effects of process deviation, operating voltage and ambient temperature on reliability, thereby ensuring that the physical unclonable function circuit implemented in a mature manufacturing process has high reliability.

[0005] The present invention is implemented by the following technical scheme: a physical unclonable function circuit based on ring oscillation, comprising a controller, the controller is connected to a decoder, a multiplexer and a measurement module, the decoder and the multiplexer are connected to an entropy source array;

[0006] The entropy source array includes multiple groups of special-shaped rings, the input ends of the special-shaped rings are connected to the decoder, and the output ends of the special-shaped rings are connected to the multiplexer;

[0007] The controller is internally provided with a clock generator and a timer;

[0008] The measuring module comprises a level counter, a cycle counter, a divider, a buffer and a comparator, the controller is connected to the level counter, the cycle counter and the comparator, the level counter and the cycle counter are connected to the divider and the multiplexer, and the divider, the buffer and the comparator are connected in sequence.

[0009] As a further improvement of the above solution, the special-shaped ring includes a first inverter, a second inverter, a third inverter, a first NAND gate and a second NAND gate;

[0010] The input end of the special-shaped ring is the first input end of the first NAND gate, and the first input end of the first NAND gate is connected to the decoder, the first output end of the first NAND gate is connected to the input end of the first inverter, the output end of the first inverter is respectively connected to the input end of the third inverter and the first input end of the second NAND gate, the output end of the third inverter is connected to the input end of the second inverter, the output end of the second inverter is connected to the second input end of the second NAND gate, and the output end of the second NAND gate is connected to the second input end of the first NAND gate;

[0011] The output end of the special-shaped ring is the output end of the second inverter, and the output end of the second inverter is connected to the multiplexer.

[0012] As a further improvement of the above solution, the controller is used to control the working state to ensure operation according to the designed timing.

[0013] As a further improvement of the above scheme, the controller is used to receive the original excitation signal input from the outside, send the special-shaped ring sequence signal to the decoder and the multiplexer, send the high-speed sampling signal, reset signal and start signal to the measurement module, and transmit the response signal to the outside.

[0014] As a further improvement of the above solution, the decoder receives the heterodyne sequence signal from the controller and compiles it into a corresponding multi-bit heterodyne selection signal, and transmits the compiled multi-bit heterodyne selection signal to the entropy source array.

[0015] As a further improvement of the above solution, the entropy source array is used to make the selected special-shaped ring generate an oscillation signal with unique identification according to the selection signal compiled by the decoder.

[0016] As a further improvement of the above scheme, the cycle counter is used to measure the number of times the rising edge of the signal received by the measurement module occurs within the sampling time; the level counter is used to measure the number of times the signal received by the measurement module is sampled to a high level by the high-speed sampling clock within the sampling time; the divider performs a division operation to obtain a duty cycle value of an irregular ring; the buffer is used to receive the duty cycle value from the divider; and the comparator extracts two levels of data in the buffer for numerical comparison.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. The present invention can compare the duty cycles of any two special-shaped rings in the entropy source array as a response.

[0019] 2. The duty cycle of the periodic signal generated by the special-shaped ring of the present invention is more sensitive to process deviations, but less sensitive to changes in operating voltage and ambient temperature, resulting in higher reliability of the output response of the physical unclonable function circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A structural diagram of a physical unclonable function circuit based on ring oscillation of the present invention;

[0021] Figure 2 A circuit diagram of a special-shaped ring of the present invention;

[0022] Figure 3 This is a waveform diagram of a periodic signal output by a special-shaped ring of the present invention;

[0023] Figure 4 It is a working timing diagram of the present invention. DETAILED DESCRIPTION

[0024] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of no conflict, the various embodiments or technical features described below can be arbitrarily combined to form a new embodiment.

[0025] Embodiment 1:

[0026] Please combine Figure 1, a physical unclonable function circuit based on ring oscillation of this embodiment includes a controller, the controller is connected to a decoder, a multiplexer and a measurement module, and the decoder and the multiplexer are connected to an entropy source array;

[0027] The entropy source array includes a plurality of groups of special-shaped rings, the input ends of the special-shaped rings are connected to the decoder, and the output ends of the special-shaped rings are connected to the multiplexer;

[0028] The controller is internally provided with a clock generator and a timer;

[0029] The measuring module comprises a level counter, a cycle counter, a divider, a buffer and a comparator, the controller is connected with the level counter, the cycle counter and the comparator, the level counter and the cycle counter are connected with the divider and the multiplexer, and the divider, the buffer and the comparator are connected in sequence;

[0030] The controller is used to control the working status to ensure operation according to the designed timing.

[0031] The controller is used to receive the original excitation signal input from the outside, send the special-shaped ring sequence signal to the decoder and the multiplexer, send the high-speed sampling signal, reset signal and start signal to the measurement module, and transmit the response signal to the outside.

[0032] The decoder receives the heterodyne ring sequence signal from the controller and compiles it into a corresponding multi-bit heterodyne ring selection signal, and transmits the compiled multi-bit heterodyne ring selection signal to the entropy source array.

[0033] The entropy source array is used to enable the multi-bit special-shaped ring to generate an oscillation signal with a unique identification according to the selection signal compiled by the decoder.

[0034] The cycle counter is used to measure the number of times the rising edge of the signal received by the measurement module occurs within the sampling time; the level counter is used to measure the number of times the signal received by the measurement module is sampled to a high level by the high-speed sampling clock within the sampling time; the divider performs a division operation to obtain a duty cycle value of an anomalous ring; the buffer is used to receive the duty cycle value from the divider; and the comparator extracts the two-level data in the buffer for numerical comparison.

[0035] Embodiment 2:

[0036] like Figure 1As shown, the first input terminal Challenge of the controller is used to receive an external original excitation signal, the fifth output terminal Response of the controller is responsible for outputting the response signal received by the second input terminal response to the outside world, the first output terminal Sel_Ring[7:0] is responsible for transmitting the 8-bit original excitation signal to the decoder module and the multiplexer module, the second output terminal dc_clk is responsible for connecting the 800MHz clock generator to the level counter of the measurement module, the third output terminal count_reset-1 is responsible for connecting the reset signal of the timer to the level counter and the cycle counter in the measurement module, so as to clear the counter in time after each measurement is completed, and the fourth output terminal count_start-2 is responsible for connecting the timer enable signal to the level counter and the cycle counter in the measurement module, so as to control the sampling time of the level counter and the cycle counter.

[0037] Embodiment 3:

[0038] like Figure 2 As shown,

[0039] The special-shaped ring includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a first NAND gate NAND1 and a second NAND gate NAND2;

[0040] The input terminal Enable of the special-shaped ring is the first input terminal of the first NAND gate NAND1, and the first input terminal of the first NAND gate NAND1 is connected to the decoder, the first output terminal of the first NAND gate NAND1 is connected to the input terminal of the first inverter INV1, the output terminal of the first inverter INV1 is respectively connected to the input terminal of the third inverter INV3 and the first input terminal of the second NAND gate NAND2, the output terminal of the third inverter INV3 is connected to the input terminal of the second inverter INV2, the output terminal of the second inverter INV2 is connected to the second input terminal of the second NAND gate NAND2, and the output terminal of the second NAND gate NAND2 is connected to the second input terminal of the first NAND gate NAND1;

[0041] The output end of the special-shaped ring is the output end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the multiplexer.

[0042] Embodiment 4:

[0043] like Figure 3As shown, the output node INV1_o of the first inverter INV1, the output node OUT of the second inverter and the output node NAND2_o of the second NAND gate NAND2 are selected to observe the waveform; the waveform of the special-shaped ring output OUT is a periodic signal whose duty cycle is not 50%, and one complete cycle thereof is composed of three path delays, the first segment T1 is the sum of the delays of the second inverter INV2 and the third inverter INV3, the second segment T2 and the third segment T3 are both the sum of the delays of the first NAND gate NAND1, the second NAND gate NAND2 and the first inverter INV1; the duty cycle of the periodic signal output by the special-shaped ring is obtained by dividing the two different circuit delays, so its correlation is weak, which can ensure better process deviation sensitivity.

[0044] Embodiment five:

[0045] Figure 4 The working timing diagram of the physical unclonable function circuit based on ring oscillation of the present invention, wherein the controller receives the original stimulus Challenge from the outside and converts it into an 8-bit ring selection signal Sel_Ring[7:0], and then the decoder compiles the signal into a 256-bit enable signal ro_en[0:255], wherein the corresponding Nth bit ro_en[N] is set to a high level;

[0046] At this time, the enable input of the Nth special-shaped ring is selected, the ring starts to work and the output is connected to the measurement module by the multiplexer; at the same time, the clock generator in the controller generates a 800MHz clock generator dc_clk and transmits it to the clock input of the level counter;

[0047] Subsequently, the count_start signal changes from 0 to 1, and the level counter and the cycle counter start sampling at the same time. The sampling time is determined by the timer in the controller. After the sampling is completed, the count_start signal changes from 1 to 0.

[0048] The results of the level counter and the cycle counter are sent to the divider for calculation, and the duty cycle value of the first special-shaped ring is obtained and temporarily stored in the buffer BUFF-1;

[0049] The count_reset signal is reset, and then the duty cycle value of the second special-shaped ring is obtained by the same operation as above and temporarily stored in the buffer BUFF-2;

[0050] Finally, the comparator compares the duty cycle values ​​of the two buffers to obtain the final response result.

[0051] In summary, the above technical scheme designed by the present invention can compare the duty cycles of any two special-shaped rings in the entropy source array as a response; the duty cycle of the periodic signal generated by the special-shaped ring of the present invention is more sensitive to process deviations, and less sensitive to changes in operating voltage and ambient temperature, resulting in the output response of the physical unclonable function circuit having higher reliability.

[0052] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A physical unclonable function circuit based on ring oscillation, comprising a controller, characterized in that: The controller is connected to a decoder, a multiplexer and a measurement module, and the decoder and the multiplexer are connected to an entropy source array; The entropy source array includes multiple groups of special-shaped rings, the input ends of the special-shaped rings are connected to the decoder, and the output ends of the special-shaped rings are connected to the multiplexer; The controller is internally provided with a clock generator and a timer; The measuring module comprises a level counter, a cycle counter, a divider, a buffer and a comparator, the controller is connected to the level counter, the cycle counter and the comparator, the level counter and the cycle counter are connected to the divider and the multiplexer, and the divider, the buffer and the comparator are connected in sequence; The special-shaped ring includes a first inverter, a second inverter, a third inverter, a first NAND gate and a second NAND gate; The input end of the special-shaped ring is the first input end of the first NAND gate, and the first input end of the first NAND gate is connected to the decoder, the first output end of the first NAND gate is connected to the input end of the first inverter, the output end of the first inverter is respectively connected to the input end of the third inverter and the first input end of the second NAND gate, the output end of the third inverter is connected to the input end of the second inverter, the output end of the second inverter is connected to the second input end of the second NAND gate, and the output end of the second NAND gate is connected to the second input end of the first NAND gate; The output end of the special-shaped ring is the output end of the second inverter, and the output end of the second inverter is connected to the multiplexer.

2. A physical unclonable function circuit based on ring oscillation as claimed in claim 1, characterized in that: The controller is used to control the working state to ensure operation according to the designed timing.

3. A physical unclonable function circuit based on ring oscillation as claimed in claim 1, characterized in that: The controller is used to receive the original excitation signal input from the outside, send the special-shaped ring sequence signal to the decoder and the multiplexer, send the high-speed sampling signal, reset signal and start signal to the measurement module, and transmit the response signal to the outside.

4. A physical unclonable function circuit based on ring oscillation as claimed in claim 1, characterized in that: The decoder receives the heterodyne ring sequence signal from the controller and compiles it into a corresponding multi-bit heterodyne ring selection signal, and transmits the compiled multi-bit heterodyne ring selection signal to the entropy source array.

5. A physical unclonable function circuit based on ring oscillation as claimed in claim 1, characterized in that: The entropy source array is used to enable the selected special-shaped ring to generate an oscillation signal with unique identification according to the selection signal compiled by the decoder.

6. A physical unclonable function circuit based on ring oscillation as claimed in claim 1, characterized in that: The cycle counter is used to measure the number of times the rising edge of the signal received by the measurement module occurs within the sampling time; the level counter is used to measure the number of times the signal received by the measurement module is sampled to a high level by the high-speed sampling clock within the sampling time; The divider performs a division operation to obtain a duty cycle value of a special-shaped ring; the buffer is used to receive the duty cycle value from the divider; and the comparator extracts two levels of data in the buffer for numerical comparison.

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