Self-repairable message order preservation method, device, terminal and storage medium

Abstract

The present application provides a self-repairable message order preservation method, by obtaining the message descriptor of the current message and the message sequence number corresponding to the message descriptor of the current message, and storing the message descriptor of the current message in the cache, and setting the valid bit corresponding to the cache space storing the message descriptor of the current message, and finally obtaining the message sequence number of the current expected output pointed to by the head pointer, if the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is not less than the preset disorder threshold, then according to the order of the message sequence number, all the message descriptors stored in the cache are output in sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset. The present application can effectively prevent the packet blocking problem in the process of message order preservation, and make the disorderly input messages output according to the preset message order after order preservation.

Description

Technical Field

[0001] The present application relates to the field of packet transmission, and in particular to a self-repairable message order preservation method, device, terminal and storage medium. Background Art

[0002] Message sequence preservation refers to the process of accurately ensuring that the order in which the device inlet port receives messages is consistent with the order in which the outlet port sends messages during business processing of data messages. However, in the packet processing system of messages, packet processing can be performed in various ways, such as adding headers to packets, adding labels to packets, classifying packets, and encrypting packets. Since the above-mentioned message processing operations often require different amounts of time to complete the processing, and the message processing procedures in various traffic flows are different, when the messages input in a specific order are output to the chip outlet after message processing, the specific order of the messages will deviate, so sequence preservation management is required so that the messages are output from the chip outlet in the order of the input.

[0003] In the currently common sequence management method, when a message is input into the chip, a serial number is assigned in the input direction. The assigned serial number is carried along the path during the message processing and is recycled in the output direction of the chip. After the serial number is recycled, the recycled serial number is returned to the chip input direction, and the chip input direction allocates it again. However, when a serial number anomaly occurs, it usually causes the serial number to be unable to be recycled. Subsequently, when the serial number allocation of the chip is exhausted, it can no longer receive incoming messages. The above process will cause the entire chip to be blocked, and it is necessary to reset the chip to restore it to normal. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a self-repairable message sequence preservation method for solving the chip packet blocking problem caused by sequence number anomalies during the message sequence preservation process.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a message sequence preservation method, including: obtaining a message descriptor of a current message and a message sequence number corresponding to the message descriptor of the current message; storing the message descriptor of the current message in a cache, wherein each cache space of the cache corresponds one-to-one to each valid bit of a register group, and setting the valid bit corresponding to the cache space storing the message descriptor of the current message; wherein each valid bit of the register group also corresponds one-to-one to the message sequence number; obtaining the message sequence number of the current expected output pointed to by the head pointer, if the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is not less than a preset disorder threshold, then outputting all the message descriptors stored in the cache in sequence according to the order of the message sequence numbers, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located.

[0006] In some embodiments of the first aspect of the present application, if the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is less than a preset out-of-order threshold, different order-preserving operations are performed according to the numerical value relationship between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer; wherein the different order-preserving operations include: outputting the message descriptor of the current message and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located; or outputting the message descriptor of the current message and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located, and increasing the message sequence number of the current expected output pointed to by the head pointer by 1; or maintaining the message descriptor of the current message stored in the cache.

[0007] In some embodiments of the first aspect of the present application, if the message sequence number corresponding to the message descriptor of the current message is smaller than the message sequence number currently expected to be output pointed to by the head pointer, the different order-preserving operations include: outputting the message descriptor of the current message, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located.

[0008] In some embodiments of the first aspect of the present application, if the message sequence number corresponding to the message descriptor of the current message is equal to the message sequence number of the current expected output pointed to by the head pointer, the different order-preserving operations include: outputting the message descriptor of the current message and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located; at the same time, adding 1 to the message sequence number of the current expected output pointed to by the head pointer.

[0009] In some embodiments of the first aspect of the present application, if the message sequence number corresponding to the message descriptor of the current message is greater than the message sequence number of the current expected output pointed to by the head pointer, the different order-preserving operations include: maintaining the message descriptor of the current message stored in the cache.

[0010] In some embodiments of the first aspect of the present application, the message sequence number corresponding to the message descriptor of the current message is generated by one of a plurality of sequencers; and the cache is a plurality of groups of caches, and the plurality of groups of caches correspond one-to-one to a plurality of sequencers; wherein the cache space of a group of the plurality of groups of caches corresponds one-to-one to the message sequence number generated by the sequencer corresponding to the group of caches.

[0011] In some embodiments of the first aspect of the present application, the method also includes: obtaining the message sequencer number of the current message; messages carrying different message sequencer numbers are respectively processed by different sequence preservation modules, each message sequencer number and each sequence preservation module correspond one to one, and each sequence preservation module is used to process messages carrying the message sequencer number corresponding to the sequence preservation module.

[0012] In some embodiments of the first aspect of the present application, before obtaining the message descriptor of the current message and the message sequence number corresponding to the message descriptor of the current message, the following is also performed: identifying and discarding invalid messages, and adding 1 to the compensation count value each time an invalid message is discarded, so that all subsequent messages update the message sequence numbers corresponding to their message descriptors; wherein the update is to instruct the message sequence numbers of all subsequent messages to be subtracted from the compensation count value.

[0013] In some embodiments of the first aspect of the present application, when all message descriptors stored in the cache are output in sequence according to the order of message sequence numbers and the valid bit of the register group corresponding to the cache space where the output message descriptors are located is reset, the message descriptors obtained at this time and their corresponding sequence numbers are directly output, and the valid bits of the register group corresponding to the message descriptors obtained at this time are reset.

[0014] In some embodiments of the first aspect of the present application, if before the message descriptor of the current message is stored in the cache, it is detected that the valid bit of the register group corresponding to the cache space where the message descriptor of the current message should be stored has been set, then the message descriptor of the current message is directly output; and all the message descriptors stored in the current cache space are output in sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset.

[0015] In some embodiments of the first aspect of the present application, if the message sequence number currently expected to be output pointed to by the head pointer cannot be obtained within the preset time, all message descriptors stored in the current cache space are output in sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset.

[0016] In some embodiments of the first aspect of the present application, it also includes: setting a register to trigger the following steps: outputting all message descriptors stored in the cache in sequence according to the order of message sequence numbers, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptors are located.

[0017] In some embodiments of the first aspect of the present application, after executing the method of outputting all message descriptors stored in the cache in sequence according to the order of message sequence numbers and resetting the valid bits of the register group corresponding to the cache space where the output message descriptors are located, the message sequence number currently expected to be output pointed to by the head pointer is the message sequence number corresponding to the message descriptor of the current message plus 1.

[0018] In some embodiments of the first aspect of the present application, after executing the method of outputting all message descriptors stored in the cache in sequence according to the order of message sequence numbers and resetting the valid bits of the register group corresponding to the cache space where the output message descriptors are located, the message sequence number currently expected to be output pointed to by the head pointer is set to the maximum value of the currently obtained message sequence number plus 1.

[0019] In some embodiments of the first aspect of the present application, the step of outputting all message descriptors stored in the cache in sequence according to the order of message sequence numbers, and resetting the valid bits of the register group corresponding to the cache space where the output message descriptors are located includes: obtaining the state of each valid bit in the register group, and the state includes 1 or 0; if there is a valid bit with a state of 1 in the register group, obtaining the message descriptor corresponding to the valid bit with a state of 1 according to the address of the valid bit with a state of 1; and outputting the message descriptors corresponding to the valid bits with a state of 1 in sequence according to the message sequence numbers until there are no valid bits with a state of 1 in the register group.

[0020] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a self-repairable message sequence preservation circuit, comprising: a decoder module: used to obtain a message descriptor of a current message and a message sequence number corresponding to the message descriptor of the current message; a storage module: comprising a cache and a register group; each cache space of the cache corresponds to each valid bit of the register group; the cache is used to store the message descriptor of the current message; the register group is used to set its valid bit when the cache space corresponding to the register group stores the message descriptor of the current message; wherein each valid bit of the register group also corresponds to the message sequence number; an order preservation module: used to obtain the message sequence number of the current expected output pointed to by the head pointer, if the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is not less than a preset disorder threshold, then all the message descriptors stored in the cache are output in sequence according to the order of the message sequence numbers, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset.

[0021] In some embodiments of the second aspect of the present application, the order preservation module includes a disorder counter for storing disorder values. If the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is not less than a preset disorder threshold, the disorder counter increments the stored disorder value.

[0022] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the method when executed by a processor.

[0023] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides an electronic terminal, including: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory so that the terminal executes the method.

[0024] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides a self-repairable message sequence preservation device, including: a sequence number generator: used to generate corresponding message sequence numbers according to the input order of the message; a message processor: used to process the message; wherein the message carries its corresponding message sequence number when processed; and a self-repairable message sequence preservation circuit.

[0025] In some embodiments of the fifth aspect of the present application, there are multiple serial number generators, which are used to generate corresponding message serial numbers and message sequencer numbers according to the input order of the messages and the sequencer numbers for processing the messages.

[0026] As described above, the present application provides a self-repairable message order preservation method, which has the following beneficial effects:

[0027] By adopting a self-repairable message order preservation method described in the present application, the messages to be preserved are classified into three non-overlapping situations according to the numerical relationship between their sequence numbers, disorder thresholds, and sequence numbers pointed to by the head pointer by means of a preset disorder threshold, and different order preservation operations are performed according to their classification. In particular, if it is identified that the difference between the sequence number of the current message and the sequence number pointed to by the head pointer is above the disorder threshold, the self-repair function is turned on, and all messages stored in the cache are output in order to clear the cache, so that subsequent messages can continue to be stored in the cache, effectively preventing the occurrence of packet blocking problems. Furthermore, on the basis of solving the packet blocking problem caused by message disorder in the prior art, the present application also includes directly outputting messages below the disorder threshold or temporarily storing them in the cache to be output when the conditions are met, so that messages input in disorder at the message input can be output in the preset message output order, completing the order preservation management operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a flowchart of a message sequence preservation method in an embodiment of the present application.

[0029] Figure 2 Shown are schematic diagrams of three critical situations of serial number distribution in one embodiment of the present application.

[0030] Figure 3 Shown is a flowchart of serial number determination in one embodiment of the present application.

[0031] Figure 4 The figure shows a schematic diagram of the self-repair process of the sequence-preserving module in one embodiment of the present application.

[0032] Figure 5 Shown is a schematic diagram of the basic structure and data flow of the order-preserving module in one embodiment of the present application.

[0033] Figure 6 Shown is a structural schematic diagram of a self-repairable message sequence-preserving circuit in one embodiment of the present application.

[0034] Figure 7 Shown is a schematic diagram of the structure of a self-repairable message sequence preservation device in one embodiment of the present application.

[0035] Figure 8 Shown is a schematic diagram of the structure of a self-repairable message sequence-preserving terminal in one embodiment of the present application. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0037] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0038] In order to solve the problems in the above-mentioned background technology, the present invention provides a self-repairing message sequence preservation method, which aims to solve the chip packet blocking problem caused by the abnormal sequence number during the message sequence preservation process. At the same time, in order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention is further described in detail through the following embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention and are not used to limit the invention.

[0039] Before further describing the present invention in detail, the nouns and terms involved in the embodiments of the present invention are introduced. It should be noted that the following introduction is only used for convenience of understanding and does not limit the scope of protection of the present application:

[0040] <1> Message: A message is a unit of data exchanged and transmitted in a network, i.e., a block of data to be sent by a station at one time. A message contains the complete data information to be sent, and its length is very inconsistent, unlimited and variable.

[0041] <2> Message sequence preservation: Message sequence preservation refers to the process of accurately ensuring that the order in which data messages are received at the device's inbound port is consistent with the order in which they are sent at the outbound port during business processing.

[0042] <3> Decoder: A decoder is a device that restores information from an encoded form to its original form. In this application, the decoder is used to parse the message descriptor of a message and the message sequence number corresponding to the message descriptor.

[0043] <4> Cache: Cache is a buffer for data exchange (called Cache), which is a temporary place to store data (frequently used data). When a user queries data, it first searches in the cache, and if it is found, it reads it directly. If it is not found, it searches in the database.

[0044] <5> Register: Registers are components of the CPU. Registers are high-speed storage components with limited storage capacity. They can be used to temporarily store instructions, data, and addresses. In the control unit of the CPU, the registers included are the instruction register (IR) and the program counter (PC).

[0045] <6> Head pointer: The head pointer is a pointer that points to the head node or the first element node of the linked list. In the application, the head pointer points to the current expected output message sequence number arranged in the order of the message sequence number.

[0046] <7> Descriptor: A descriptor is an index created by the kernel to efficiently manage operation objects. It is used to refer to the operation object. All system calls related to its I / O operations need to go through the descriptor.

[0047] The embodiments of the present invention provide a self-repairable message order preservation method, a system for the self-repairable message order preservation method, and a storage medium storing an executable program for implementing the self-repairable message order preservation method. As far as the implementation of the self-repairable message order preservation method is concerned, the embodiments of the present invention will illustrate an exemplary implementation scenario of the self-repairable message order preservation method.

[0048] like Figure 1 As shown, a flowchart of a self-repairable message order preservation method in an embodiment of the present invention is shown. The self-repairable message order preservation method in this embodiment mainly includes the following steps:

[0049] Step S11: Acquire a message descriptor of a current message and a message sequence number corresponding to the message descriptor of the current message.

[0050] Specifically, step S11 is implemented by a decoder module in the sequence preservation module, which receives the message and parses its message sequence number, and combines the sequencer number with the valid bits of the sequence number in combination with the number of allocated sequencers to generate a storage address.

[0051] Step S12: The message descriptor of the current message is stored in a cache, wherein each cache space of the cache corresponds one-to-one to each valid bit of the register group, and the valid bit corresponding to the cache space storing the message descriptor of the current message is set; wherein each valid bit of the register group also corresponds one-to-one to the message sequence number.

[0052] Specifically, the sequence-preserving module includes a storage unit; the storage unit is composed of a cache and a register group, wherein each cache space of the cache and each valid bit of the register group are in a one-to-one correspondence. When a message descriptor is stored in a certain cache space, the valid position of the register group corresponding to the cache space is 1, otherwise the valid position of the register group corresponding to the cache space is 0. It should also be noted that each valid bit of the register group also corresponds to the message sequence number one-to-one. In general, there is a fixed mapping relationship between each cache space in the cache, each valid bit in the register group, and the message sequence number of each message, such as the first cache space corresponds to the first valid bit in the register group, and corresponds to the first message sequence number.

[0053] For ease of understanding, the following example is given here: assuming that the sequence number of the currently received message is 3, the message descriptor with the message sequence number 3 is stored in the 3rd cache space in the cache, and the 3rd valid position in the register group corresponding to the 3rd cache space is set to 1, to indicate that the message descriptor with the message sequence number 3 has been stored in the corresponding cache space.

[0054] Step S13: Obtain the message sequence number of the current expected output pointed to by the head pointer. If the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is not less than a preset disorder threshold, then all message descriptors stored in the cache are output in sequence according to the order of the message sequence numbers, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset.

[0055] Specifically, a head pointer is also set in the register to point to the message sequence number currently expected to be output. For example, if at a certain moment, the current sequence preservation module expects to output a message descriptor with a message sequence number of 5, then the object pointed to by the head pointer is the valid bit (the 5th valid bit of the register group) of the register group corresponding to the message sequence number (message sequence number 5), which is used to prompt the message descriptor that should be output at this moment according to the message sequence number order.

[0056] A disorder threshold is preset to indicate the disorder degree of the message received by the order preservation module. Preferably, the disorder threshold does not exceed one half of the maximum message sequence number. In this embodiment, if the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is not less than the preset disorder threshold, it means that the order preservation module determines that there is an abnormality in the current message sequence number and enters a self-repair state. Preferably, the self-repair state means that the order preservation module outputs all message descriptors stored in the cache in sequence, and resets the valid bits of the register group corresponding to the cache space where the output message descriptors are located. Since the order preservation module recognizes that there is an abnormality in the current message order preservation activity, if self-repair measures are not taken, with the continuous input and caching of incoming messages, the risk of chip packet jamming continues to increase. Therefore, in this embodiment, when the order preservation module detects that the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number currently expected to be output pointed to by the head pointer is not less than a preset out-of-order threshold, all message descriptors currently stored in the cache are emptied in order, and the valid bits of the register group corresponding to the cache space where the output message descriptors are located are reset, so that the cache space is restored to a blank state for storing the upcoming new messages, thereby preventing the chip from being blocked.

[0057] In some implementations of the present embodiment, if the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is less than a preset out-of-order threshold, different order-preserving operations are performed according to the numerical relationship between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer; wherein the different order-preserving operations include: outputting the message descriptor of the current message, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located; or outputting the message descriptor of the current message, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located, and increasing the message sequence number of the current expected output pointed to by the head pointer by 1; or maintaining the message descriptor of the current message stored in the cache.

[0058] Specifically, if the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is less than the preset disorder threshold, it means that the messages in the order preservation module may be out of order at this time, and the disorder is controllable and is not sufficient to cause the chip packet blocking problem. Therefore, in this case, it is necessary to judge the size relationship between the message sequence number and the message sequence number of the current expected output pointed to by the head pointer, so as to perform different order preservation operations: output the message descriptor of the current message, and reset the valid bit of the register group corresponding to the cache space where the output message descriptor is located; or output the message descriptor of the current message, and reset the valid bit of the register group corresponding to the cache space where the output message descriptor is located, and increase the current expected output message sequence number pointed to by the head pointer by 1; or maintain the message descriptor of the current message stored in the cache.

[0059] In some implementations of this embodiment, if the message sequence number corresponding to the message descriptor of the current message is smaller than the message sequence number currently expected to be output pointed to by the head pointer, the different order-preserving operations include: outputting the message descriptor of the current message, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located.

[0060] Specifically, if the message sequence number corresponding to the message descriptor of the current message is less than the message sequence number of the current expected output pointed to by the head pointer, it means that there is a delay in the output of the current message, that is, the current message should have been output before. However, since the current disorder level has not reached the disorder threshold, the message descriptor of the current message should be output directly, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located should be reset. Based on this order preservation operation, the order preservation module can identify the message descriptor that is output too late at the current moment, and output the message descriptor in time to complete the message order preservation.

[0061] In some implementation processes of this embodiment, if the message sequence number corresponding to the message descriptor of the current message is equal to the message sequence number of the current expected output pointed to by the head pointer, the different order-preserving operations include: outputting the message descriptor of the current message and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located; at the same time, increasing the message sequence number of the current expected output pointed to by the head pointer by 1.

[0062] Specifically, if the message sequence number corresponding to the message descriptor of the current message is equal to the message sequence number of the current expected output pointed to by the head pointer, it means that the current message is exactly the message that the order-preserving module should output at this time according to the order of the message sequence numbers, so the message descriptor of the current message is output, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset. It should be noted that in this case, since the order-preserving module outputs the message sequence number of the current expected output pointed to by the head pointer on time, after outputting the message, the message sequence number of the current expected output pointed to by the head pointer is increased by 1, and the output operation is performed when the next message carrying the expected message sequence number is input. Through the above method, the order-preserving model can output the message descriptor carrying the expected message sequence number pointed to by the head pointer in sequence.

[0063] In some implementations of this embodiment, if the message sequence number corresponding to the message descriptor of the current message is greater than the message sequence number of the current expected output pointed to by the head pointer, the different order-preserving operations include: maintaining the message descriptor of the current message stored in the cache.

[0064] Specifically, if the message sequence number corresponding to the message descriptor of the current message is greater than the message sequence number currently expected to be output pointed to by the head pointer, it means that the current message arrives at the order preservation module a little earlier, and the current message needs to be maintained and stored in the corresponding cache space. When the subsequent head pointer points to the message sequence number corresponding to the current message, the message is output in sequence. Through the above order preservation operation, the message descriptor of the message with a later message sequence number can be temporarily stored in the cache, and output when the order output conditions are met, completing the message order preservation.

[0065] It should be noted that the present invention actually determines three non-overlapping and complementary numerical intervals to cover all message sequence numbers by comparing the numerical relationship between the message sequence number corresponding to the message descriptor of the current message, the message sequence number of the current expected output pointed to by the head pointer, and the disorder threshold, and performs different sequence preservation operations based on the numerical intervals in which the message sequence number is located. For example:

[0066] The first interval (flush area) is: the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number currently expected to be output pointed to by the head pointer is not less than a preset disorder threshold.

[0067] The second interval (send area) is: the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is less than the preset disorder threshold, and the message sequence number corresponding to the message descriptor of the current message is less than the message sequence number of the current expected output pointed to by the head pointer.

[0068] The third interval (reorder area) is: the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is less than the preset disorder threshold, and the message sequence number corresponding to the message descriptor of the current message is greater than the message sequence number of the current expected output pointed to by the head pointer.

[0069] It also includes a fourth node: the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is less than a preset disorder threshold, and the message sequence number corresponding to the message descriptor of the current message is equal to the message sequence number of the current expected output pointed to by the head pointer.

[0070] The first, second, third intervals and the fourth node are sufficient to cover all message sequence numbers, forming a complete order preservation process to complete the order preservation operation of all messages.

[0071] In some implementations of this embodiment, since the sequence number output by the sequencer will be cleared when it overflows, the sequence preservation module needs to consider critical situations when determining the interval to which the sequence number belongs, such as Figure 2 Three critical situations are shown:

[0072] The first critical case (corresponding to Figure 2 Scenario 3): When (head pointer + out of order threshold > maximum sequence number): the first range starts at (head pointer + out of order threshold - maximum sequence number) and ends at (head pointer - out of order threshold); the second range starts at (head pointer - out of order threshold) and ends at (head pointer - 1); the third interval has two parts: the first part starts at the head pointer and ends at the maximum sequence number; the second part starts at the initial value 0 and ends at (head pointer + out of order threshold - maximum sequence number).

[0073] The second critical case (corresponding to Figure 2 Scenario 2): When (head pointer < out-of-order threshold): the first interval starts at (head pointer + out-of-order threshold) and ends at (maximum sequence number - out-of-order threshold + head pointer); the second interval has two parts: the first part starts at the initial value 0 and ends at (head pointer - 1); the second part starts at (maximum sequence number - out-of-order threshold + head pointer) and ends at the maximum sequence number; the third interval starts at the head pointer and ends at (head pointer + out-of-order threshold).

[0074] The third critical situation (corresponding to Figure 2 Scenario 1): The first interval has two parts: the first part starts at the initial value 0 and ends at (head pointer-out of order threshold); the second part starts at (head pointer + out of order threshold) and ends at the maximum sequence number; the third part starts at (head pointer-out of order threshold) and ends at (head pointer-1); the third part starts at the head pointer and ends at (head pointer + out of order threshold).

[0075] It needs to be explained that Figure 2 The flush interval is the first interval, the send interval is the second interval, the store and reorder interval is the third interval, ooo count refers to the disorder threshold, head pointer is the sequence number pointed to by the head pointer, max sequence number is the maximum value of the message sequence number, and sequence number wrap is an entire sequence package, including all sequence numbers.

[0076] It should be noted that Figure 2 It also shows the situation in which the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is less than the preset disorder threshold, and the message sequence number corresponding to the message descriptor of the current message is equal to the message sequence number of the current expected output pointed to by the head pointer in three situations, that is, Figure 2 The intersection of the second (send) interval and the third (reorder) interval.

[0077] In some implementations of this embodiment, the message sequence number corresponding to the message descriptor of the current message is generated by one of a plurality of sequencers; and the cache is a plurality of groups of caches, and the plurality of groups of caches correspond one-to-one to a plurality of sequencers; wherein the cache space of a group of the plurality of groups of caches corresponds one-to-one to the message sequence number generated by the sequencer corresponding to the group of caches.

[0078] Specifically, under some preferred implementations, since the input messages are often not of the same type, the messages can be classified in advance according to their categories, and order-preserving operations can be performed based on their classifications. By setting multiple sequencers to generate serial numbers for messages of different categories, the serial numbers generated by each sequencer are independent of each other and increase in sequence. In addition, when there are multiple sequencers, multiple groups of caches are set to correspond one-to-one with multiple sequencers, and each cache space in a single group of caches corresponds one-to-one with the serial number generated by its corresponding sequencer. For ease of understanding, the above scenario is illustrated here by example: assuming that the incoming messages are divided into three categories according to the pre-classification criteria, three sequencers are pre-set, wherein each sequencer corresponds one-to-one to each category of the message, such as the first sequencer corresponds to the first category of messages, the second sequencer corresponds to the second category of messages, and the third sequencer corresponds to the third category of messages. The three sequencers generate message sequence numbers and sequencer numbers for the messages of their corresponding categories respectively, which are carried by the messages during the processing. For example, the first message in the first category carries the first sequence number and the first sequencer number. The sequence number and the sequencer number are combined to identify a message in all categories of messages. In terms of setting the cache, each cache group in the multiple cache groups corresponds to each sequencer one by one. For example, the first cache group corresponds to the first sequencer, so each cache space in the first cache group corresponds to the sequence number generated by the first sequencer one by one, such as the first cache space of the first cache group corresponds to the first sequence number generated by the first sequencer.

[0079] In some implementation processes of this embodiment, the method also includes: obtaining the message sequencer number of the current message; messages carrying different message sequencer numbers are respectively processed by different sequence preservation modules, each message sequencer number and each sequence preservation module has a one-to-one correspondence, and each sequence preservation module is used to process messages carrying the message sequencer number corresponding to the sequence preservation module.

[0080] Specifically, when the sequence number is generated by multiple sequencers respectively, a sequencer number for generating a message sequence number is also generated separately, and the message carries its message sequence number and sequencer number along the way during the processing to distinguish all messages. It should be noted that messages carrying different message sequencer numbers are processed by different sequence preservation modules respectively, and there is a one-to-one correspondence between each message sequencer number and each sequence preservation module, and each sequence preservation module is only responsible for processing messages carrying the message sequencer number corresponding to the sequence preservation module. For example, in a certain application scenario, there are 5 message sequencers and 5 sequence preservation modules corresponding one-to-one, then the first sequence preservation module is only responsible for processing messages carrying the message sequence number generated by the first message sequencer (that is, messages carrying a message sequencer number of 1).

[0081] In some implementations of this embodiment, before obtaining the message descriptor of the current message and the message sequence number corresponding to the message descriptor of the current message, the following is also performed: identifying and discarding invalid messages, adding 1 to the compensation count value each time an invalid message is discarded, so that all subsequent messages update the message sequence numbers corresponding to their message descriptors; wherein the update is to instruct the message sequence numbers of all subsequent messages to be subtracted from the compensation count value.

[0082] Specifically, before the message is input into the sequence management module, since not all the input messages are valid, the present embodiment also includes a step of identifying and discarding invalid messages. This step is used to identify invalid messages in the incoming and outgoing messages and discard them to improve the processing efficiency of subsequent messages and prevent the waste of cache resources. Furthermore, since each message has been generated with a sequence number that increases in sequence by the sequence number generator before entering the sequence management module, discarding the invalid messages therein will cause the message sequence number to be discontinuous, making it inconvenient to maintain the sequence. Therefore, in the present embodiment, a compensation count value is set, and each time an invalid message is discarded, the compensation count value is increased by one, and all subsequent input messages have their message sequence numbers updated, so that the message sequence numbers of all subsequent messages are subtracted from the compensation count value. For example, in a certain scenario, when the message with the input message sequence number of 5 is identified as an invalid message and discarded, the message sequence numbers of all subsequent messages are updated to reduce their message sequence numbers by one, that is, the message with the original message sequence number of 6 is updated to 5, the message with the original message sequence number of 7 is updated to 6, and so on. Based on the above message preprocessing operation, invalid messages in the message can be excluded without affecting the normal operation of the order preservation operation.

[0083] In some implementation processes of this embodiment, when all message descriptors stored in the cache are output in sequence according to the message sequence number order and the valid bit of the register group corresponding to the cache space where the output message descriptors are located is reset, the message descriptors obtained at this time and their corresponding sequence numbers are directly output, and the valid bits of the register group corresponding to the message descriptors obtained at this time are reset.

[0084] Specifically, when all the message descriptors stored in the cache are output in sequence according to the message sequence number, and the valid bit of the register group corresponding to the cache space where the output message descriptors are located is reset, it indicates that the sequence preservation module is in the self-repair stage. If the sequence preservation module receives a new message descriptor and its corresponding sequence number at this time, since the self-repair process has not been completed, the newly obtained message descriptor and its corresponding sequence number are directly output, and the valid bit of the register group corresponding to the message descriptor obtained at this time is reset.

[0085] Figure 3 Shown is a flowchart of serial number determination in one embodiment of the present application.

[0086] In some implementations of this embodiment, if before the message descriptor of the current message is stored in the cache, it is detected that the valid bit of the register group corresponding to the cache space where the message descriptor of the current message should be stored has been set, then the message descriptor of the current message is directly output; and all the message descriptors stored in the current cache space are output in sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset.

[0087] Specifically, before storing the message descriptor of the current message in the cache, the order preservation module can confirm whether the cache space corresponding to the message sequence number of the message has been occupied by calling the register (detecting through the register whether the valid bit of the register group corresponding to the cache space is 1 or 0, 1 indicates occupied, and 0 indicates vacant). If it is detected that the cache space is occupied at this time, it indicates that an error has occurred in the order preservation link, so the self-repair process is triggered: the message descriptor of the current message is directly output; and all the message descriptors stored in the current cache space are output in sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset.

[0088] In some implementations of this embodiment, if the message sequence number currently expected to be output pointed to by the head pointer cannot be obtained within a preset time, all message descriptors stored in the current cache space are output in sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptors are located is reset.

[0089] Specifically, if the sequence preservation module fails to obtain the message sequence number of the current expected output pointed to by the head pointer within the preset threshold time, it indicates that there is an abnormality in the operation of the current sequence preservation module, so the self-repair process is triggered: all message descriptors stored in the current cache space are output in sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset.

[0090] In some implementations of this embodiment, the method also includes: setting a register to trigger the following steps: outputting all message descriptors stored in the cache in sequence according to the order of message sequence numbers, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptors are located.

[0091] Specifically, the self-repair process in the present application can also be actively triggered by setting a register. By setting a register instruction, the above-mentioned self-repair process can be triggered by the outside world: all message descriptors stored in the cache are output in sequence, and the valid bits of the register group corresponding to the cache space where the output message descriptors are located are reset.

[0092] In some implementations of the present embodiment, after the process of outputting all the message descriptors stored in the cache in sequence according to the order of the message sequence numbers and resetting the valid bits of the register group corresponding to the cache space where the output message descriptors are located, the message sequence number currently expected to be output pointed to by the head pointer is the message sequence number corresponding to the message descriptor of the current message plus 1.

[0093] Specifically, after the sequence-preserving module completes the self-repair process, in order to restore the module to a normal operating state, the message sequence number currently expected to be output pointed to by the head pointer is set to the message sequence number corresponding to the message descriptor of the current message plus 1. For example, if the sequence-preserving module triggers the self-repair process after receiving a message with a message sequence number of 5, then after the self-repair process, the message sequence number currently expected to be output pointed to by the head pointer is set to 6, so that the messages are output in order.

[0094] In some implementations of the present embodiment, after the process of outputting all the message descriptors stored in the cache in sequence according to the message sequence number order and resetting the valid bit of the register group corresponding to the cache space where the output message descriptors are located is executed, the message sequence number currently expected to be output pointed to by the head pointer is the message sequence number corresponding to the message descriptor of the current message plus 1, and the maximum value of the message sequence number currently obtained is increased by 1.

[0095] Specifically, each packet sequence preservation module maintains a head pointer internally, which is used to point to the sequence number that the current packet sequence preservation module expects to output according to the sequence preservation requirements. When the message descriptor is correctly output according to the sequence preservation requirements, the corresponding head pointer is increased by 1; when the packet sequence preservation module enters the self-repair state, the corresponding head pointer is assigned different values ​​according to different triggering conditions. In some implementation processes of the aforementioned present embodiment, the self-repair process is triggered in addition to the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number currently expected to be output pointed to by the head pointer is not less than the preset disorder threshold, and also includes two situations: active triggering through a register and triggering when it is detected that the valid bit of the register group corresponding to the cache space where the message descriptor of the current message should be stored has been set. In these two cases, after the triggered self-repair process ends, the message sequence number currently expected to be output pointed to by the head pointer is set to the message sequence number corresponding to the message descriptor of the current message plus 1, and the maximum value of the currently obtained message sequence number is increased by 1 to restore the normal operation of the sequence preservation activity.

[0096] In some implementations of this embodiment, the step of outputting all message descriptors stored in the cache in sequence according to the message sequence number order, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptors are located includes: obtaining the state of each valid bit in the register group, and the state includes 1 or 0; if there is a valid bit with a state of 1 in the register group, obtaining the message descriptor corresponding to the valid bit with a state of 1 according to the address of the valid bit with a state of 1; and outputting the message descriptors corresponding to the valid bit with a state of 1 in sequence according to the message sequence number until there is no valid bit with a state of 1 in the register group.

[0097] Specifically, Figure 4 Shown is a schematic diagram of the self-repair process of the order-preserving module in one embodiment of the present application. The self-repair process of the order-preserving module first detects the status of all valid bits of the register. If the status is 1, it means that the cache space corresponding to the valid bit stores the message descriptor, and if the status is 0, it means that the cache space corresponding to the valid bit does not store the message descriptor. If a valid bit of the register with a status of 1 is detected in the aforementioned steps, the message descriptors corresponding to all valid bits with a status of 1 are obtained according to the address of the valid bit with a status of 1, and these message descriptors are output in sequence. After the output is completed, continue to detect the status of all valid bits of the register. If there are still valid bits of the register group with a status of 1, repeat the above-mentioned step of outputting the message descriptor until the order-preserving module no longer detects the existence of valid bits with a status of 1 in the register. The purpose of the above steps is to confirm whether the self-repair process has successfully output all the message descriptors stored in the cache.

[0098] Although the various steps in the above embodiment are described in the above-mentioned order, those skilled in the art can understand that in order to achieve the effect of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple changes are within the protection range of the present invention.

[0099] Figure 5It is shown as a schematic diagram of the basic structure and data flow of the order-keeping module in an embodiment of the present application. Specifically, when the processed message and the sequence number and sequencer number carried along with it are input into the message order-keeping module, it first enters the write controller for judgment. According to the relationship between the sequence number, the sequence number position pointed to by the head pointer, and the disorder threshold, it is judged whether the message is normally stored in the cache RAM and the order-keeping process is performed. Under abnormal circumstances, the flush self-repair is triggered, and the self-repair flag bit state is used to identify whether it is currently in the self-repair state. Among them, the self-repair state can also be triggered by a timeout controller or a soft controller. The read controller determines the relationship between the value of the sequence number pointed to by the head pointer and the register group, which is used to control the message order-keeping output. In the flush self-repair state, the read controller quickly scans the register group array and empties the message in the cache RAM. When all the messages in the cache are emptied, the self-repair flag bit state is cleared to restore normal order-keeping work.

[0100] In some implementations of this embodiment, a self-repairable message sequence preservation circuit 600 is also involved, including: a decoder module 601: used to obtain a message descriptor of a current message and a message sequence number corresponding to the message descriptor of the current message; a storage module 602: including a cache and a register group; each cache space of the cache corresponds to each valid bit of the register group one by one; the cache is used to store the message descriptor of the current message; the register group is used to store the message descriptor of the current message when the cache space corresponding to the register group stores the message descriptor of the current message. The valid bit is set; wherein, each valid bit of the register group also corresponds one-to-one to the message sequence number; the sequence preservation module 603: is used to obtain the message sequence number of the current expected output pointed to by the head pointer, if the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is not less than the preset disorder threshold, then according to the order of the message sequence number, all the message descriptors stored in the cache are output in sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset.

[0101] Specifically, Figure 6 Shown is a structural diagram of a self-repairable message sequence preservation circuit in one embodiment of the present application. The decoder module 601 is used to receive the message sequencer number and the message sequence number, and in combination with the number of allocated sequencers, the sequencer number and the sequence number valid bits are spliced ​​to generate a storage address. The decoder module 601 obtains the access address of the cache space and the register group by recombining the sequencer number and the sequence number. Based on the size of the cache space and the register group, as the number of sequencers increases, the cache space that each sequencer can detect decreases linearly. When the sequence number is assigned to the message input, there is no need to perceive the number of sequencers, and all sequencers can still detect the entire storage space of the cache.

[0102] In some implementations of this embodiment, the order preservation module 603 includes a disorder counter for storing disorder values. If the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is not less than a preset disorder threshold, the disorder counter increments the stored disorder value.

[0103] like Figure 7 As shown, a schematic diagram of the structure of a self-repairable message sequence preservation device in an embodiment of the present invention is shown. In this embodiment, a self-repairable message sequence preservation device 700 includes: a sequence number generator 701: used to generate corresponding message sequence numbers according to the input order of the message; a message processor 702: used to process the message; wherein the message carries its corresponding message sequence number when processed; a self-repairable message sequence preservation circuit 703: used to perform message sequence preservation according to the method.

[0104] Specifically, when the sequence number generator 701 of the incoming message receives a message, it uses an incremental method and follows the order in which the message is received to mark the input message with a sequence number in sequence. The initial value is 0, and the sequence number will be carried along the path until the message is processed and input into the message sequence preservation module 703 for post-processing. The sequence number generator 701 only responds to the flow control signal returned by the subsequent stage to control the message receiving flow, wherein the generation of the sequence number is realized by a counter. Each time a message is received, the counter is incremented by 1, and the corresponding carried sequence number is incremented by 1. When the counter reaches the maximum value, it flips over and starts counting again from 0. Therefore, the entire process does not require the recovery and redistribution of sequence numbers.

[0105] In some implementations of this embodiment, pre-classification can be performed based on the preliminary analysis of the message, and multiple sequencers are allocated based on the pre-classification results, and the sequence numbers between the sequencers are independent of each other, and the sequence number generated by a single sequencer needs to be processed separately. The sequencer number will be carried along the route until it is input into the message sequence protection module for post-processing after the message processing is completed.

[0106] In some implementations of this embodiment, there are multiple serial number generators for generating corresponding message serial numbers and message sequencer numbers according to the input order of the messages and the serializer numbers for processing the messages.

[0107] It should be noted that: the self-repairable message sequence preservation device provided in the above embodiment only uses the division of the above program modules as an example when performing self-repairable message sequence preservation. In actual applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the device is divided into different program modules to complete all or part of the processing described above. In addition, the self-repairable message sequence preservation device provided in the above embodiment and the self-repairable message sequence preservation method embodiment belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0108] The self-repairable message sequence preservation method provided in the embodiment of the present invention can be implemented on the terminal side or the server side. As for the hardware structure of the self-repairable message sequence preservation terminal, please refer to Figure 8 , is an optional hardware structure diagram of a self-repairable message sequence preservation terminal 800 provided in an embodiment of the present invention. The terminal 800 may be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The self-repairable message sequence preservation terminal 800 includes: at least one processor 801, a memory 802, at least one network interface 804 and a user interface 806. The various components in the device are coupled together through a bus system 805. It can be understood that the bus system 805 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 805 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, in Figure 8 In the specification, various buses are labeled as bus systems.

[0109] The user interface 806 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0110] It is understood that the memory 802 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0111] The memory 802 in the embodiment of the present invention is used to store various categories of data to support the operation of the self-repairable message sequence preservation terminal 800. Examples of these data include: any executable program used to operate on the self-repairable message sequence preservation terminal 800, such as an operating system 8021 and an application 8022; the operating system 8021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 8022 may include various applications, such as a media player (MediaPlayer), a browser (Browser), etc., for implementing various application services. The self-repairable message sequence preservation method provided by the embodiment of the present invention may be included in the application 8022.

[0112] The method disclosed in the above embodiment of the present invention can be applied to the processor 801, or implemented by the processor 801. The processor 801 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 801 or the instruction in the form of software. The above processor 801 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 801 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 801 can be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0113] In an exemplary embodiment, the self-repairable message sequence preservation terminal 800 can be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), and complex programmable logic devices (CPLDs) to execute the aforementioned method.

[0114] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

[0115] In the embodiments provided in the present application, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

[0116] In summary, the present application provides a self-repairable message sequence preservation method, device, terminal and medium, and the present invention provides a method for improving the efficiency of self-repairable message sequence preservation, which is used to solve the chip packet blocking problem caused by abnormal sequence number during message sequence preservation. Therefore, the present application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0117] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A self-repairable message order preservation method, characterized in that: include: Obtaining a message descriptor of a current message and a message sequence number corresponding to the message descriptor of the current message; The message descriptor of the current message is stored in a cache, wherein each cache space of the cache corresponds to each valid bit of the register group, and the valid bit corresponding to the cache space storing the message descriptor of the current message is set; wherein each valid bit of the register group also corresponds to the message sequence number; Obtaining the message sequence number of the current expected output pointed to by the head pointer, if the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is not less than a preset disorder threshold, then outputting all the message descriptors stored in the cache in order according to the message sequence number sequence, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located; If the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is less than a preset out-of-order threshold, different order-preserving operations are performed according to the numerical value relationship between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer; wherein the different order-preserving operations include: outputting the message descriptor of the current message, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located; or outputting the message descriptor of the current message, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located, and increasing the message sequence number of the current expected output pointed to by the head pointer by 1; or maintaining the message descriptor of the current message stored in the cache.

2. The self-repairable message order preservation method according to claim 1, characterized in that: If the message sequence number corresponding to the message descriptor of the current message is smaller than the message sequence number currently expected to be output pointed to by the head pointer, the different order-preserving operations include: outputting the message descriptor of the current message and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located.

3. The self-repairable message order preservation method according to claim 1, characterized in that: If the message sequence number corresponding to the message descriptor of the current message is equal to the message sequence number of the current expected output pointed to by the head pointer, the different order-preserving operations include: outputting the message descriptor of the current message and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located; at the same time, increasing the message sequence number of the current expected output pointed to by the head pointer by 1.

4. The self-repairable message order preservation method according to claim 1, characterized in that: If the message sequence number corresponding to the message descriptor of the current message is greater than the message sequence number of the current expected output pointed to by the head pointer, the different order-preserving operations include: maintaining the message descriptor of the current message stored in the cache.

5. The self-repairable message order preservation method according to any one of claims 1 to 4, characterized in that: The message sequence number corresponding to the message descriptor of the current message is generated by one of multiple sequencers; and the cache is a plurality of groups of caches, and the plurality of groups of caches correspond one-to-one to the plurality of sequencers; wherein the cache space of one group of the plurality of groups of caches corresponds one-to-one to the message sequence number generated by the sequencer corresponding to the group of caches.

6. The self-repairable message order preservation method according to claim 5, characterized in that: The method also includes: obtaining the message sequencer number of the current message; messages carrying different message sequencer numbers are respectively processed by different sequence preservation modules, each message sequencer number corresponds to each sequence preservation module one by one, and each sequence preservation module is used to process the message carrying the message sequencer number corresponding to the sequence preservation module.

7. The self-repairable message order preservation method according to any one of claims 1 to 4, characterized in that: Before obtaining the message descriptor of the current message and the message sequence number corresponding to the message descriptor of the current message, the following steps are also performed: identifying and discarding invalid messages, increasing the compensation count value by 1 each time an invalid message is discarded, so that all subsequent messages update the message sequence numbers corresponding to their message descriptors; wherein the update is to instruct the message sequence numbers of all subsequent messages to be subtracted from the compensation count value.

8. The self-repairable message order preservation method according to any one of claims 1 to 4, characterized in that: When all the message descriptors stored in the cache are output in sequence according to the message sequence number order, and the valid bit of the register group corresponding to the cache space where the output message descriptors are located is reset, the message descriptors obtained at this time and their corresponding sequence numbers are directly output, and the valid bit of the register group corresponding to the message descriptors obtained at this time is reset.

9. The self-repairable message order preservation method according to any one of claims 1 to 4, characterized in that: If, before the message descriptor of the current message is stored in the cache, it is detected that the valid bit of the register group corresponding to the cache space where the message descriptor of the current message should be stored has been set, the message descriptor of the current message is directly output; and all the message descriptors stored in the current cache space are output in sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset.

10. The self-repairable message order preservation method according to any one of claims 1 to 4, characterized in that: If the message sequence number currently expected to be output pointed to by the head pointer cannot be obtained within the preset time, all message descriptors stored in the current cache space are output in sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptors are located is reset.

11. The self-repairable message order preservation method according to any one of claims 1 to 4, characterized in that: Also includes: The register is set to trigger the following steps: all message descriptors stored in the cache are output in sequence according to the message sequence number sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset.

12. The self-repairable message order preservation method according to any one of claims 1 to 4, characterized in that: After executing the method of outputting all the message descriptors stored in the cache in sequence according to the order of the message sequence numbers and resetting the valid bits of the register group corresponding to the cache space where the output message descriptors are located, the message sequence number currently expected to be output pointed to by the head pointer is the message sequence number corresponding to the message descriptor of the current message plus 1.

13. The self-repairable message order preservation method according to claim 10, characterized in that: After executing the method of outputting all the message descriptors stored in the cache in sequence according to the order of the message sequence numbers and resetting the valid bits of the register group corresponding to the cache space where the output message descriptors are located, the message sequence number currently expected to be output pointed to by the head pointer is set to the maximum value of the currently obtained message sequence number plus 1.

14. The self-repairable message order preservation method according to claim 11, characterized in that: After executing the method of outputting all the message descriptors stored in the cache in sequence according to the order of the message sequence numbers and resetting the valid bits of the register group corresponding to the cache space where the output message descriptors are located, the message sequence number currently expected to be output pointed to by the head pointer is set to the maximum value of the currently obtained message sequence number plus 1.

15. The self-repairable message order preservation method according to any one of claims 1 to 4, characterized in that: The step of outputting all the message descriptors stored in the cache in order according to the message sequence number sequence, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptors are located comprises: Obtaining the status of each valid bit in the register group, wherein the status includes 1 or 0; If there is a valid bit with a status of 1 in the register group, obtaining a message descriptor corresponding to the valid bit with a status of 1 according to the address of the valid bit with a status of 1; The message descriptors corresponding to the valid bits whose status is 1 are output in sequence according to the message sequence numbers until there are no valid bits whose status is 1 in the register group.

16. A self-repairable message sequence-preserving circuit, characterized in that: include: Decoder module: used for obtaining a message descriptor of a current message and a message sequence number corresponding to the message descriptor of the current message; The storage module includes a cache and a register group; each cache space of the cache corresponds to each valid bit of the register group one by one; the cache is used to store the message descriptor of the current message; the register group is used to set the valid bit when the cache space corresponding to the register group stores the message descriptor of the current message; wherein each valid bit of the register group also corresponds to the message sequence number one by one; Sequence preservation module: used to obtain the message sequence number of the current expected output pointed to by the head pointer, if the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is not less than the preset disorder threshold, then all the message descriptors stored in the cache are output in sequence according to the message sequence number sequence, and the valid bit of the register group corresponding to the cache space where the output message descriptor is located is reset; If the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is less than a preset out-of-order threshold, different order-preserving operations are performed according to the numerical value relationship between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer; wherein the different order-preserving operations include: outputting the message descriptor of the current message, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located; or outputting the message descriptor of the current message, and resetting the valid bit of the register group corresponding to the cache space where the output message descriptor is located, and increasing the message sequence number of the current expected output pointed to by the head pointer by 1; or maintaining the message descriptor of the current message stored in the cache.

17. A self-repairable message sequence-preserving circuit according to claim 16, characterized in that: Used to execute the method according to any one of claims 1 to 15.

18. The self-repairable message sequence-preserving circuit according to claim 16, characterized in that: The order-preserving module includes an out-of-order counter for storing out-of-order values. If the difference between the message sequence number corresponding to the message descriptor of the current message and the message sequence number of the current expected output pointed to by the head pointer is not less than a preset out-of-order threshold, the out-of-order counter increments the stored out-of-order value.

19. A self-repairable message sequence preservation device, characterized in that: include: Sequence number generator: used to generate corresponding message sequence numbers according to the input order of the messages; Message processor: used to process messages; wherein the message carries its corresponding message sequence number when processed; The self-repairable message sequence preservation circuit as described in claim 16 is used to perform message sequence preservation according to the method described in any one of claims 1 to 15.

20. The self-repairable message sequence preservation device according to claim 19, characterized in that: There are multiple sequence number generators, which are used to generate corresponding message sequence numbers and message sequencer numbers according to the input order of the messages and the sequencer numbers for processing the messages.

21. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 15 is implemented.

22. An electronic terminal, characterized in that: include: Processor and memory; The memory is used to store computer programs; The processor is configured to execute the computer program stored in the memory, so as to enable the terminal to perform the method according to any one of claims 1 to 15.

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