register

Abstract

The application discloses a register, comprising: a master-slave flip-flop powered by a first power voltage; a balloon latch powered by a second power voltage, wherein the second power voltage is independent of the first power voltage; and a level shifter providing voltage conversion between the master-slave flip-flop and the balloon latch; wherein data is stored in the master-slave flip-flop, and when the first power voltage is disabled, the balloon latch is configured to temporarily retain the data. Since the balloon latch is powered by the second power voltage instead of the first power voltage, the balloon latch can help temporarily retain the data of the master-slave flip-flop, so that the register in the design of the embodiment of the application not only provides the function of data retention, but also reduces the overall power consumption.

Description

Technical Field

[0001] This invention relates to the field of electrical technology, and more particularly to a register. Background Technology

[0002] In a traditional register design, all latches are powered by the same power source. If the power is off (or on), the register cannot retain data. However, the power consumption of traditional registers can be too high. Therefore, a novel solution is needed to address the problems of existing technologies or traditional designs. Summary of the Invention

[0003] In view of this, the present invention provides a register with data retention to solve the above problems.

[0004] According to a first aspect of the present invention, a register is disclosed, comprising:

[0005] Master-slave flip-flops, powered by the first power supply voltage;

[0006] A balloon latch, powered by a second power supply voltage, wherein the second power supply voltage is independent of the first power supply voltage; and

[0007] A level shifter provides voltage conversion between the master-slave flip-flop and the balloon latch;

[0008] The master-slave trigger stores data, and the balloon latch is configured to temporarily hold the data when the first power supply voltage is disabled.

[0009] The register of this invention includes: a master-slave flip-flop powered by a first power supply voltage; a balloon latch powered by a second power supply voltage, wherein the second power supply voltage is independent of the first power supply voltage; and a level shifter providing voltage conversion between the master-slave flip-flop and the balloon latch; wherein data is stored in the master-slave flip-flop, and the balloon latch is configured to temporarily retain the data when the first power supply voltage is disabled. Because the balloon latch is powered by the second power supply voltage instead of the first power supply voltage, it can help temporarily retain data from the master-slave flip-flop. Therefore, the register proposed in this embodiment not only provides data retention functionality but also reduces overall power consumption. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a register according to an embodiment of the present invention;

[0011] Figure 2 This is a circuit diagram of a register according to an embodiment of the present invention;

[0012] Figure 3 This is a circuit diagram of a master-slave flip-flop according to another embodiment of the present invention;

[0013] Figure 4 This is a circuit diagram of a master-slave flip-flop according to another embodiment of the present invention;

[0014] Figure 5 A circuit diagram of a register according to another embodiment of the present invention; and

[0015] Figure 6 This is a voltage waveform diagram of the register according to an embodiment of the present invention;

[0016] Figure 7 This is a schematic diagram of a register according to another embodiment of the present invention;

[0017] Figure 8 This is a schematic diagram of a register according to yet another embodiment of the present invention. Detailed Implementation

[0018] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0019] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one component, part, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary component, part, region, layer, or portion discussed below may be referred to as a second or secondary component, part, region, layer, or portion.

[0020] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of a component or feature to it. Another component or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0021] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0022] What will be understood is that when a “component” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another component or layer, it can be directly on, connected to, coupled to, or adjacent to the other component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another component or layer, there are no intermediate components or layers.

[0023] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0024] Figure 1This is a schematic diagram of register 100 according to an embodiment of the present invention. Register 100 can be applied to a mobile device, such as a smartphone, tablet computer, or notebook computer, but is not limited thereto. Figure 1 As shown, register 100 includes a master-slave flip-flop 110, a balloon latch 120, and a level shifter 130. The master-slave flip-flop 110 is powered by a first power supply voltage VDD1. The balloon latch 120 is powered by a second power supply voltage VDD2. It should be noted that the second power supply voltage VDD2 is independent of the first power supply voltage VDD1. For example, the first power supply voltage VDD1 may come from a first power supply, and the second power supply voltage VDD2 may come from a second power supply. If the first power supply is turned off, the first power supply voltage VDD1 will be disabled, but this will not negatively affect the second power supply voltage VDD2 from the second power supply. In some embodiments, the second power supply voltage VDD2 is always enabled (either the second power supply voltage VDD2 is always enabled or the second power supply voltage VDD2 is always enabled). The voltages of the first power supply voltage VDD1 and the second power supply voltage VDD2 can be the same or different. In one embodiment, a first power supply voltage VDD1 is supplied to the master-slave flip-flop 110, but the power supply may be disconnected; for example, by controlling the switch between the first power supply voltage VDD1 and the master-slave flip-flop 110 to supply power to the master-slave flip-flop 110, and by controlling the switch to disconnect to stop supplying power to the master-slave flip-flop 110. A second power supply voltage VDD2 supplies power to the balloon latch 120, and in one embodiment, the second power supply voltage VDD2 continuously supplies power to the balloon latch 120 without interruption. A level shifter (or voltage level shifter) 130 provides voltage conversion between the master-slave flip-flop 110 and the balloon latch 120. For example, the level shifter 130 may be a cross-coupling type level shifter or a current-mirror type level shifter.

[0025] Data DA is originally stored in master-slave flip-flop 110. Typically, when the first power supply voltage VDD1 is disabled (either when the first power supply voltage VDD1 is disabled or when VDD1 is disabled), balloon latch 120 is configured to temporarily retain data DA, so data DA is not lost. Specifically, register 100 can operate in normal mode, saving mode, or restoring mode. In normal mode, master-slave flip-flop 110 functions normally. In saving mode, data DA can be read from master-slave flip-flop 110 and then written to balloon latch 120. Conversely, in restoring mode, data DA can be read from balloon latch 120 and then written back to master-slave flip-flop 110. For example, the above read and write operations can be performed based on received signals. For example, master-slave flip-flop 110 (or master latch) may have one or more interfaces that can be used to receive data DA, clock CK, save mode signal, restore mode signal, etc. For example, the first power supply voltage VDD1 can be temporarily disabled after the save mode and before the restore mode (the first power supply voltage VDD1 can be temporarily disabled after the save mode and before the restore mode). In this embodiment of the invention, the first power supply voltage VDD1 being disabled or temporarily disabled can be active or passive. For example, in some application scenarios, the first power supply voltage VDD1 may be interrupted due to need, and this invention can be applied to these application scenarios. Since the balloon latch 120 is powered by the second power supply voltage VDD2 instead of the first power supply voltage VDD1, the balloon latch 120 can help temporarily (or temporarily) retain the data DA of the master-slave flip-flop 110. In the design of this embodiment of the invention, the proposed register 100 not only provides the function of data retention, but also reduces the overall power consumption. In some embodiments, the register 100 is considered to be a DRRTFF (Dual-Rail Retention Flip-Flop). In the prior art, for example, the master-slave flip-flop 110 is powered by the first power supply voltage VDD1, and the balloon latch 120 is also powered by the first power supply voltage VDD1. However, the inventors discovered that in this application scenario, when the first power supply voltage VDD1 is disconnected for some reason, data loss will occur. Furthermore, this design places high demands on the first power supply voltage VDD1, resulting in significant design limitations.Therefore, in the embodiments of the present invention proposed by the inventors, the balloon latch 120 is designed to be powered by a second power supply voltage VDD2 independent of the first power supply voltage VDD1. The second power supply voltage VDD2 is a continuously supplying power source. In addition, for voltage adaptation, the embodiments of the present invention provide a level converter 130 to perform voltage conversion and balancing. Therefore, in the solution proposed in the embodiments of the present invention, even in some scenarios where the first power supply voltage VDD1 needs to be disabled, data can be (temporarily) saved in the balloon latch 120, so that data will not be lost. At the same time, the use of power supply is more flexible, improving the elasticity and flexibility of the design and providing more design options. In addition, in the solution of the embodiments of the present invention, the first power supply voltage VDD1 can be disabled normally without any problems, so the overall power consumption of register 100 will be reduced.

[0026] The following embodiments will describe different configurations and detailed structural features of register 100. It should be understood that these figures and descriptions are exemplary only and not intended to limit the invention.

[0027] Figure 2 This is a circuit diagram of register 200 according to an embodiment of the present invention. Figure 2 In this embodiment, register 200 includes a master-slave flip-flop 210, a balloon latch 220, and a level shifter 230. The master-slave flip-flop 210 is powered by a first power supply voltage VDD1. The balloon latch 220 is powered by a second power supply voltage VDD2. It should be noted that the second power supply voltage VDD2 is independent of the first power supply voltage VDD1. In some embodiments, the device or apparatus supplied or powered by the second power supply voltage VDD2 is implemented using a higher threshold voltage (e.g., HVT (higher threshold voltage)) device, while other devices or apparatuses are devices or apparatuses using a lower threshold voltage, such as a lower threshold voltage (LVT) or a standard threshold voltage (SVT).

[0028] The balloon latch 220 includes a first inverter 251, a second inverter 252, a third inverter 253, a first transmission gate 261, a second transmission gate 262, a third transmission gate 263, and a fourth transmission gate 264. The first transmission gate 261 can be opened (disconnected) or closed (connected) according to the restoring voltage VR. The first transmission gate 261 has a first terminal coupled to a first common node NM1 and a second terminal coupled to a second common node NM2. The second transmission gate 262 can be opened (disconnected) or closed (connected) according to the inverted restoring voltage VRB. The second transmission gate 262 has a first terminal coupled to the first common node NM1 and a second terminal coupled to the first node N1. In some embodiments, the inverted restoring voltage VRB is generated by triggering the restoring voltage VR, and they have complementary logic levels.

[0029] For example, if the transmission gate is controlled according to a corresponding voltage, it can be closed when the corresponding voltage has a high logic level (e.g., logic "1"), and opened when the corresponding voltage has a low logic level (e.g., logic "0"), but is not limited thereto. Furthermore, if the transmission gate is closed, its first terminal can be coupled to its second terminal. Conversely, if the transmission gate is open, its first terminal can be decoupled from its second terminal. That is, in this document, "closed" represents being connected, and "open" represents being disconnected.

[0030] The first inverter 251 has an input terminal coupled to the first node N1 and an output terminal coupled to the second node N2. The third transmission gate 263 can be opened or closed according to the inverted (inverted) saving voltage VSB (the third transmission gate 263 can also be opened or closed according to the saving voltage VS, which does not affect the operation of the third transmission gate 263). The third transmission gate 263 has a first terminal coupled to the second node N2 and a second terminal coupled to the third node N3. The input terminal of the second inverter 252 is coupled to the third node N3, and its output terminal is coupled to the first node N1. The fourth transmission gate 264 can be opened or closed (or disconnected or connected) according to the saving voltage VS. The first terminal of the fourth transmission gate 264 is coupled to the third node N3, and its second terminal is coupled to the fourth node N4. The input terminal of the third inverter 253 is coupled to the fifth node N5, and its output terminal is coupled to the fourth node N4. In some embodiments, the inverted storage voltage VSB is generated by triggering the storage voltage VS, and they have complementary logic levels.

[0031] The level shifter 230 includes a first P-type transistor MP1, a second P-type transistor MP2, a third P-type transistor MP3, a fourth P-type transistor MP4, a first N-type transistor MN1, and a second N-type transistor MN2. For example, each P-type transistor can be a PMOS transistor (P-type Metal-Oxide-Semiconductor Field-Effect Transistor), and each N-type transistor can be an NMOS transistor (N-type Metal-Oxide-Semiconductor Field-Effect Transistor).

[0032] The first P-type transistor MP1 has a control terminal coupled to the sixth node N6, a first terminal coupled to the second power supply voltage VDD2, and a second terminal coupled to the seventh node N7. The second P-type transistor MP2 has a control terminal coupled to the fifth node N5, a first terminal coupled to the second power supply voltage VDD2, and a second terminal coupled to the eighth node N8. The third P-type transistor MP3 has a control terminal for receiving a shifting voltage VL, a first terminal coupled to the seventh node N7, and a second terminal coupled to the fifth node N5. The fourth P-type transistor MP4 has a control terminal for receiving an inverted shifting voltage VLB, a first terminal coupled to the eighth node N8, and a second terminal coupled to the sixth node N6. The first N-type transistor MN1 has a control terminal for receiving a shifting voltage VL, a first terminal coupled to the ground voltage VSS, and a second terminal coupled to the fifth node N5. The second N-type transistor MN2 has a control terminal for receiving the inverted shift voltage VLB, a first terminal coupled to the ground voltage VSS, and a second terminal coupled to the sixth node N6. In some embodiments, the inverted shift voltage VLB is generated by triggering a shift voltage VL, and they have complementary logic levels.

[0033] The master-slave trigger 210 includes a fourth inverter 254, a fifth inverter 255, a sixth inverter 256, a seventh inverter 257, a fifth transmission gate 265, a sixth transmission gate 266, a seventh transmission gate 267, an eighth transmission gate 268, a first control inverter 271, and a second control inverter 272.

[0034] The fourth inverter 254 has an input terminal for receiving a data voltage VD and an output terminal coupled to the ninth node N9. The fifth transmission gate 265 can be turned on or off (or disconnected or connected) according to the inverted clock CKB. The fifth transmission gate 265 has a first terminal coupled to the ninth node N9 and a second terminal coupled to the tenth node N10. The input terminal of the first control inverter 271 is coupled to the tenth node N10, and its output terminal is coupled to the eleventh node N11. The sixth transmission gate 266 can be turned on or off according to the clock CK. The sixth transmission gate 266 has a first terminal coupled to the tenth node N10 and a second terminal coupled to the twelfth node N12. The input terminal of the fifth inverter 255 is coupled to the eleventh node N11, and its output terminal is coupled to the twelfth node N12. In some embodiments, the inverted clock CKB is generated by triggering the clock CK, and they have complementary logic levels.

[0035] The seventh transmission gate 267 can be turned on or off according to the clock CK. The seventh transmission gate 267 has a first terminal coupled to the eleventh node N11 and a second terminal coupled to the thirteenth node N13. The input of the sixth inverter 256 is coupled to the thirteenth node N13 to receive the shift voltage VL, while its output is coupled to the second common node NM2 to output the inverted shift voltage VLB. In some embodiments, the shift voltage VL and the inverted shift voltage VLB of the master-slave flip-flop 210 are also arranged to control the level shifter 230. The eighth transmission gate 268 can be turned on or off according to the inverted clock CKB. The eighth transmission gate 268 has a first terminal coupled to the thirteenth node N13 and a second terminal coupled to the fourteenth node N14. The input of the second control inverter 272 is coupled to the first common node NM1 and its output is coupled to the fourteenth node N14. The seventh inverter 257 has an input coupled to the second common node NM2 and an output for outputting the output voltage VQ. In some embodiments, any one of the data voltage VD, shift voltage VL, and output voltage VQ is considered to be the aforementioned data DA stored in the master-slave flip-flop 210.

[0036] Specifically, register 200 can operate in normal mode, save mode, or restore mode, which will be described in detail below.

[0037] In normal mode, the storage voltage VS is at a low logic level, and the recovery voltage VR is at a high logic level. Therefore, the first transmission gate 261 and the third transmission gate 263 are both closed, and the second transmission gate 262 and the fourth transmission gate 264 are both open. The master-slave flip-flop 210 is used as a normal flip-flop.

[0038] In save mode, both the save voltage VS and the recovery voltage VR are at high logic levels. Therefore, the first transmission gate 261 and the fourth transmission gate 264 are both closed, while the second transmission gate 262 and the third transmission gate 263 are both open. At this time, data (e.g., data voltage VD, shift voltage VL, or output voltage VQ) can be read from the master-slave flip-flop 210 and then written to the balloon latch 220. Furthermore, the level shifter 230 can provide voltage conversion for the data between the first power supply voltage VDD1 and the second power supply voltage VDD2.

[0039] In recovery mode, the save voltage VS, the recovery voltage VR, and the clock CK are all at low logic levels. Therefore, the second transmission gate 262 and the third transmission gate 263 are both closed, while the first transmission gate 261 and the fourth transmission gate 264 are both open. At this time, data can be read from the balloon latch 220 and then written back to the master-slave flip-flop 210. Therefore, even if the first power supply voltage VDD1 is temporarily disabled, the output voltage VQ of the master-slave flip-flop 210 can be fully recovered (because the second power supply voltage VDD2 of the balloon latch 220 is always enabled).

[0040] Figure 3 This is a circuit diagram of a master-slave flip-flop 310 according to another embodiment of the present invention. The master-slave flip-flop 310 with a positive reset function can be applied to the aforementioned register 200. Figure 3 In this embodiment, the master-slave flip-flop 310 includes a first inverse NOR gate 371 and a second NOR gate 372, replacing the first control inverter 271 and the second control inverter 272 described above, respectively. Specifically, the first NOR gate 371 has a first input terminal for receiving the reset voltage VRE, a second input terminal coupled to the tenth node N10, and an output terminal coupled to the eleventh node N11. The second NOR gate 372 has a first input terminal coupled to the first common node NM1, a second input terminal for receiving the reset voltage VRE, and an output terminal coupled to the fourteenth node N14. It should be noted that if the reset voltage VRE is a high logic level, the output voltage VQ can be forcibly reset to a low logic level. Figure 3 Other features of the master-slave trigger 310 and Figure 2 The master-slave triggers 210 have similar characteristics. Therefore, the two embodiments can achieve similar levels of performance. Compared to Figure 2 Implementation examples, Figure 3 The embodiments have a reset function, thus providing more design options.

[0041] Figure 4This is a circuit diagram of a master-slave flip-flop 410 according to another embodiment of the present invention. The master-slave flip-flop 410 with a negative set function can be applied to the aforementioned register 200. Figure 4 In this embodiment, the master-slave flip-flop 410 includes a first NAND gate 471 and a second NAND gate 472, replacing the first control inverter 271 and the second control inverter 272 described above, respectively. Specifically, the first NAND gate 471 has a first input terminal for receiving a set voltage VSE, a second input terminal coupled to the tenth node N10, and an output terminal coupled to the eleventh node N11. The second NAND gate 472 has a first input terminal coupled to the first common node NM1, a second input terminal for receiving the set voltage VSE, and an output terminal coupled to the fourteenth node N14. It should be noted that if the set voltage VSE is a low logic level, the output voltage VQ can be forced to a high logic level. Figure 4 Other features of the master-slave trigger 410 and Figure 2 The master-slave triggers 210 have similar characteristics. Therefore, the two embodiments can achieve similar performance levels. Compared to Figure 2 Implementation examples, Figure 4 The embodiments have a set function, thus providing more design options.

[0042] Figure 5 This is a circuit diagram of register 500 according to another embodiment of the present invention. Figure 5 In this embodiment, register 500 includes a master-slave flip-flop 210, a balloon latch 520, a level shifter 530, and auxiliary circuitry 540. The master-slave flip-flop 210 is powered by a first power supply voltage VDD1. The balloon latch 520 is powered by a second power supply voltage VDD2. It should be noted that the second power supply voltage VDD2 is independent of the first power supply voltage VDD1. The circuit structure and operation of the master-slave flip-flop 210 have been described in the above embodiments and will not be repeated here.

[0043] The balloon latch 520 includes a first inverter 251, a second inverter 252, a first transmission gate 261, a second transmission gate 262, a third transmission gate 263, and a fourth transmission gate 264. The first transmission gate 261 can be opened or closed according to a recovery voltage VR. The first transmission gate 261 has a first terminal coupled to a first common node NM1 and a second terminal coupled to a second common node NM2. The second transmission gate 262 can be opened or closed according to an inverted recovery voltage VRB. The second transmission gate 262 has a first terminal coupled to the first common node NM1 and a second terminal coupled to a first node N1. The input terminal of the first inverter 251 is coupled to the first node N1, and the output terminal is coupled to the second node N2. The third transmission gate 263 can be opened or closed according to an inverted storage voltage VSB. The third transmission gate 263 has a first terminal coupled to the second node N2 and a second terminal coupled to the third node N3. The second inverter 252 has an input coupled to the third node N3 and an output coupled to the first node N1. The fourth transmission gate 264 can be turned on or off according to the stored voltage VS. The first terminal of the fourth transmission gate 264 is coupled to the third node N3, and the second terminal of the fourth transmission gate 264 is coupled to the fourth node N4.

[0044] The level shifter 530 includes a first P-type transistor MP1, a second P-type transistor MP2, a third P-type transistor MP3, a fourth P-type transistor MP4, a first N-type transistor MN1, and a second N-type transistor MN2. The first P-type transistor MP1 has a control terminal coupled to a fifth node N5, a first terminal coupled to a second power supply voltage VDD2, and a second terminal coupled to a sixth node N6. The second P-type transistor MP2 has a control terminal coupled to a fourth node N4, a first terminal coupled to the second power supply voltage VDD2, and a second terminal coupled to a seventh node N7. The third P-type transistor MP3 has a control terminal coupled to an eighth node N8, a first terminal coupled to the sixth node N6, and a second terminal coupled to the fourth node N4. The fourth P-type transistor MP4 has a control terminal coupled to a connection node NE, a first terminal coupled to the seventh node N7, and a second terminal coupled to the fifth node N5. The first N-type transistor MN1 has a control terminal coupled to the eighth node N8, a first terminal coupled to a ground voltage VSS, and a second terminal coupled to the fourth node N4. The second N-type transistor MN2 has a control terminal coupled to the connection node NE, a first terminal coupled to the ground voltage VSS, and a second terminal coupled to the fifth node N5.

[0045] An auxiliary circuit 540 is coupled to a level shifter 530. Typically, the auxiliary circuit 540 can selectively pull up the voltage V8 at the eighth node N8 to the second supply voltage VDD2. Specifically, the auxiliary circuit 540 includes a control transistor MS, a third inverter 253, and an auxiliary transmission gate 569. In some embodiments, the control transistor MS is a PMOS transistor. The control transistor MS has a control terminal for receiving an operating voltage VT, a first terminal coupled to the second supply voltage VDD2, and a second terminal coupled to the eighth node N8. For example, the operating voltage VT can be the same as the storage voltage VS, the first supply voltage VDD1, or the second supply voltage VDD2. In an alternative embodiment, the control transistor MS is replaced with another NMOS transistor, and the operating voltage (or working voltage, operating voltage) VT is the same as the inverted storage voltage VSB or the ground voltage VSS. The input of the third inverter 253 is coupled to the eighth node N8, and the output is coupled to the connection node NE. The auxiliary transmission gate 569 can be turned on or off depending on the storage voltage VS. The auxiliary transmission gate 569 has a first terminal coupled to the eighth node N8 and a second terminal for receiving the inverted shift voltage VLB from the master-slave flip-flop 210. In some embodiments, the third inverter 253 in the auxiliary circuit 540 is provided or powered by the first power supply voltage VDD1, but is not limited thereto.

[0046] Similarly, register 500 can operate in normal mode, save mode, or restore mode, which will be described in detail below.

[0047] In normal mode, the storage voltage VS is at a low logic level and the recovery voltage VR is at a high logic level. Therefore, the first transmission gate 261 and the third transmission gate 263 are both closed, while the second transmission gate 262, the fourth transmission gate 264, and the auxiliary transmission gate 569 are all open. Furthermore, the P-type transistor MP5 is turned on to pull up the voltage V8 at the eighth node N8. The master-slave flip-flop 210 functions as a normal flip-flop.

[0048] In save mode, both the save voltage VS and the recovery voltage VR are at high logic levels. Therefore, the first transmission gate 261, the fourth transmission gate 264, and the auxiliary transmission gate 569 are all closed, while the second transmission gate 262 and the third transmission gate 263 are both open. Furthermore, the P-type transistor MP5 is turned off. At this time, data can be read from the master-slave flip-flop 210 and then written to the balloon latch 520. This design results in relatively low path loading for the master-slave flip-flop 210 because only the inverting shift voltage VLB is used to operate the balloon latch 520 (without using the shift voltage VL).

[0049] In recovery mode, the storage voltage VS, recovery voltage VR, and clock CK are all at low logic levels. Therefore, the second transmission gate 262 and the third transmission gate 263 are both closed, while the first transmission gate 261, the fourth transmission gate 264, and the auxiliary transmission gate 569 are all open. Furthermore, the P-type transistor MP5 is turned on to pull up the voltage V8 at the eighth node N8. At this time, data can be read from the balloon latch 520 and then written back to the master-slave flip-flop 210. It is important to note that in both normal and recovery modes, the control transistor MS provides a stable input to the control level shifter 530. This design effectively reduces the power consumption of the level shifter 530 because the inverted storage voltage VSB (with fluctuations) from the master-slave flip-flop 210 is completely blocked by the auxiliary transmission gate 569.

[0050] Figure 5 Other features of register 500 are similar to Figure 2 Those features of register 200. Therefore, the two embodiments can achieve a similar level of performance. In an alternative embodiment, Figure 3 Master-slave trigger 310 or Figure 4 The master-slave trigger 410 can also be applied to Figure 5 Register 500.

[0051] Figure 6 This is a voltage waveform diagram of register 100 (or 200 or 500) according to an embodiment of the present invention, where the horizontal axis represents time and the vertical axis represents each voltage level. During the first stage T1, register 100 operates in normal mode, with the first power supply voltage VDD1 and clock CK enabled. During the second stage T2, register 100 operates in save mode, with the save voltage VS generating a high logic pulse (high logic level), causing data DA to be transferred from master-slave flip-flop 110 to balloon latch 120. In the third stage T3, clock CK and the first power supply voltage VDD1 are temporarily turned off to reduce the power consumption of the entire register 100 (shaded areas indicate no signal input). During the fourth stage T4, register 100 operates in recovery mode, with the recovery voltage VR generating a low logic pulse (low logic level), causing data DA to be transferred from balloon latch 120 back to master-slave flip-flop 110. In the fifth stage T5, register 100 also operates in normal mode, with the first power supply voltage VDD1 and clock CK enabled again.

[0052] In this embodiment of the invention, register 100 can also be made in many different variations. For example, Figure 7 This is a schematic diagram of a register according to another embodiment of the present invention. Figure 7As shown, in one embodiment of the present invention, the master-slave trigger 110 may include a master latch 119 and a slave latch 118. The master latch 119 may have one or more input interfaces for receiving, for example, data DA, clock CK, signals for triggering save mode (e.g., SAVE signal), signals for triggering restore mode (e.g., RESTORE signal), etc. The slave latch 118 may have an output terminal Q for outputting signals or data, etc. The master latch 119 is connected to the slave latch 118. The master latch 119 and the slave latch 118 are powered by a first power supply voltage VDD1, and the balloon latch 120 is powered by a second power supply voltage VDD2. The register 100 may have level shifters 131 and 132, which may both be connected (coupled) between the balloon latch 120 and the slave latch 118. The specific locations of level converters 131 and 132 connected to latch 118 can be freely selected and replaced according to the design, and are not limited in this embodiment of the invention. Both level converters 131 and 132 can provide conversion between the first power supply voltage VDD1 and the second power supply voltage VDD2. In the embodiment of the invention proposed by the inventors, balloon latch 120 is designed to be powered by a second power supply voltage VDD2 independent of the first power supply voltage VDD1. The second power supply voltage VDD2 is a continuously powered power supply. Furthermore, for voltage adaptation, this embodiment of the invention provides level converters 131 and / or 132 for voltage conversion and balancing. Therefore, in the solution proposed in this embodiment of the invention, even in scenarios where the first power supply voltage VDD1 needs to be disabled, data can be (temporarily) saved in balloon latch 120, thus preventing data loss. This also provides greater flexibility in power supply usage, improving design elasticity and flexibility, and offering more design options. Furthermore, in this embodiment of the invention, any one or both of level converters 131 and 132 may adopt the same structure or configuration as the level converters 130, 230, and 530 described above. For example, any one or both of level converters 131 and 132 may be cross-coupled level converters or current mirror level converters.

[0053] like Figure 7As shown, in this embodiment of the invention, level converters 131 and 132 can be provided, or one of them can be omitted, or both can be omitted. For example, when the second power supply voltage VDD2 is greater than the first power supply voltage VDD1, level converter 131 can be provided while level converter 132 can be omitted, thus reducing the number of components, simplifying the design, and reducing power consumption; of course, level converter 132 can also be included. When the second power supply voltage VDD2 is less than the first power supply voltage VDD1, level converter 132 can be provided while level converter 131 can be omitted, thus reducing the number of components, simplifying the design, and reducing power consumption; of course, level converter 131 can also be included. When the second power supply voltage VDD2 is equal to the first power supply voltage VDD1, level converters 131 and 132 can be omitted (in which case the balloon latch is directly connected to the master-slave flip-flop), thus reducing the number of components, simplifying the design, and reducing power consumption; of course, level converters 131 and 132 can also be included. In this embodiment of the invention, both level converter 131 and level converter 132 can be provided simultaneously, which can be applied to more application scenarios, such as when the magnitudes of the first power supply voltage VDD1 and the second power supply voltage VDD2 are uncertain or their magnitudes may change. Therefore, this embodiment of the invention provides multiple designs for level converter 131 and level converter 132 to provide more flexible and diverse design options and meet different design requirements.

[0054] In this embodiment of the invention, register 100 can also be made in many different variations. For example, Figure 8 This is a schematic diagram of a register according to yet another embodiment of the present invention. Figure 8 As shown, this embodiment is similar to Figure 7 The difference lies in that level shifters 131 and 132 can both be connected (coupled) between the balloon latch 120 and the main latch 119. The specific locations where level shifters 131 and 132 are connected to the main latch 119 can be freely chosen and replaced according to the design; this embodiment of the invention is not limited. Figure 8 As shown in the embodiments of the present invention, with Figure 7 The illustrated embodiment is the same, and can include level shifters 131 and 132. Alternatively, one of level shifters 131 and 132 can be omitted, or both can be omitted (in which case the balloon latch is directly connected to the master-slave flip-flop), providing more flexible and diverse design options to meet different design requirements. Therefore, the present invention... Figure 7 and Figure 8The embodiments provide different design options to offer more diverse design choices, increase design flexibility and adaptability, and meet different application requirements. Furthermore, in these embodiments, any one or both of level converters 131 and 132 can adopt the same structure or configuration as the aforementioned level converters 130, 230, and 530. For example, any one or both of level converters 131 and 132 can be cross-coupled level converters or current mirror level converters.

[0055] This invention proposes a novel register. Compared to conventional designs, this invention offers advantages in data retention and low power consumption, making it suitable for various electronic devices.

[0056] It should be noted that the aforementioned component parameters such as voltage, current, resistance, inductance, and capacitance are not limitations of this invention. Designers can adjust these settings according to different requirements. The registers of this invention are not limited to... Figure 1-6 The configuration. This invention may include only... Figure 1-6 Any one or more features of any one or more embodiments. In other words, not all features shown in the figures should be implemented in the registers of this invention. Although embodiments of this invention use MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) as an example, this invention is not limited thereto. Those skilled in the art can use other types of transistors, such as BJT (Bipolar Junction Transistor), JFET (Junction Gate Field Effect Transistor), FinFET (Fin Field Effect Transistor), etc., without affecting the performance of this invention.

[0057] The use of sequential terms such as “first,” “second,” and “third” in claims to modify claim elements does not imply any priority, order, or temporal sequence of action of one claim element relative to another claim element. These terms are merely labels used to distinguish one claim element with a specific name from another element with the same name (but using serial numbers) to differentiate claim elements.

[0058] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A register, characterized in that, include: Master-slave trigger, powered by the first power supply voltage; The balloon latch is powered by a second power supply voltage, which is independent of the first power supply voltage. as well as A level shifter provides voltage conversion between the master-slave flip-flop and the balloon latch; The master-slave trigger stores data, and the balloon latch is configured to temporarily hold the data when the first power supply voltage is disabled. The balloon latch includes: A first transmission gate is closed or opened according to a recovery voltage, wherein a first end of the first transmission gate is coupled to a first common node, and a second end of the first transmission gate is coupled to a second common node. The second transmission gate is closed or opened according to the inverted recovery voltage, wherein the second transmission gate has a first end coupled to the first common node and a second end coupled to the first node; A first inverter, wherein the first inverter has an input terminal coupled to the first node and an output terminal coupled to the second node; The third transmission gate is turned off or on according to the inverted storage voltage, wherein the third transmission gate has a first end coupled to the second node and a second end coupled to the third node; A second inverter, wherein the input of the second inverter is coupled to the third node, and the output of the second inverter is coupled to the first node; and The fourth transmission gate is closed or opened according to the stored voltage, wherein the first end of the fourth transmission gate is coupled to the third node, and the second end of the fourth transmission gate is coupled to the fourth node.

2. The register as described in claim 1, characterized in that, The second power supply voltage is always enabled.

3. The register as described in claim 1, characterized in that, This register operates in normal mode, save mode, or restore mode.

4. The register as described in claim 3, characterized in that, In this save mode, the data is written to the balloon latch.

5. The register as described in claim 3, characterized in that, In this recovery mode, the data is read from the balloon latch.

6. The register as described in claim 3, characterized in that, The first power supply voltage is temporarily disabled after this save mode and before this restore mode.

7. The register as claimed in claim 1, characterized in that, The level converter is either a cross-coupled level converter or a current mirror level converter.

8. The register as claimed in claim 1, characterized in that, The balloon latch also includes: A third inverter, wherein the input of the third inverter is coupled to the fifth node, and the output of the third inverter is coupled to the fourth node.

9. The register as described in claim 8, characterized in that, The level shifter includes: A first P-type transistor, wherein the first P-type transistor has a control terminal coupled to a sixth node, a first terminal coupled to the second power supply voltage, and a second terminal coupled to a seventh node; The second P-type transistor has a control terminal coupled to the fifth node, a first terminal coupled to the second power supply voltage, and a second terminal coupled to the eighth node. The third P-type transistor has a control terminal for receiving a shift voltage, a first terminal coupled to the seventh node, and a second terminal coupled to the fifth node. A fourth P-type transistor, wherein the fourth P-type transistor has a control terminal for receiving an inverted shift voltage, a first terminal coupled to the eighth node, and a second terminal coupled to the sixth node; A first N-type transistor, wherein the first N-type transistor has a control terminal for receiving the shift voltage, a first terminal coupled to ground voltage, and a second terminal coupled to the fifth node; and The second N-type transistor has a control terminal for receiving the inverted shift voltage, a first terminal coupled to the ground voltage, and a second terminal coupled to the sixth node.

10. The register as claimed in claim 1, characterized in that, The level shifter includes: A first P-type transistor, wherein the first P-type transistor has a control terminal coupled to a fifth node, a first terminal coupled to the second power supply voltage, and a second terminal coupled to a sixth node; The second P-type transistor has a control terminal coupled to the fourth node, a first terminal coupled to the second power supply voltage, and a second terminal coupled to the seventh node. The third P-type transistor has a control terminal coupled to the eighth node, a first terminal coupled to the sixth node, and a second terminal coupled to the fourth node; A fourth P-type transistor, wherein the fourth P-type transistor has a control terminal coupled to the connection node, a first terminal coupled to the seventh node, and a second terminal coupled to the fifth node; A first N-type transistor, wherein the first N-type transistor has a control terminal coupled to the eighth node, a first terminal coupled to ground voltage, and a second terminal coupled to the fourth node; and The second N-type transistor has a control terminal coupled to the connection node, a first terminal coupled to the ground voltage, and a second terminal coupled to the fifth node.

11. The register as claimed in claim 10, characterized in that, Also includes: An auxiliary circuit, coupled to the level converter, wherein the auxiliary circuit selectively pulls up the voltage at the eighth node to the second power supply voltage.

12. The register as claimed in claim 11, characterized in that, The auxiliary circuit includes: A control transistor, wherein the control transistor has a control terminal for receiving an operating voltage, a first terminal coupled to the second power supply voltage, and a second terminal coupled to the eighth node; A third inverter, wherein the input of the third inverter is coupled to the eighth node, and the output of the third inverter is coupled to the connection node; and An auxiliary transmission gate, which is closed or opened according to a stored voltage, wherein the auxiliary transmission gate has a first end coupled to the eighth node and a second end for receiving an inverted shift voltage.

13. The register as claimed in claim 1, characterized in that, This master-slave trigger includes: A fourth inverter, wherein the fourth inverter has an input terminal for receiving data voltage and an output terminal coupled to the ninth node; The fifth transmission gate is turned off or on according to the inverted clock, wherein the first end of the fifth transmission gate is coupled to the ninth node, and the second end of the fifth transmission gate is coupled to the tenth node. A first control inverter, wherein the input terminal of the first control inverter is coupled to the tenth node, and the output terminal of the first control inverter is coupled to the eleventh node; A sixth transmission gate, which is closed or opened according to a clock, wherein the sixth transmission gate has a first end coupled to the tenth node and a second end coupled to the twelfth node; and A fifth inverter, wherein the input of the fifth inverter is coupled to the eleventh node, and the output of the fifth inverter is coupled to the twelfth node.

14. The register as claimed in claim 13, characterized in that, This master-slave trigger also includes: The seventh transmission gate is closed or opened according to the clock, wherein the first end of the seventh transmission gate is coupled to the eleventh node, and the second end of the seventh transmission gate is coupled to the thirteenth node; A sixth inverter, wherein the input of the sixth inverter is coupled to the thirteenth node to receive the shift voltage, and the output of the sixth inverter is coupled to the second common node to output the inverted shift voltage; The eighth transmission gate is turned off or on according to the inverted clock, wherein the first end of the eighth transmission gate is coupled to the thirteenth node, and the second end of the eighth transmission gate is coupled to the fourteenth node; A second control inverter, wherein the input of the second control inverter is coupled to the first common node, and the output of the second control inverter is coupled to the fourteenth node; and A seventh inverter, wherein the seventh inverter has an input terminal coupled to the second common node and an output terminal for outputting an output voltage.

15. The register as claimed in claim 1, characterized in that, This master-slave trigger includes: A fourth inverter, wherein the fourth inverter has an input terminal for receiving data voltage and an output terminal coupled to the ninth node; The fifth transmission gate is turned off or on according to the inverted clock, wherein the first end of the fifth transmission gate is coupled to the ninth node, and the second end of the fifth transmission gate is coupled to the tenth node. A first NOR gate, wherein the first NOR gate has a first input terminal receiving a reset voltage, a second input terminal coupled to the tenth node, and an output terminal coupled to the eleventh node; A sixth transmission gate, which is closed or opened according to a clock, has a first end coupled to the tenth node and a second end coupled to the twelfth node; and A fifth inverter, wherein the input of the fifth inverter is coupled to the eleventh node, and the output of the fifth inverter is coupled to the twelfth node.

16. The register as claimed in claim 15, characterized in that, This master-slave trigger also includes: The seventh transmission gate is closed or opened according to the clock, wherein the first end of the seventh transmission gate is coupled to the eleventh node, and the second end of the seventh transmission gate is coupled to the thirteenth node; A sixth inverter, wherein the input of the sixth inverter is coupled to the thirteenth node to receive the shift voltage, and the output of the sixth inverter is coupled to the second common node to output the inverted shift voltage; The eighth transmission gate is turned off or on according to the inverted clock, wherein the first end of the eighth transmission gate is coupled to the thirteenth node, and the second end of the eighth transmission gate is coupled to the fourteenth node; A second NOR gate, wherein the second NOR gate has a first input coupled to a first common node, a second input for receiving the reset voltage, and an output coupled to the fourteenth node; and A seventh inverter, wherein the seventh inverter has an input terminal coupled to the second common node and an output terminal for outputting an output voltage.

17. The register as claimed in claim 1, characterized in that, This master-slave trigger includes: A fourth inverter, wherein the fourth inverter has an input terminal for receiving data voltage and an output terminal coupled to the ninth node; The fifth transmission gate is turned off or on according to the inverted clock, wherein the first end of the fifth transmission gate is coupled to the ninth node, and the second end of the fifth transmission gate is coupled to the tenth node. A first NAND gate, wherein the first NAND gate has a first input terminal for receiving a set voltage, a second input terminal coupled to a tenth node, and an output terminal coupled to an eleventh node; A sixth transmission gate, which is closed or opened according to a clock, has a first end coupled to the tenth node and a second end coupled to the twelfth node; and A fifth inverter, wherein the input of the fifth inverter is coupled to the eleventh node, and the output of the fifth inverter is coupled to the twelfth node.

18. The register as claimed in claim 17, characterized in that, This master-slave trigger also includes: The seventh transmission gate is closed or opened according to a clock, wherein the first end of the seventh transmission gate is coupled to the eleventh node, and the second end of the seventh transmission gate is coupled to the thirteenth node; A sixth inverter, wherein the input of the sixth inverter is coupled to the thirteenth node to receive the shift voltage, and the output of the sixth inverter is coupled to the second common node to output the inverted shift voltage; The eighth transmission gate is turned off or on according to the inverted clock, wherein the first end of the eighth transmission gate is coupled to the thirteenth node, and the second end of the eighth transmission gate is coupled to the fourteenth node; A second NAND gate, wherein the second NAND gate has a first input terminal coupled to the first common node, a second input terminal for receiving a set voltage, and an output terminal coupled to the fourteenth node; and A seventh inverter, wherein the seventh inverter has an input terminal coupled to the second common node and an output terminal for outputting an output voltage.

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