A current regulating circuit

Abstract

The application discloses a current regulating circuit, a first control module is arranged between the gate of a first PMOS and the gate of a second PMOS, when receiving a first closing instruction, the first control module controls the gate of the second PMOS to be connected with the gate of the first PMOS, the second PMOS is turned on, the first PMOS and the second PMOS are connected in common-gate to form a current mirror and output current; when receiving a first opening instruction, the first control module controls the second PMOS to be turned off, and the second PMOS cannot output current. When the second PMOS is turned on, the current output by the drain of the second PMOS directly flows into the output end of the current regulating circuit, the second PMOS is prevented from being affected by the on-voltage drop, so that the second PMOS stably works in a saturation region, the working condition of the second PMOS as the current mirror is met, and the stability of the current regulating circuit is ensured.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a current regulation circuit. Background Technology

[0002] In integrated circuit design, many circuits require current regulation circuits to provide a stable current. Therefore, the quality of the current regulation circuit design directly affects the performance of the integrated circuit. Current regulation circuits typically use current mirrors to adjust the output current. A current mirror usually has one input to provide a reference current and multiple parallel outputs to output the total current based on the reference current. The input circuit of the current mirror includes a reference MOSFET. Each output of the current mirror includes an output MOSFET that shares a common gate and source with the reference MOSFET, and a switching MOSFET whose source and drain are connected. The drain of the switching MOSFET serves as the output for that output. In multiple outputs, the drains of the switching MOSFETs are connected to output the final total current of the current mirror. However, due to the on-state voltage drop of the switching MOSFETs, the output MOSFETs in the current mirror are affected by the switching MOSFETs and cannot operate stably in the saturation region. This prevents the current mirror from meeting the stable operating conditions and thus affects the stability of the current regulation circuit. Summary of the Invention

[0003] The purpose of this invention is to provide a current regulation circuit that can avoid the influence of the on-state voltage drop on the second PMOS, thereby enabling the second PMOS to operate stably in the saturation region, satisfying the operating conditions for the second PMOS to operate stably as a current mirror, and ensuring the stability of the current regulation circuit.

[0004] To solve the above-mentioned technical problems, the present invention provides a current regulation circuit, including a reference current supply module, a first PMOS and N first output modules, each of the first output modules including a second PMOS and a first control module, where N is a positive integer;

[0005] The output terminal of the reference current providing module is connected to the drain of the first PMOS, and is used to provide the first PMOS with a reference current flowing from the drain of the first PMOS to the output terminal of the reference current providing module.

[0006] The source of the first PMOS and the first terminals of the N first output modules are all connected to the first power supply. The gate of the first PMOS is connected to the drain of the first PMOS and the second terminals of the N first output modules respectively. The third terminals of the N first output modules are connected and the common terminal of the connection is used as the output terminal of the current regulation circuit.

[0007] The first terminal of the first control module serves as the second terminal of the first output module, the source of the second PMOS serves as the first terminal of the first output module, the second terminal of the first control module is connected to the gate of the second PMOS, and the drain of the second PMOS serves as the third terminal of the first output module.

[0008] The first control module is used to control the gate of the second PMOS to connect with the gate of the first PMOS to control the second PMOS to be turned on when a first closing command is received, and to control the second PMOS to be turned off when a first closing command is received.

[0009] Preferably, the reference current providing module includes a first NMOS and a second NMOS;

[0010] The drain of the first NMOS serves as the input terminal of the reference current providing module. The drain of the first NMOS is connected to the gate of the first NMOS and the gate of the second NMOS, respectively. The source of the first NMOS is grounded and connected to the source of the second NMOS. The drain of the second NMOS is connected to the drain of the first PMOS. This is used to provide a reference current to the first PMOS, which flows from the drain of the first PMOS to the output terminal of the reference current providing module, based on the reference current.

[0011] Preferably, the first control module includes a third PMOS and a fourth PMOS;

[0012] The source of the third PMOS serves as the first terminal of the first control module, the source of the fourth PMOS is connected to the first power supply, the drain of the third PMOS is connected to the drain of the fourth PMOS and the common terminal of the connection serves as the second terminal of the first control module, the gate of the third PMOS is used to turn on when receiving a first low level and turn off when receiving a first high level; the gate of the fourth PMOS is used to turn off when receiving a second high level and close when receiving a second low level.

[0013] The first closing instruction includes the first low level and the second high level, and the first opening instruction includes the first high level and the second low level.

[0014] Preferably, it further includes a reference current providing module, the output terminal of which is connected to the drain of the first NMOS, for providing the reference current.

[0015] Preferably, the reference current providing module includes an operational amplifier, a fifth PMOS, and a resistor. The inverting input of the operational amplifier is connected to a second power supply. The non-inverting input of the operational amplifier is connected to the first end of the resistor, and the common terminal of the connection is connected to the drain of the fifth PMOS. The second end of the resistor is grounded and serves as the output of the reference current providing module. The output of the operational amplifier is connected to the gate of the fifth PMOS, and the source of the fifth PMOS is connected to a third power supply.

[0016] Preferably, the aspect ratio of the first NMOS is the same as that of the second NMOS.

[0017] Preferably, the width-to-length ratio of the first PMOS is the same as that of the second PMOS.

[0018] Preferably, it also includes N second output modules, each of which includes a third NMOS and a second control module;

[0019] The first terminals of all N second output modules are grounded, the second terminals of all N second output modules are connected to the gate of the second NMOS, and the third terminals of all N second output modules are connected to the third terminals of all N first output modules, with the common terminal of the connection serving as the output terminal of the current regulation circuit.

[0020] The first terminal of the second control module serves as the second terminal of the second output module, the source of the third NMOS serves as the first terminal of the second output module, the second terminal of the second control module is connected to the gate of the third NMOS, and the drain of the third NMOS serves as the third terminal of the second output module.

[0021] The second control module is used to control the gate of the third NMOS to be connected to the gate of the second NMOS to control the third NMOS to be turned on when a second closing command is received, and to control the third NMOS to be turned off when a second closing command is received.

[0022] Preferably, the second control module includes a fourth NMOS and a fifth NMOS;

[0023] The source of the fourth NMOS serves as the first terminal of the second control module, the source of the fifth NMOS is grounded, and the common terminal of the connection between the drain of the fourth NMOS and the drain of the fifth NMOS serves as the second terminal of the second control module. The gate of the fourth NMOS is used to turn on when receiving a third high level and turn off when receiving a third low level; the gate of the fifth NMOS is used to turn off when receiving a fourth low level and turn on when receiving a fourth high level.

[0024] The second closing instruction includes the third high level and the fourth low level, and the second opening instruction includes the third low level and the fourth high level.

[0025] Preferably, the aspect ratio of the third NMOS is the same as that of the second NMOS.

[0026] This invention provides a current regulation circuit. A first control module is positioned between the gate of a first PMOS and the gate of a second PMOS. When the first control module receives a first closing command, it controls the gate of the second PMOS to connect with the gate of the first PMOS, turning the second PMOS on. The first and second PMOS then form a current mirror by sharing a common gate and source, and output current. When the first control module receives a first closing command, it controls the second PMOS to turn off, preventing it from outputting current. When the second PMOS is on, the current output from its drain flows directly into the output terminal of the current regulation circuit, avoiding the influence of the on-state voltage drop. This allows the second PMOS to operate stably in the saturation region, satisfying the stable operating conditions for the second PMOS as a current mirror and ensuring the stability of the current regulation circuit. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of a current regulation circuit provided by the present invention;

[0029] Figure 2 A schematic diagram of another current regulation circuit provided by the present invention. Detailed Implementation

[0030] The core of this invention is to provide a current regulation circuit that can avoid the second PMOS being affected by the on-state voltage drop, thereby enabling the second PMOS to operate stably in the saturation region, satisfying the operating conditions for the second PMOS to operate stably as a current mirror, and ensuring the stability of the current regulation circuit.

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] Please refer to Figure 1 , Figure 1 The present invention provides a schematic diagram of a current regulation circuit, which includes a reference current supply module 11, a first PMOS 12 and N first output modules 13, each first output module 13 including a second PMOS 131 and a first control module 132, where N is a positive integer.

[0033] The output terminal of the reference current providing module 11 is connected to the drain of the first PMOS 12, and is used to provide the first PMOS 12 with a reference current flowing from the drain of the first PMOS 12 to the output terminal of the reference current providing module 11.

[0034] The source of the first PMOS 12 and the first terminals of the N first output modules 13 are all connected to the first power supply. The gate of the first PMOS 12 is connected to the drain of the first PMOS 12 and the second terminals of the N first output modules 13 respectively. The third terminals of the N first output modules 13 are connected and the common terminal of the connection is used as the output terminal of the current regulation circuit.

[0035] The first terminal of the first control module 132 serves as the second terminal of the first output module 13, the source of the second PMOS 131 serves as the first terminal of the first output module 13, the second terminal of the first control module 132 is connected to the gate of the second PMOS 131, and the drain of the second PMOS 131 serves as the third terminal of the first output module 13.

[0036] The first control module 132 is used to control the gate of the second PMOS 131 to connect with the gate of the first PMOS 12 to control the second PMOS 131 to be turned on when a first closing command is received, and to control the second PMOS 131 to be turned off when a first closing command is received.

[0037] In the prior art, due to the on-state voltage drop of the switching MOSFET, the drain voltage of the output MOSFET in the current mirror is affected by the on-state voltage drop of the switching MOSFET. The drain voltage of the output MOSFET affects whether the output MOSFET can operate stably in the saturation region. If the output MOSFET cannot operate stably in the saturation region, the operating conditions for the stable operation of the current mirror cannot be met, which in turn affects the stability of the current regulation circuit.

[0038] To solve the above-mentioned technical problems, this application provides a current regulation circuit, which uses a common-gate common-source first PMOS12 and a second PMOS131 to form a current mirror. A first control module 132 is set between the gate of the first PMOS12 and the gate of the second PMOS131 to control the second PMOS131 to turn on or off. Thus, the drain voltage of the second PMOS131 is not affected by the on-state voltage drop, that is, the second PMOS131 can operate stably in the saturation region, thereby achieving the purpose of regulating the output current of the current regulation circuit.

[0039] Specifically, the drain of the first PMOS 12 is connected to the output terminal of the reference current providing module 11, which provides a reference current to the first PMOS 12. When the first PMOS 12 is turned on, its drain outputs a reference current. Since the second PMOS 131 shares a common gate and source with the first PMOS 12, after the first control module 132 receives the first closing command and controls the gate of the second PMOS 131 to connect with the gate of the first PMOS 12, the second PMOS 131 turns on. The direction of the current output from the drain of the second PMOS 131 is consistent with the direction of the current output from the drain of the first PMOS 12, i.e., the reference current, and its magnitude is proportional to the ratio of the width-to-length ratio of the second PMOS 131 to that of the first PMOS 12. The output current of the current regulation circuit is the vector sum of the currents output from the drain of the second PMOS 131 when it is in the turned-on state. If the width-to-length ratio of the first PMOS12 is the same as that of the second PMOS131, then the output current of the current regulation circuit is M times the reference current, where M is the number of second PMOS131s in the on state.

[0040] In summary, this invention provides a current regulation circuit. A first control module 132 is disposed between the gate of the first PMOS 12 and the gate of the second PMOS 131. When the first control module 132 receives a first closing command, it controls the gate of the second PMOS 131 to connect with the gate of the first PMOS 12, turning on the second PMOS 131. The first PMOS 12 and the second PMOS 131 form a current mirror with a common gate and common source and output current. When the first closing command is received, it controls the second PMOS 131 to turn off, preventing the second PMOS 131 from outputting current. When the second PMOS 131 is on, the current output from the drain of the second PMOS 131 flows directly into the output terminal of the current regulation circuit, avoiding the influence of the on-state voltage drop on the second PMOS 131. This allows the second PMOS 131 to operate stably in the saturation region, satisfying the operating conditions for the second PMOS 131 to operate stably as a current mirror, thus ensuring the stability of the current regulation circuit.

[0041] Based on the above embodiments:

[0042] In a preferred embodiment, the reference current providing module 11 includes a first NMOS and a second NMOS;

[0043] The drain of the first NMOS serves as the input terminal of the reference current supply module 11. The drain of the first NMOS is connected to the gate of the first NMOS and the gate of the second NMOS, respectively. The source of the first NMOS is grounded and connected to the source of the second NMOS. The drain of the second NMOS is connected to the drain of the first PMOS 12, which is used to provide a reference current to the first PMOS 12 from the drain of the first PMOS 12 to the output terminal of the reference current supply module 11 according to the reference current.

[0044] In this embodiment, a reference current providing module 11 is composed of a first NMOS and a second NMOS. The sources of both the first and second NMOS are grounded. The gates of the first and second NMOS are connected, and their common terminal is connected to the drain of the first NMOS. Based on this connection method, the conduction conditions of the first and second NMOS are satisfied, and the first and second NMOS form a common-gate, common-source current mirror. The drain of the first NMOS serves as the input terminal of the reference current providing module 11, inputting a reference current. The drain of the second NMOS is connected to the drain of the first PMOS 12, providing a reference current flowing from the drain of the first PMOS 12 to the output terminal of the reference current providing module 11 according to the reference current. Since the first and second NMOS form a common-gate, common-source current mirror, the direction of the reference current is consistent with the direction of the reference current, and its magnitude is proportional to the ratio of the width-to-length ratio of the first NMOS to the width-to-length ratio of the second NMOS. If the width-to-length ratio of the first NMOS is the same as that of the second NMOS, then the magnitude and direction of the reference current are the same as those of the standard current. Furthermore, the reference current providing module 11 in this embodiment has the advantages of simple structure and ease of implementation.

[0045] In a preferred embodiment, the first control module 132 includes a third PMOS and a fourth PMOS;

[0046] The source of the third PMOS serves as the first terminal of the first control module 132. The source of the fourth PMOS is connected to the first power supply. The drains of the third PMOS and the fourth PMOS are connected, and their common terminal serves as the second terminal of the first control module 132. The gate of the third PMOS is used to turn on when receiving a first low level and turn off when receiving a first high level. The gate of the fourth PMOS is used to turn off when receiving a second high level and close when receiving a second low level.

[0047] The first closing instruction includes a first low level and a second high level, and the first opening instruction includes a first high level and a second low level.

[0048] In this embodiment, the first control module 132 is composed of the third PMOS and the fourth PMOS. Specifically, when the first control module 132 wants to control the second PMOS 131 to turn on: since the source of the third PMOS is connected to the gate of the first PMOS 12 as the first terminal of the first control module 132, when the gate of the third PMOS receives the first low level, the conduction condition of the first PMOS 12 is satisfied, causing the first PMOS 12 to turn on. This further causes the gate of the second PMOS 131 to connect with the gate of the first PMOS 12, causing the second PMOS 131 to turn on and output current as a current mirror with the first PMOS 12 sharing the same gate and source, thereby achieving the purpose of adjusting the output current of the current regulation circuit.

[0049] When the first control module 132 wants to control the second PMOS 131 to turn off: the gate of the third PMOS receives the first high level, which does not meet the conduction condition of the third PMOS, so the third PMOS turns off, thereby disconnecting the gate of the second PMOS 131 from the first PMOS 12. However, due to the high gate impedance of the MOS transistor, even if the gate of the second PMOS 131 is disconnected from the first PMOS 12, the gate of the second PMOS 131 will still maintain the potential when it is on, causing the drain of the second PMOS 131 to still output current. Based on the above reasons, this application provides a fourth PMOS. The fourth PMOS turns on when it receives the second low level, so that the gate of the second PMOS 131 is connected to the power supply, thereby making the potential of the gate of the second PMOS 131 equal to the potential of the source equal to the power supply voltage. Therefore, the second PMOS 131 no longer meets the conduction condition, and the second PMOS 131 turns off and no longer outputs current.

[0050] In summary, the first control module 132 in this embodiment is composed of the third PMOS and the fourth PMOS, which has a simple structure and reliable operation.

[0051] In a preferred embodiment, a reference current providing module is also included, the output of which is connected to the drain of the first NMOS to provide a reference current.

[0052] In this embodiment, a reference current supply module is connected to the drain of the first NMOS, so that the current regulation circuit can adjust the output current of the current regulation circuit based on the reference current without the need to connect external devices.

[0053] In a preferred embodiment, the reference current providing module includes an operational amplifier, a fifth PMOS, and a resistor. The inverting input of the operational amplifier is connected to a second power supply. The non-inverting input of the operational amplifier is connected to the first end of the resistor, and the common terminal of the connection is connected to the drain of the fifth PMOS. The second end of the resistor is grounded and serves as the output of the reference current providing module. The output of the operational amplifier is connected to the gate of the fifth PMOS, and the source of the fifth PMOS is connected to a third power supply.

[0054] This embodiment provides a specific structure of a reference current providing module. The magnitude of the reference current provided by the reference current providing module is the voltage value of the second power supply divided by the resistance value of the resistor, and the direction of the reference current is from the output terminal of the reference current providing module to the drain of the first NMOS.

[0055] In a preferred embodiment, the aspect ratio of the first NMOS is the same as that of the second NMOS.

[0056] The current after the MOSFET is turned on is (V GS -V TH ) 2 (W / L), where V GS V is the turn-on voltage of the MOSFET. TH Where V is the threshold voltage of the MOSFET, and W / L is the width-to-length ratio of the MOSFET. If the V of each MOSFET... GS and V TH If the width and length ratios are the same, then the ratio of the currents after each MOSFET is turned on is equal to the ratio of the width and length ratios of each MOSFET. Based on the above principle, in this embodiment, a first NMOS and a second NMOS with the same width and length ratio are selected. Therefore, the current after the second NMOS is turned on is equal to the current after the first NMOS is turned on, making the adjustment of the output current of the current regulation circuit more intuitive and simple, and the circuit structure is simple and easy to implement.

[0057] In a preferred embodiment, the aspect ratio of the first PMOS 12 is the same as that of the second PMOS 131.

[0058] The current after the MOSFET is turned on is (V GS -V TH ) 2 (W / L), where V GS V is the turn-on voltage of the MOSFET. TH Where V is the threshold voltage of the MOSFET, and W / L is the width-to-length ratio of the MOSFET. If the V of each MOSFET... GS and V THIf the width and length ratios are the same, then the ratio of the currents after each MOS transistor is turned on is equal to the ratio of the width and length ratios of each MOS transistor. Based on the above principle, in this embodiment, the first PMOS12 and the second PMOS131 with the same width and length ratio are selected. Then, the current after the second PMOS131 is turned on is equal to the current after the first PMOS12 is turned on, making it more intuitive and simple to adjust the output current of the current adjustment circuit, and the circuit structure is simple and easy to implement.

[0059] In a preferred embodiment, it further includes N second output modules 21, each second output module 21 including a third NMOS 213 and a second control module 212;

[0060] The first terminals of N second output modules 21 are all grounded, the second terminals of N second output modules 21 are all connected to the gate of the second NMOS, and the third terminals of N second output modules 21 are connected to the third terminals of N first output modules 13, with the common terminal of the connection serving as the output terminal of the current regulation circuit.

[0061] The first terminal of the second control module 212 serves as the second terminal of the second output module 21, the source of the third NMOS 213 serves as the first terminal of the second output module 21, the second terminal of the second control module 212 is connected to the gate of the third NMOS 213, and the drain of the third NMOS 213 serves as the third terminal of the second output module 21.

[0062] The second control module 212 is used to control the gate of the third NMOS 213 to connect with the gate of the second NMOS when receiving the second closing command, so as to control the third NMOS 213 to be turned on, and to control the third NMOS 213 to be turned off when receiving the second closing command.

[0063] In this embodiment, a common-gate, common-source third NMOS 213 and a second NMOS are used to form a current mirror. A second control module 212 is set between the gate of the third NMOS 213 and the gate of the second NMOS to control the third NMOS 213 to turn on or off. Thus, the drain voltage of the third NMOS 213 is not affected by the on-state voltage drop, that is, the third NMOS 213 can work stably in the saturation region, thereby achieving the purpose of adjusting the output current of the current regulation circuit.

[0064] Specifically, since the third NMOS 213 shares a common gate and source with the second NMOS, after the second control module 212 receives the second closing command and controls the gate of the third NMOS 213 to connect with the gate of the second NMOS, the third NMOS 213 turns on. The direction of the drain current output of the third NMOS 213 is consistent with the direction of the drain current output of the second NMOS, i.e., the reference current, and its magnitude is proportional to the ratio of the width-to-length ratio of the second NMOS to the width-to-length ratio of the third NMOS 213. The output current of the current regulation circuit is the vector sum of the drain current output of the second PMOS 131 in the on state and the drain current output of the third NMOS 213 in the on state. If the width-to-length ratio of the first PMOS12 is the same as that of the second PMOS131, and the width-to-length ratio of the second NMOS is the same as that of the third NMOS213, then the output current of the current regulation circuit is X times the reference current, where X is the number of second PMOS131s in the on state plus the number of third NMOS213s in the on state.

[0065] In a preferred embodiment, the second control module 212 includes a fourth NMOS and a fifth NMOS;

[0066] The source of the fourth NMOS serves as the first terminal of the second control module 212, the source of the fifth NMOS is grounded, the drains of the fourth and fifth NMOS are connected and their common terminal serves as the second terminal of the second control module 212, the gate of the fourth NMOS is used to turn on when receiving a third high level and turn off when receiving a third low level; the gate of the fifth NMOS is used to turn off when receiving a fourth low level and turn on when receiving a fourth high level.

[0067] The second closing instruction includes a third high level and a fourth low level, and the second opening instruction includes a third low level and a fourth high level.

[0068] Figure 2 A schematic diagram of another current regulation circuit provided by the present invention.

[0069] In this embodiment, the second control module 212 is composed of the fourth NMOS and the fifth NMOS. Specifically, when the second control module 212 needs to control the third NMOS 213 to turn on: since the source of the fourth NMOS is connected to the gate of the second NMOS as the first terminal of the second control module 212, when the gate of the fourth NMOS receives the third high level, the conduction condition of the fourth NMOS is met, causing the fourth NMOS to turn on. This further connects the gate of the second NMOS to the gate of the third NMOS 213, causing the third NMOS 213 to turn on and act as a current mirror with the second NMOS sharing the same gate and source, thereby achieving the purpose of adjusting the output current of the current regulation circuit.

[0070] When the second control module 212 wants to control the third NMOS 213 to turn off: the gate of the fourth NMOS receives the third low level, which does not meet the conduction condition of the fourth NMOS, so the fourth NMOS turns off, thereby disconnecting the gate of the third NMOS 213 from the gate of the second NMOS. However, since the gate impedance of the MOS is very high, even if the gate of the third NMOS 213 is disconnected from the gate of the second NMOS, the gate of the third NMOS 213 will still maintain the potential when it is on, causing the drain of the third NMOS 213 to still output current. Based on the above reasons, this application sets a fifth NMOS. The fifth NMOS turns on when it receives the fourth high level, so that the potential of the gate of the third NMOS 213 is equal to the potential of the source, which no longer meets the conduction condition, so the third NMOS 213 turns off and no longer outputs current.

[0071] In summary, the first control module 132 in this embodiment is composed of the fourth NMOS and the fifth NMOS, which has a simple structure and reliable operation.

[0072] In a preferred embodiment, the aspect ratio of the third NMOS213 is the same as that of the second NMOS.

[0073] In this embodiment, a third NMOS213 and a second NMOS with the same width-to-length ratio are selected. The current after the third NMOS213 is turned on is equal to the current after the second NMOS is turned on, making it more intuitive and simple to adjust the output current of the current adjustment circuit, and the circuit structure is simple and easy to implement.

[0074] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0075] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A current regulating circuit, characterized by, The current regulating circuit comprises a reference current providing module, a first PMOS and N first output modules, each of the first output modules comprises a second PMOS and a first control module, N is a positive integer; The output end of the reference current providing module is connected with the drain of the first PMOS, for providing a reference current flowing from the drain of the first PMOS to the output end of the reference current providing module for the first PMOS; The source of the first PMOS and the first ends of the N first output modules are connected with a first power supply, the gate of the first PMOS is connected with the drain of the first PMOS and the second ends of the N first output modules respectively, and the third ends of the N first output modules are connected and the common end connected with the third ends is used as an output end of the current regulating circuit; The first end of the first control module is used as the second end of the first output module, the source of the second PMOS is used as the first end of the first output module, the second end of the first control module is connected with the gate of the second PMOS, and the drain of the second PMOS is used as the third end of the first output module; The first control module is used for controlling the gate of the second PMOS to be connected with the gate of the first PMOS to control the second PMOS to be turned on when a first closing instruction is received, and controlling the second PMOS to be turned off when a first opening instruction is received.

2. The current regulating circuit of claim 1, wherein, The reference current providing module comprises a first NMOS and a second NMOS; The drain of the first NMOS is used as an input end of the reference current providing module, the drain of the first NMOS is connected with the gate of the first NMOS and the gate of the second NMOS respectively, the source of the first NMOS is grounded and connected with the source of the second NMOS, and the drain of the second NMOS is connected with the drain of the first PMOS, for providing a reference current flowing from the drain of the first PMOS to the output end of the reference current providing module for the first PMOS according to a reference current.

3. The current regulating circuit of claim 2, wherein, The first control module comprises a third PMOS and a fourth PMOS; The source of the third PMOS is used as the first end of the first control module, the source of the fourth PMOS is connected with the first power supply, the drain of the third PMOS is connected with the drain of the fourth PMOS and the common end connected with the drains is used as the second end of the first control module, and the gate of the third PMOS is used for being turned on when a first low level is received and being turned off when a first high level is received; the gate of the fourth PMOS is used for being turned off when a second high level is received and being closed when a second low level is received; The first closing instruction comprises the first low level and the second high level, and the first opening instruction comprises the first high level and the second low level.

4. The current regulating circuit of claim 2, wherein, The current regulating circuit further comprises a reference current providing module, and the output end of the reference current providing module is connected with the drain of the first NMOS, for providing the reference current.

5. The current regulating circuit of claim 4, wherein, The reference current providing module comprises an operational amplifier, a fifth PMOS and a resistor, the inverting input terminal of the operational amplifier is connected with a second power supply, the non-inverting input terminal of the operational amplifier is connected with a first terminal of the resistor, and a common terminal connected with the first terminal is connected with the drain of the fifth PMOS, a second terminal of the resistor is grounded and serves as an output terminal of the reference current providing module, the output terminal of the operational amplifier is connected with the gate of the fifth PMOS, and the source of the fifth PMOS is connected with a third power supply.

6. The current regulating circuit of claim 2, wherein, The width-length ratio of the first NMOS is the same as that of the second NMOS.

7. The current regulating circuit of claim 6, wherein, The width-length ratio of the first PMOS is the same as that of the second PMOS.

8. A current regulating circuit as claimed in any one of claims 2 to 7, characterized in that, The current regulating circuit further comprises N second output modules, each of which comprises a third NMOS and a second control module. The first terminals of the N second output modules are all grounded, the second terminals of the N second output modules are all connected with the gates of the second NMOS, the third terminals of the N second output modules are connected with the third terminals of the N first output modules, and a common terminal connected with the third terminals serves as an output terminal of the current regulating circuit. The first terminal of the second control module serves as the second terminal of the second output module, the source of the third NMOS serves as the first terminal of the second output module, the second terminal of the second control module is connected with the gate of the third NMOS, and the drain of the third NMOS serves as the third terminal of the second output module. The second control module is configured to control the gate of the third NMOS to be connected with the gate of the second NMOS to control the third NMOS to be turned on when a second closing instruction is received, and control the third NMOS to be turned off when a second opening instruction is received.

9. The current regulating circuit of claim 8, wherein, The second control module comprises a fourth NMOS and a fifth NMOS. The source of the fourth NMOS serves as the first terminal of the second control module, the source of the fifth NMOS is grounded, the drain of the fourth NMOS is connected with the drain of the fifth NMOS, and a common terminal connected with the drains serves as the second terminal of the second control module, the gate of the fourth NMOS is configured to be turned on when a third high level is received and turned off when a third low level is received, and the gate of the fifth NMOS is configured to be turned off when a fourth low level is received and turned on when a fourth high level is received. The second closing instruction comprises the third high level and the fourth low level, and the second opening instruction comprises the third low level and the fourth high level.

10. The current regulating circuit of claim 8, wherein, The width-length ratio of the third NMOS is the same as that of the second NMOS.

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