A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductor, and is used for simplifying the manufacturing process of a three-dimensional stacked complementary transistor, reducing the manufacturing difficulty of the three-dimensional stacked complementary transistor, and further improving the working performance of the three-dimensional stacked complementary transistor. The semiconductor device comprises a semiconductor substrate, a first ring-gate transistor and a second ring-gate transistor. The first ring-gate transistor is formed on the semiconductor substrate. The material of a channel region of the first ring-gate transistor is single-crystal semiconductor material. The second ring-gate transistor is formed above the first ring-gate transistor and is arranged in a spaced mode with the first ring-gate transistor. The material of a channel region of the second ring-gate transistor is polycrystal semiconductor material. The second ring-gate transistor and the first ring-gate transistor constitute a three-dimensional stacked complementary transistor. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Three-dimensional stacked complementary transistors consist of vertically stacked N-type and P-type transistors, eliminating the lateral spacing between them. This allows for a further increase in the effective channel width, thereby improving the performance and integration of semiconductor devices.

[0003] However, the existing manufacturing process of three-dimensional stacked complementary transistors is relatively complicated and has high requirements for processing technology, which makes it difficult to manufacture three-dimensional stacked complementary transistors and is not conducive to improving the working performance of three-dimensional stacked complementary transistors. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which simplifies the manufacturing process of three-dimensional stacked complementary transistors, reduces the manufacturing difficulty of three-dimensional stacked complementary transistors, and thus helps to improve the working performance of three-dimensional stacked complementary transistors.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a semiconductor device comprising: a semiconductor substrate, a first ring gate transistor, and a second ring gate transistor.

[0006] The first gate-ring transistor is formed on a semiconductor substrate. The channel region of the first gate-ring transistor is made of a single-crystal semiconductor material. The second gate-ring transistor is formed above the first gate-ring transistor and spaced apart from it. The channel region of the second gate-ring transistor is made of a polycrystalline semiconductor material. The second gate-ring transistor and the first gate-ring transistor constitute a three-dimensional stacked complementary transistor.

[0007] When using the above technical solution, single-crystal semiconductor materials have higher conductivity than polycrystalline semiconductor materials. Therefore, when the channel region of the first gate-ring transistor in the three-dimensional stacked complementary transistor is made of single-crystal semiconductor material, the on-resistance of the first gate-ring transistor can be reduced, which is beneficial to improving the electrical performance of the first gate-ring transistor. Furthermore, the channel region of the second gate-ring transistor formed above the first gate-ring transistor is made of polycrystalline semiconductor material. Based on this, in practical applications, polycrystalline semiconductor materials can be formed by depositing amorphous semiconductor materials and then performing low-temperature annealing on the amorphous semiconductor materials. In other words, after forming at least the first gate-ring transistor and the interlayer dielectric layer that isolates the first gate-ring transistor from the second gate-ring transistor, a patterned structure (including at least the first dielectric layer and an amorphous semiconductor layer) for fabricating the channel region of the second gate-ring transistor can be directly formed on the interlayer dielectric layer using a deposition process. The polycrystalline semiconductor layer for the channel region can then be obtained through a low-temperature annealing process. This eliminates the need for the complex existing sequential integration method of bonding a semiconductor substrate to the underlying first gate-ring transistor and integrating the second gate-ring transistor on that substrate, thus reducing the manufacturing difficulty of three-dimensional stacked complementary transistors. Furthermore, unlike existing monolithic integration methods, it eliminates the need to simultaneously process the corresponding film layers for fabricating the first and second gate-ring transistors, reducing the aspect ratio when fabricating the first and second gate-ring transistors separately, and further reducing the manufacturing difficulty of three-dimensional stacked complementary transistors. In addition, it eliminates the need for multiple etching and epitaxial processes to form the source and drain regions of the first and second gate ring transistors, simplifying the manufacturing process of the three-dimensional stacked complementary transistor and improving its performance.

[0008] Secondly, the present invention also provides a method for manufacturing a semiconductor device, the method comprising:

[0009] First, a semiconductor substrate is provided.

[0010] Next, a first gate-ring transistor is formed on the semiconductor substrate. The channel region of the first gate-ring transistor is made of a single-crystal semiconductor material.

[0011] Next, a second ring-gate transistor is formed, positioned above and spaced apart from the first ring-gate transistor. The source, drain, and channel regions of the second ring-gate transistor are all made of polycrystalline semiconductor material. The second ring-gate transistor and the first ring-gate transistor constitute a three-dimensional stacked complementary transistor.

[0012] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0014] Figure 1 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 1 ;

[0015] Figure 2 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 ;

[0016] Figure 3 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 3 ;

[0017] Figure 4 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 4 ;

[0018] Figure 5 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 5 ;

[0019] Figure 6 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 6 ;

[0020] Figure 7 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 7 ;

[0021] Figure 8 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 8 ;

[0022] Figure 9 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 9 ;

[0023] Figure 10 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 ;

[0024] Figure 11A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 one;

[0025] Figure 12 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 two;

[0026] Figure 13 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 three;

[0027] Figure 14 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 Four;

[0028] Figure 15 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 five;

[0029] Figure 16 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 six;

[0030] Figure 17 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 seven;

[0031] Figure 18 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Eight and Figure 10 Nine;

[0032] Figure 19 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 ten;

[0033] Figure 20 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 eleven;

[0034] Figure 21 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 twelve;

[0035] Figure 22 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 Thirteen;

[0036] Figure 23A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 fourteen.

[0037] Reference numerals: 11 Interlayer dielectric layer, 12 Etch stop layer, 13 First dielectric material layer, 14 Amorphous semiconductor material layer, 15 Fin structure, 16 Source formation region, 17 Drain formation region, 18 Channel formation region, 19 Pattern structure, 20 First dielectric layer, 21 Channel formation layer, 22 Amorphous semiconductor layer, 23 Sacrificial gate, 24 Sidewall, 25 Source region, 26 Drain region, 27 Polycrystalline semiconductor layer, 28 Dielectric layer, 29 Channel region, 30 Nanostructure, 31 Gate stack structure, 32 Second dielectric material layer, 33 Second dielectric layer, 34 Channel formation space, 35 Amorphous semiconductor material, 36 Amorphous semiconductor capping layer, 37 Mask layer, 38 Nanowire / wafer. Detailed Implementation

[0038] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0039] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0040] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0042] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0043] Three-dimensional stacked complementary transistors consist of vertically stacked N-type and P-type transistors, eliminating the lateral spacing between them. This allows for a further increase in the effective channel width, thereby improving the performance and integration of semiconductor devices.

[0044] However, the existing manufacturing process for three-dimensional stacked complementary transistors (3D complementary transistors) is relatively complex and requires advanced processing techniques, making it difficult to manufacture and hindering the improvement of their performance. The existing manufacturing methods for 3D complementary transistors mainly include the following two integration schemes:

[0045] The first method involves fabricating a three-dimensional stacked complementary transistor using a monolithic approach. Specifically, taking an example where both the N-type and P-type transistors are gate-around transistors, with the P-type transistor positioned above the N-type transistor, the process of fabricating a three-dimensional stacked complementary transistor using existing methods is explained: First, a fin structure is formed on a semiconductor substrate. This fin structure comprises at least two stacked layers. Each stack includes a sacrificial layer and a channel layer located on the sacrificial layer, and both the sacrificial layer and the channel layer are made of semiconductor materials. Next, a sacrificial gate and sidewalls are formed across a portion of the fin structure. Using the sacrificial gate and sidewalls as a mask, the fin structure is selectively etched to remove the portion of the fin structure exposed outside the sacrificial gate and sidewalls. Then, a first semiconductor material for fabricating the source and drain regions of the N-type transistor is formed on the semiconductor substrate. At this point, since the remaining portions of the sacrificial layers and channel layers corresponding to the N-type and P-type transistors are exposed after etching, these remaining portions can serve as seed layers for the epitaxial growth of the first semiconductor material. Therefore, the first semiconductor material is formed not only on both sides of the remaining portions of the sacrificial layers and channel layers corresponding to the N-type transistor, but also on both sides of the remaining portions of the sacrificial layers and channel layers corresponding to the P-type transistor. Next, the first semiconductor material located on both sides of the remaining portions of the sacrificial layers and channel layers corresponding to the P-type transistor needs to be removed, and the remaining portion of the first semiconductor material forms the source and drain regions included in the N-type transistor. Then, an epitaxial isolation layer is formed covering the source and drain regions included in the N-type transistor away from the substrate surface; and the source and drain regions of the P-type transistor are formed on the epitaxial isolation layer using an epitaxial growth process. Finally, the sacrificial gate and the portion of the sacrificial layer located within the gate formation region are removed; and a gate stack structure surrounding the outer periphery of the channel region is formed to obtain a three-dimensional stacked complementary transistor.

[0046] The second method involves fabricating a three-dimensional stacked complementary transistor using a sequential approach. This method involves forming the bottom layer transistor using conventional semiconductor device manufacturing processes. After forming the corresponding contact electrodes of the bottom layer transistor, a semiconductor layer is deposited on top of the bottom layer transistor using wafer-to-wafer bonding technology and a wafer transfer method. Then, the top layer transistor is integrated based on this semiconductor layer, connecting the top and bottom gates to obtain the three-dimensional stacked complementary transistor.

[0047] As can be seen from the manufacturing process of the first method described above, in order to isolate the source, drain, and channel regions of the bottom and top layer transistors, the vertical distance between the two transistors is relatively large. Therefore, this method has a relatively high aspect ratio vertical structure, which brings significant technical challenges to subsequent patterning of fin structures, sacrificial gates, gate sidewalls, and source and drain electrodes. Furthermore, the manufacturing process of the corresponding three-dimensional stacked complementary transistor is quite complex. The manufacturing process of the second method for manufacturing three-dimensional stacked complementary transistors is also quite complex and has high process requirements, resulting in greater manufacturing difficulty and hindering the improvement of the performance of the three-dimensional stacked complementary transistor.

[0048] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by these embodiments, the channel region of the first gate-ring transistor formed on the semiconductor substrate is made of a single-crystal semiconductor material, while the channel region of the second gate-ring transistor formed above the first gate-ring transistor is made of a polycrystalline semiconductor material. This simplifies the manufacturing process of the three-dimensional stacked complementary transistor, reduces its manufacturing difficulty, and improves its performance.

[0049] Firstly, such as Figure 11 and Figure 23 As shown, the semiconductor device provided in this embodiment of the invention includes: a semiconductor substrate, a first ring gate transistor, and a second ring gate transistor.

[0050] The aforementioned first gate-ring transistor is formed on a semiconductor substrate. The channel region of the first gate-ring transistor is made of a single-crystal semiconductor material. For example... Figure 11 and Figure 23 As shown, the second gate ring transistor is formed above and spaced apart from the first gate ring transistor (not shown in the figure). The channel region 29 of the second gate ring transistor is made of polycrystalline semiconductor material. The second gate ring transistor and the first gate ring transistor constitute a three-dimensional stacked complementary transistor.

[0051] Specifically, the specific structure and materials of the semiconductor substrate provided in the embodiments of the present invention can be set according to the actual application scenario, and are not specifically limited here. For example, the semiconductor substrate provided in the embodiments of the present invention can be a semiconductor substrate such as silicon, germanium-silicon, or germanium without any structure formed. Alternatively, the semiconductor substrate can also be a semiconductor substrate with some structure formed. For example, when the three-dimensional stacked complementary transistor in the embodiments of the present invention is a three-dimensional stacked complementary transistor of the second or higher layer in a semiconductor device, the semiconductor substrate includes a semiconductor structure located below the three-dimensional stacked complementary transistor, etc.

[0052] For the aforementioned first-ring-gate transistor, the first-ring-gate transistor may include a source region, a drain region, a channel region, and a gate stack structure. Structurally, the channel region of the first-ring-gate transistor is located between and in contact with the source and drain regions, respectively. The channel region of the first-ring-gate transistor may include at least one nanostructure, each nanostructure having a gap between it and the semiconductor substrate. Specifically, each nanostructure may include at least one nanowire / sheet spaced apart along the width direction of the gate stack structure of the first-ring-gate transistor. Furthermore, when the channel region of the first-ring-gate transistor includes at least two nanostructures, there is also a gap between adjacent nanostructures. The gate stack structure of the first-ring-gate transistor surrounds the outer periphery of the channel region. The gate stack structure of the first-ring-gate transistor may include a gate dielectric layer and a gate. The gate dielectric layer of the first-ring-gate transistor surrounds the outer periphery of the channel region, and the gate of the first-ring-gate transistor is formed on the gate dielectric layer.

[0053] From a material perspective, the source and drain regions of the first gate-ring transistor are made of semiconductor materials. Specifically, the source and drain regions of the first gate-ring transistor can be made of polycrystalline semiconductor materials or monocrystalline semiconductor materials. Preferably, the source and drain regions of the first gate-ring transistor are made of monocrystalline semiconductor materials to reduce the on-resistance of the source and drain regions, thereby improving the driving performance of the first gate-ring transistor. Additionally, the channel region of the first gate-ring transistor can be made of monocrystalline semiconductor materials such as monocrystalline silicon, monocrystalline germanium silicon, or monocrystalline germanium.

[0054] Regarding the materials of the gate stack structure included in the first ring-gate transistor, the material of the gate dielectric layer included in the gate stack structure of the first ring-gate transistor can be an insulating material such as HfO2, ZrO2, TiO2, or Al2O3. The material of the gate included in the gate stack structure of the first ring-gate transistor can be a conductive material such as TiN, TaN, or TiSiN.

[0055] In some cases, the first-ring gate transistor may further include a shallow trench isolation structure, sidewalls, and a dielectric layer. The shallow trench isolation structure of the first-ring gate transistor is used to isolate different active regions of the semiconductor substrate, preventing leakage. The thickness of the shallow trench isolation structure can be set according to the actual situation. The material of the shallow trench isolation structure can be an insulating material such as SiN, Si3N4, SiO2, or SiCO. The sidewalls of the first-ring gate transistor are formed at least on both sides of the gate stack structure along its own length direction to isolate the gate stack structure from other conductive structures, improving the electrical characteristics of the first-ring gate transistor. The thickness of the sidewalls located on both sides of the gate stack structure along its length direction can be the same. The material of the sidewalls of the first-ring gate transistor can be an insulating material such as silicon oxide or silicon nitride. Furthermore, the dielectric layer of the first-ring gate transistor covers the semiconductor substrate, and its top is flush with the top of the gate stack structure. In actual manufacturing, the presence of the dielectric layer in the first gate ring transistor protects the source and drain regions from subsequent operations such as removing the sacrificial gate and sacrificial layer, thereby improving the yield of the first gate ring transistor. The dielectric layer in the first gate ring transistor can be made of insulating materials such as silicon oxide or silicon nitride.

[0056] In some cases, such as Figure 1 As shown, the semiconductor device may further include an interlayer dielectric layer 11 covering the first gate ring transistor to separate the first gate ring transistor and the second gate ring transistor and prevent leakage. The material of the interlayer dielectric layer 11 may be an insulating material such as silicon oxide.

[0057] In addition, such as Figure 1 As shown, the semiconductor device described above may further include an etch stop layer 12 formed between the interlayer dielectric layer 11 and the second gate ring transistor to prevent the interlayer dielectric layer 11 from being affected during the fabrication of the second gate ring transistor, thereby improving the yield of the semiconductor device. The material of the etch stop layer 12 can be any insulating material different from that of the interlayer dielectric layer 11, as long as it can be applied to the semiconductor device provided in the embodiments of the present invention. For example, if the material of the interlayer dielectric layer 11 is silicon oxide, the material of the etch stop layer 12 can be silicon nitride.

[0058] For the aforementioned second-ring gate transistor, the second-ring gate transistor may include a source region, a drain region, a channel region, and a gate stack structure. Structurally, the channel region of the second-ring gate transistor is located between and contacts both the source and drain regions. Furthermore, as... Figure 11 and Figure 23As shown, the channel region 29 of the second gate ring transistor includes at least one layer of nanostructures 30. Specifically, when only the interlayer dielectric layer 11 is formed, each nanostructure 30 has a gap with the interlayer dielectric layer 11. When an etch stop layer 12 is formed, each nanostructure 30 has a gap with the etch stop layer 12. Furthermore, when the channel region 29 of the second gate ring transistor includes at least two layers of nanostructures 30, there is also a gap between every two adjacent nanostructures 30 in the second gate ring transistor. Secondly, as... Figure 11 As shown, each nanostructure 30 in the second gate ring transistor can be a monolithic structure. In other words, each nanostructure 30 in the second gate ring transistor is a single nanowire / sheet. Or, as... Figure 22 and Figure 23 As shown, each nanostructure 30 may also include two nanowires / sheets 38 spaced apart along a first direction. The two different nanowires / sheets 38 included in the same nanostructure 30 are aligned along the thickness direction of the semiconductor substrate. The first direction is parallel to the length direction of the gate stack structure 31 included in the second ring gate transistor. In this case, when the channel region 29 in the second ring gate transistor includes at least two nanostructures 30, the nanowires / sheets 38 in the same column included in different nanostructures 30 are aligned along the width direction of the gate stack structure 31 in the second ring gate transistor.

[0059] In addition, such as Figures 14 to 21 As shown, the source region 25 and drain region 26 of the second gate ring transistor can be integrally formed with the channel region 29 of the second gate ring transistor. Alternatively, as... Figures 1 to 10 As shown, the source region 25 and drain region 26 of the second gate ring transistor can also be formed stepwise with the channel region 29 of the second gate ring transistor in different operation steps.

[0060] The gate stack structure included in the second ring gate transistor may include a gate dielectric layer and a gate. The gate dielectric layer of the second ring gate transistor surrounds the outer periphery of the channel region included in the second ring gate transistor, and the gate of the second ring gate transistor is formed on the gate dielectric layer included in the second ring gate transistor. Furthermore, in addition to the source region 25, drain region 26, and channel region 29 included in the second ring gate transistor... Figure 20 In addition to the structure shown, such as Figures 8 to 11 As shown, the gate stack structure 31 included in the second ring gate transistor can be self-aligned with the channel region 29 included in the second ring gate transistor, so as to further reduce the manufacturing difficulty of the second ring gate transistor.

[0061] From a material perspective, the channel region of the second-ring gate transistor can be made of polycrystalline semiconductor materials such as polycrystalline silicon, polycrystalline germanium silicon, or polycrystalline germanium. The source and drain regions of the second-ring gate transistor are made of semiconductor materials. Specifically, when the source and drain regions of the second-ring gate transistor are integrally formed with the channel region, the materials of the source and drain regions are the same as the material of the channel region; that is, the materials of the source, drain, and channel regions of the second-ring gate transistor are all polycrystalline semiconductor materials. However, when the source and drain regions of the second-ring gate transistor are formed separately from the channel region in different operations, the materials of the second-ring gate transistor can be either polycrystalline or single-crystal semiconductor materials.

[0062] As for the material of the gate stack structure included in the second ring gate transistor, it can be referred to the material of the gate stack structure included in the first ring gate transistor described above, and will not be repeated here.

[0063] In terms of conductivity type, the channel region of the second gate-ring transistor can be a doped channel region doped with impurities. In this case, the doping type of the impurities in the channel region of the second gate-ring transistor can be the same as or opposite to the doping type of the source and drain regions. Specifically, when the doping type of the impurities in the channel region of the second gate-ring transistor is opposite to the doping type of the source and drain regions, the conductivity type of the channel region is opposite to the conductivity type of the source and drain regions, and the impurity doping concentration in the channel region of the second gate-ring transistor must be lower than the impurity doping concentrations in the source and drain regions, respectively.

[0064] Alternatively, the conductivity type of the channel region included in the second ring gate transistor can also be intrinsic.

[0065] As can be seen from the above, the material of the channel region in the second ring-gate transistor formed above the first ring-gate transistor is a polycrystalline semiconductor material. Based on this, in practical applications, polycrystalline semiconductor materials can be formed by depositing amorphous semiconductor materials and then performing low-temperature annealing on the amorphous semiconductor materials. In other words, as... Figures 1 to 23As shown, after forming at least the first gate-ring transistor and the interlayer dielectric layer 11 that isolates the first gate-ring transistor from the second gate-ring transistor, a pattern structure 19 (including at least the first dielectric layer 20 and an amorphous semiconductor layer 22) for fabricating the channel region 29 of the second gate-ring transistor can be directly formed on the interlayer dielectric layer 11 using a deposition process. The polycrystalline semiconductor layer 27 of the channel region 29 can then be obtained through a low-temperature annealing process. This eliminates the need for the complex existing sequential integration method of bonding a semiconductor substrate to the underlying first gate-ring transistor and integrating the second gate-ring transistor based on that substrate. Furthermore, unlike the existing monolithic integration method, it eliminates the need to simultaneously process the corresponding film layers for fabricating the first and second gate-ring transistors, reducing the aspect ratio when fabricating the first and second gate-ring transistors separately, thereby reducing the manufacturing difficulty of three-dimensional stacked complementary transistors. In addition, it eliminates the need for multiple etching and epitaxial processes to form the source region 25 and drain region 26 of the first and second gate ring transistors, respectively, simplifying the manufacturing process of the three-dimensional stacked complementary transistor and improving its performance.

[0066] In some cases, such as Figure 8 As shown, the second gate-ring transistor may further include sidewalls 24 and a dielectric layer 28. The sidewalls 24 of the second gate-ring transistor are formed at least on both sides of the gate stack structure along its length to isolate the gate stack structure from other conductive structures, thereby improving the electrical characteristics of the second gate-ring transistor. The thickness of the portions of the sidewalls 24 on both sides of the gate stack structure along its length can be the same. Furthermore, the dielectric layer 28 of the second gate-ring transistor covers the etch stop layer 12, and its top is flush with the top of the gate stack structure, to protect the source region 25 and drain region 26 of the second gate-ring transistor from subsequent operations, thereby improving the yield of the second gate-ring transistor. The materials of the dielectric layer 28 and sidewalls 24 of the second gate-ring transistor can be referenced to the materials of the dielectric layer 28 and sidewalls 24 of the first gate-ring transistor described above, and will not be repeated here.

[0067] Secondly, embodiments of the present invention also provide a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 1 to 23 The illustrated perspective or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps:

[0068] First, a semiconductor substrate is provided. The specific structure of the semiconductor substrate can be referred to in the previous text, and will not be repeated here.

[0069] Next, a first gate-ring transistor is formed on the semiconductor substrate. The channel region of the first gate-ring transistor is made of a single-crystal semiconductor material.

[0070] Specifically, the structure and materials of the first gate ring transistor can be referred to the previous text. Furthermore, the specific manufacturing process of the first gate ring transistor can be determined according to the actual application scenario. The following is a brief explanation of the manufacturing process of the first gate ring transistor, taking an example where the channel region of the first gate ring transistor consists of only one nanostructure layer, and both the source and drain regions are formed using epitaxial growth.

[0071] First, an epitaxial process can be used to form a sacrificial layer covering the semiconductor substrate and a channel layer located on the sacrificial layer. Next, photolithography and etching processes can be used to pattern the channel layer, sacrificial layer, and a portion of the semiconductor substrate to form a Fin structure; and a shallow trench isolation structure can be formed on the semiconductor substrate using deposition and etching processes. The portion of the Fin structure exposed outside the shallow trench isolation structure is called a fin. Along the length of the fin, the fin includes a first semiconductor region, a second semiconductor region, and a third semiconductor region located between the first and second semiconductor regions. Next, a sacrificial gate and sidewalls are formed across the portion of the fin corresponding to the third semiconductor region. The sidewalls are formed at least on both sides of the sacrificial gate along its length. Then, under the masking effect of the sacrificial gate and sidewalls, an etching process can be used to remove the portion of the fin corresponding to the first and second semiconductor regions; and an epitaxial process can be used to form the source and drain regions included in the first ring-gate transistor. Next, a dielectric layer covering the semiconductor substrate is formed using deposition and planarization processes, with the top of the dielectric layer flush with the top of the sacrificial layer. Finally, an etching process is used to remove the sacrificial gate and the portion of the third semiconductor region corresponding to the sacrificial layer to obtain the channel region included in the first ring gate transistor; and an atomic layer deposition process can be used to form the gate stack structure included in the first ring gate transistor to obtain the first ring gate transistor.

[0072] It should be noted that the first ring-gate transistor described above can be formed in various ways. How the first ring-gate transistor is formed is not the main feature of this invention; therefore, it is only briefly described in this specification to enable those skilled in the art to easily implement the invention. Those skilled in the art can certainly conceive of other ways to fabricate the first ring-gate transistor described above.

[0073] Next, as Figure 11 and Figure 23As shown, a second ring-gate transistor is formed above and spaced apart from the first ring-gate transistor. The source region 25, drain region 26, and channel region 29 of the second ring-gate transistor are all made of polycrystalline semiconductor material. The second ring-gate transistor and the first ring-gate transistor constitute a three-dimensional stacked complementary transistor.

[0074] Specifically, the structure and materials of the second ring gate transistor can be found in the previous text, and will not be repeated here.

[0075] For example, forming a second ring gate transistor located above and spaced apart from the first ring gate transistor may include the step of: firstly, as... Figure 2 and Figure 3 ,as well as Figure 14 and Figure 15 As shown, at least a patterned structure 19 is formed above the first ring gate transistor. The patterned structure 19 includes alternating layers of first dielectric layers 20 and channel formation layers 21 along the thickness direction of the semiconductor substrate. Of the alternating layers of first dielectric layers 20 and channel formation layers 21, the bottom layer is the first dielectric layer 20. Each channel formation layer 21 includes an amorphous semiconductor layer 22. Next, as... Figure 7 ,as well as Figure 16 and Figure 17 As shown, the amorphous semiconductor layer is subjected to low-temperature annealing to form a polycrystalline semiconductor layer 27. Next, as... Figure 10 and Figure 20 As shown, at least all the first dielectric layers included in the patterned structure are removed so that all polycrystalline semiconductor layers form the channel region 29 included in the second ring gate transistor.

[0076] In this design, the amorphous semiconductor layer included in the pattern structure is annealed at low temperature to form a polycrystalline semiconductor layer; and the polycrystalline semiconductor layer is used to form the channel region included in the second gate ring transistor. Based on this, the specific structure of the pattern structure, the number of the first dielectric layer and the channel forming layer included in the pattern structure, and the specific structure of each channel forming layer can be determined according to the structure of the channel region included in the second gate ring transistor.

[0077] Specifically, depending on the different nanostructures included in each layer of the channel region in the second-ring gate transistor, the process of forming the second-ring gate transistor can be divided into at least the following two types:

[0078] The first scenario: where each nanostructure layer in the channel region of the second-ring gate transistor is a monolithic structure, such as... Figure 3As shown, each channel forming layer 21 includes only an amorphous semiconductor layer 22. In addition, in the alternating layers of the first dielectric layer 20 and the channel forming layer 21 included in the patterned structure 19, the top layer can be either the first dielectric layer or the amorphous semiconductor layer 22.

[0079] Specifically, when an etch stop layer is formed on the interlayer dielectric layer, the material of the first dielectric layer can be any insulating material different from the etch stop layer. When no etch stop layer is formed, the material of the first dielectric layer can be any insulating material different from the interlayer dielectric layer. Furthermore, since the first dielectric layer located below each amorphous semiconductor layer serves as the formation space for the corresponding portion of the gate stack structure, the thickness of the corresponding first dielectric layer can be determined based on the dimensions of the gate stack structure included in the second ring gate transistor.

[0080] In the first case, forming a patterned structure above the first ring gate transistor may include the steps of: Figure 1 As shown, a deposition process can be used to form alternating layers of first dielectric material 13 and amorphous semiconductor material 14 above the first ring-gate transistor. Next, as... Figure 2 As shown, photolithography and etching processes can be used to pattern the alternating layers of first dielectric material and amorphous semiconductor material to form a fin structure 15. Along the length of the fin structure 15, the fin structure 15 has a source formation region 16, a drain formation region 17, and a channel formation region 18 located between the source formation region 16 and the drain formation region 17. The portion of the fin structure 15 located in the channel formation region 18 is a patterned structure 19.

[0081] In addition, in this first case, if the source region and drain region of the second ring gate transistor are formed separately from the channel region of the second ring gate transistor, then after at least forming a patterned structure above the first ring gate transistor, and before performing a low-temperature annealing treatment on the amorphous semiconductor layer, the manufacturing method of the above semiconductor device further includes the step of: Figure 4 As shown, a deposition and etching process can be used to form the sacrificial gate 23 and sidewalls 24 spanning the patterned structure. The sidewalls 24 are formed at least on both sides of the sacrificial gate 23 along its length. Figure 5 As shown, under the masking effect of the sacrificial gate 23 and the sidewall 24, an etching process can be used to remove the portion of the fin structure located in the source formation region and the drain formation region. Figure 6 As shown, the source region 25 and drain region 26 of the second ring gate transistor can be formed on both sides of the pattern structure along the length direction of the sacrificial gate 23 using processes such as epitaxy or deposition.

[0082] Next, in the first case, after forming the source and drain regions included in the second ring gate transistor, as... Figure 7As shown, each amorphous semiconductor layer undergoes low-temperature annealing to form a corresponding polycrystalline semiconductor layer 27. The temperature and time of this low-temperature annealing process can be set according to the actual application scenario and are not specifically limited here.

[0083] For example, the temperature of the above-mentioned low-temperature annealing process is greater than 0 and less than or equal to 600°C. For instance, the temperature of the low-temperature annealing process can be 200°C, 300°C, 400°C, 500°C, or 600°C, etc. In this case, the temperature of the low-temperature annealing process is within the above range, which can prevent the channel region in the first ring gate transistor from being affected by the high temperature, and ensure that the first ring gate transistor has a high yield.

[0084] For example, the annealing time for the aforementioned low-temperature annealing process can be greater than or equal to 1 hour and less than or equal to 24 hours. For instance, the annealing time for the low-temperature annealing process can be 1 hour, 5 hours, 10 hours, 15 hours, or 24 hours, etc. In this case, the low-temperature annealing time is within the aforementioned range, which can prevent the partial amorphous semiconductor layer from failing to form a polycrystalline semiconductor layer due to a short time, thus avoiding a large on-resistance in the channel region included in the second ring gate transistor, ensuring that the second ring gate transistor has good electrical performance. At the same time, it can also prevent the low-temperature annealing process from being inefficient due to a long time, which is beneficial for improving the manufacturing efficiency of the second ring gate transistor and reducing its manufacturing cost.

[0085] In the actual manufacturing process, when the aforementioned sacrificial gate is formed, after the amorphous semiconductor layer undergoes low-temperature annealing and before subsequent operations, the manufacturing method of the aforementioned semiconductor device further includes the following steps: Figure 9 As shown, the sacrificial gate can be removed using processes such as wet etching. At this point, the first dielectric layer 20 and the polycrystalline semiconductor layer 27 are exposed.

[0086] Next, as Figure 10 As shown, wet etching and other processes can be used to remove the first dielectric layer to obtain the channel region 29 included in the second gate ring transistor. Finally, as... Figure 11 As shown, a gate stack structure 31 can be formed around the channel region 29 included in the second ring gate transistor by using processes such as atomic layer deposition.

[0087] The second type: such as Figure 22 As shown, in the case where each layer of nanostructure 30 in the channel region 29 of the second ring gate transistor comprises two nanowires / sheets 38 spaced apart along the aforementioned first direction, such as Figure 15As shown, in the alternating layers of the first dielectric layer 20 and the channel forming layer 21, the top layer is the first dielectric layer 20. The patterned structure 19 also includes an amorphous semiconductor capping layer 36 formed on the top first dielectric layer 20. Furthermore, as... Figure 15 As shown, each channel forming layer 21 includes a second dielectric layer 33 and amorphous semiconductor layers 22 located on both sides of the second dielectric layer 33 along a first direction. The material of the second dielectric layer 33 is different from the material of the first dielectric layer 20. The first direction is parallel to the length direction of the gate stack structure included in the second ring gate transistor.

[0088] Specifically, in this second scenario, when an etch stop layer is formed, the material of the first dielectric layer can be the same as or different from the material of the etch stop layer. When no etch stop layer is formed, the material of the first dielectric layer can be any insulating material different from that of the interlayer dielectric layer.

[0089] Regarding the material of the second dielectric layer, when no etch stop layer is formed, the material of the second dielectric layer is any insulating material different from that of the first dielectric layer and the interlayer dielectric layer. When an etch stop layer is formed, the material of the second dielectric layer is any insulating material different from that of the first dielectric layer and the etch stop layer.

[0090] In addition, the size of the second dielectric layer can be determined based on parameters such as the thickness of the two nanowires / sheets included in the same nanostructure and the spacing between them.

[0091] In the second case, forming a patterned structure above the first ring gate transistor may include the steps of: firstly, as... Figure 12 As shown, processes such as deposition and selective etching can be used to form an alternating first dielectric layer 20 and a second dielectric material layer 32 above the first gate ring transistor. Next, as... Figure 13 As shown, an etching process can be used to selectively thin the second dielectric material layer laterally along the first direction, so that the remaining portion of each second dielectric material layer forms a corresponding second dielectric layer 33. The sidewalls of the second dielectric layer 33 are recessed inward relative to the sidewalls of the first dielectric layer 20, forming a channel formation space 34. The width of this channel formation space 34 can be determined based on the width of each nanowire / sheet. Then, as... Figure 14 and Figure 15 As shown, an amorphous semiconductor material 35 can be formed on a semiconductor substrate using a deposition process. The portion of the amorphous semiconductor material 35 filling the channel formation space constitutes the amorphous semiconductor layer 22. The portion of the amorphous semiconductor material 35 located on the top first dielectric layer 20 constitutes the amorphous semiconductor capping layer 36.

[0092] Next, as Figure 16As shown, the amorphous semiconductor layers undergo low-temperature annealing to form a corresponding polycrystalline semiconductor layer 27 for each amorphous semiconductor layer. The conditions for this low-temperature annealing process can be referred to the previous text and will not be repeated here.

[0093] It is important to note that, such as Figure 16 As shown, while the amorphous semiconductor layer undergoes low-temperature annealing, the remaining portion of the amorphous semiconductor material forms a polycrystalline semiconductor material. Here, the remaining portion of the amorphous semiconductor material refers to the portion of the amorphous semiconductor material excluding the amorphous semiconductor layer located between each pair of adjacent first dielectric layers.

[0094] In addition, in this second case, if the source and drain regions of the second gate ring transistor are integrally formed with the channel region of the second gate ring transistor, then after the amorphous semiconductor layer is subjected to low-temperature annealing and before subsequent operations, the manufacturing method of the above-mentioned semiconductor device further includes the step of: Figure 17 ,as well as Figure 18 As shown in parts (1) and (2), the polycrystalline semiconductor material corresponding to the source region 25 and drain region 26 of the second ring gate transistor is doped using processes such as diffusion or ion implantation to obtain the source region 25 and drain region 26 of the second ring gate transistor. Figure 18 Part (1) is a longitudinal cross-sectional view of the structure after the formation of the second ring gate transistor, including the source region 25 and the drain region 26, at the polycrystalline semiconductor layer 27. Figure 18 Part (2) is a longitudinal cross-sectional view of the structure after the formation of the source region 25 and drain region 26 of the second ring gate transistor at the second dielectric layer 33. Next, as... Figure 19 As shown, a mask layer 37 is formed covering the source region 25 and drain region of the second gate ring transistor. The material of this mask layer 37 can be a mask material such as silicon oxide. The formation process of this mask layer 37 can be determined based on the material of the mask layer 37. For example, when the material of the mask layer 37 is silicon oxide, processes such as deposition and etching can be used to form the mask layer 37. Next, as... Figure 20 As shown, under the masking effect of the mask layer 37, the polycrystalline semiconductor material is patterned to retain only the polycrystalline semiconductor layer 27 and the source region 25 and drain region included in the second ring gate transistor. At this time, as... Figure 20 As shown, the first dielectric layer 20 and the polycrystalline semiconductor layer 27 are exposed.

[0095] Next, as Figure 21 and Figure 22 As shown, dry etching or wet etching processes are used to remove all the first dielectric layer and all the second dielectric layer included in the pattern structure to obtain the channel region 29 included in the second ring gate transistor.

[0096] Finally, as Figure 23 As shown, a gate stack structure 31 surrounding the channel region 29 included in the second ring gate transistor can be formed using processes such as atomic layer deposition, thereby obtaining the second ring gate transistor. The structure and materials of this gate stack structure 31 can be referred to the preceding text.

[0097] It should be noted that, Figures 1 to 10 ,as well as Figures 12 to 23 The diagram only shows the interlayer dielectric layer and the corresponding structure located on the interlayer dielectric layer, and does not imply that the interlayer dielectric layer is the bottommost film layer in the semiconductor device. Figures 1 to 10 ,as well as Figures 12 to 23 This is a schematic diagram omitting the structure located below the interlayer dielectric layer.

[0098] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0099] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0100] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate; A first gate-ring transistor is formed on the semiconductor substrate; the channel region of the first gate-ring transistor is made of a single-crystal semiconductor material. A second ring gate transistor is formed above the first ring gate transistor and spaced apart from the first ring gate transistor; the channel region of the second ring gate transistor is made of polycrystalline semiconductor material; the second ring gate transistor and the first ring gate transistor constitute a three-dimensional stacked complementary transistor. An interlayer dielectric layer is disposed between the first gate ring transistor and the second gate ring transistor; The interlayer dielectric layer covers the first ring gate transistor and is used to isolate the first ring gate transistor and the second ring gate transistor; An etch stop layer is disposed between the interlayer dielectric layer and the second gate ring transistor, wherein the etch stop layer and the interlayer dielectric layer are made of different materials.

2. The semiconductor device according to claim 1, characterized in that, The second ring gate transistor includes a channel region having at least one layer of nanostructure; each of the nanostructures is an integral structure.

3. The semiconductor device according to claim 1, characterized in that, The gate stack structure of the second ring gate transistor is self-aligned with the channel region of the second ring gate transistor.

4. The semiconductor device according to claim 1, characterized in that, The second gate ring transistor includes a channel region having at least one nanostructure, each nanostructure comprising two nanowires / sheets spaced apart along a first direction; the two different nanowires / sheets in the same nanostructure are aligned along the thickness direction of the semiconductor substrate; The first direction is parallel to the length direction of the gate stack structure included in the second ring gate transistor.

5. The semiconductor device according to claim 4, characterized in that, The second ring-gate transistor includes a channel region with intrinsic conductivity; or, The conductivity type of the channel region included in the second gate ring transistor is opposite to that of the source and drain regions included in the second gate ring transistor, and the impurity doping concentration in the channel region included in the second gate ring transistor is less than the impurity doping concentration in the source and drain regions included in the second gate ring transistor.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The second gate-ring transistor comprises a source region, a drain region, and a channel region all made of polycrystalline semiconductor material; and / or, The second ring gate transistor includes a source region, a drain region, and a channel region integrally formed.

7. A method for manufacturing a semiconductor device, characterized in that, include: Provide a semiconductor substrate; A first gate ring transistor is formed on the semiconductor substrate; the channel region of the first gate ring transistor is made of a single-crystal semiconductor material. An interlayer dielectric layer is formed covering the first gate ring transistor; An etch stop layer is formed on the interlayer dielectric layer; the etch stop layer and the interlayer dielectric layer are made of different materials. A second ring gate transistor is formed above the first ring gate transistor and spaced apart from it; the source region, drain region and channel region of the second ring gate transistor are all made of polycrystalline semiconductor material; the second ring gate transistor and the first ring gate transistor constitute a three-dimensional stacked complementary transistor; the interlayer dielectric layer is used to isolate the first ring gate transistor and the second ring gate transistor.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The formation of a second ring gate transistor located above and spaced apart from the first ring gate transistor includes: A patterned structure is formed above the first gate ring transistor; the patterned structure includes alternating layers of a first dielectric layer and a channel forming layer along the thickness direction of the semiconductor substrate; in the alternating layers of the first dielectric layer and the channel forming layer, the bottom layer is the first dielectric layer; each channel forming layer includes an amorphous semiconductor layer; The amorphous semiconductor layer is subjected to low-temperature annealing to form a polycrystalline semiconductor layer. At least all of the first dielectric layers included in the patterned structure are removed such that all of the polycrystalline semiconductor layers form the channel region included in the second gate ring transistor.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, Each of the channel forming layers comprises only the amorphous semiconductor layer.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The formation of a patterned structure above the first ring gate transistor includes: An alternating layer of first dielectric material and amorphous semiconductor material is formed above the first ring gate transistor; The alternatingly stacked first dielectric material layer and amorphous semiconductor material layer are patterned to form a fin structure; along the length direction of the fin structure, the fin structure has a source formation region, a drain formation region, and a channel formation region located between the source formation region and the drain formation region; the portion of the fin structure located in the channel formation region is the pattern structure.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, After forming at least a patterned structure above the first ring-gate transistor, and before performing low-temperature annealing on the amorphous semiconductor layer, the method for manufacturing the semiconductor device further includes: A sacrificial gate and sidewalls are formed across the pattern structure; the sidewalls are formed at least on both sides of the sacrificial gate along its own length. Remove the portion of the fin-like structure located within the source formation region and the drain formation region; The source and drain regions of the second ring gate transistor are formed on both sides of the pattern structure along the length direction of the sacrificial gate; After performing low-temperature annealing on the amorphous semiconductor layer, and before removing at least all of the first dielectric layers included in the patterned structure, the method for manufacturing the semiconductor device further includes removing the sacrificial gate.

12. The method for manufacturing a semiconductor device according to claim 8, characterized in that, In the alternating stacked first dielectric layer and channel forming layer, the top layer is the first dielectric layer; the patterned structure further includes an amorphous semiconductor capping layer formed on the top first dielectric layer; Each of the channel forming layers includes a second dielectric layer and an amorphous semiconductor layer located on both sides of the second dielectric layer along a first direction; the material of the second dielectric layer is different from the material of the first dielectric layer; the first direction is parallel to the length direction of the gate stack structure included in the second ring gate transistor; The step of removing at least all of the first dielectric layers included in the patterned structure includes: removing all of the first dielectric layers and all of the second dielectric layers included in the patterned structure.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The formation of a patterned structure above the first ring gate transistor includes: An alternating stack of the first dielectric layer and the second dielectric material layer is formed above the first gate ring transistor; Along the first direction, the second dielectric material layer is selectively thinned laterally so that the remaining portion of each second dielectric material layer forms the corresponding second dielectric layer; the sidewall of the second dielectric layer is recessed inward relative to the sidewall of the first dielectric layer to form a channel forming space; An amorphous semiconductor material is formed covering a semiconductor substrate; the portion of the amorphous semiconductor material filling the channel formation space is the amorphous semiconductor layer; the portion of the amorphous semiconductor material located on the top first dielectric layer is the amorphous semiconductor capping layer.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, While the amorphous semiconductor layer is subjected to low-temperature annealing, the remaining portion of the amorphous semiconductor material forms a polycrystalline semiconductor material. After performing low-temperature annealing on the amorphous semiconductor layer, and before removing at least all of the first dielectric layers included in the patterned structure, the method for manufacturing the semiconductor device further includes: The polycrystalline semiconductor material is doped to the portion of the source and drain regions corresponding to the second gate ring transistor to obtain the source and drain regions of the second gate ring transistor. Under the masking effect of the mask layer, the polycrystalline semiconductor material is patterned to retain only the polycrystalline semiconductor layer and the source and drain regions included in the second gate ring transistor; the mask layer covers the source and drain regions included in the second gate ring transistor.

15. A method for manufacturing a semiconductor device according to any one of claims 8 to 14, characterized in that, The low-temperature annealing treatment is performed at a temperature greater than 0°C and less than or equal to 600°C; and / or, The annealing time for the low-temperature annealing process is greater than or equal to 1 hour and less than or equal to 24 hours.

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