A field-effect transistor

Abstract

This invention discloses a field-effect transistor (FET), comprising trench structures extending into a first conductivity type semiconductor drift region. Each trench structure includes at least two first sub-trench structures and one second sub-trench structure, with the at least two first sub-trench structures arranged sequentially along a third direction. Each first sub-trench structure includes a shielding gate polysilicon electrode. A second conductivity type region is located between adjacent first sub-trench structures. The opposing surfaces of adjacent first sub-trench structures are designated as first surfaces, and the surfaces of first sub-trench structures adjacent to the first conductivity type semiconductor substrate are designated as second surfaces. The second conductivity type region at least covers a portion of the first surface intersecting with the second surface and / or at least covers a portion of the second surface intersecting with the first surface. This invention can alleviate electric field concentration at the bottom corner of the shielding gate trench, improving device reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a field-effect transistor. Background Technology

[0002] To improve the performance of DMOS, researchers have proposed novel structures such as shielded-gate MOSFETs. Shielded-gate MOSFETs utilize their first polycrystalline layer (i.e., the shielded gate electrode) as a "body field plate" to reduce the electric field in the drift region. Therefore, shielded-gate MOSFETs typically have lower on-resistance and higher breakdown voltage.

[0003] Figure 1 This is a perspective view of a conventional shielded gate MOSFET structure provided in an embodiment of the present invention, for reference. Figure 1 In a conventional shielded-gate MOSFET, the shielded gate polysilicon electrode 7 (shielded gate) and the gate polysilicon electrode 8 (control gate) are located in the same deep trench, corresponding vertically, with the trench extending in the Z-direction. It can be seen that the shielded gate polysilicon electrode 7 occupies a large current spread region, which to some extent limits the improvement of the device's current capability. Furthermore, the shielded gate polysilicon electrode 7 must be fabricated in a deep trench, where the electric field concentrates at the bottom, especially at the corners, leading to reduced device reliability. Summary of the Invention

[0004] This invention provides a field-effect transistor to alleviate electric field concentration at the bottom corner of the trench where the shielded gate polysilicon electrode is located, thereby improving device reliability.

[0005] According to one aspect of the present invention, a field-effect transistor is provided, comprising:

[0006] A first conductivity type semiconductor substrate, a first conductivity type semiconductor drift region, a second conductivity type semiconductor well region, a shielded gate polysilicon electrode, a gate polysilicon electrode, a shielded gate dielectric layer, an isolation dielectric layer, a gate dielectric layer, and a second conductivity type region.

[0007] The first type of conductive semiconductor substrate, the first type of conductive semiconductor drift region, and the second type of conductive semiconductor well region are sequentially stacked along a first direction;

[0008] A trench structure extends into the drift region of a first conductivity type semiconductor. The trench structure includes a shielded gate polysilicon electrode, a gate polysilicon electrode, a shielded gate dielectric layer, an isolation dielectric layer, and a gate dielectric layer. Two trench structures are located on both sides of a second conductivity type semiconductor well region along a second direction. The trench structure extends along a third direction. The first direction, the second direction, and the third direction are perpendicular to each other.

[0009] Each of the trench structures includes at least two first sub-trench structures and one second sub-trench structure. The at least two first sub-trench structures are arranged sequentially along the third direction. The second sub-trench structure is located on the side of the first sub-trench structure away from the first conductivity type semiconductor substrate along the first direction, and the second sub-trench structure is interconnected with the first sub-trench structure. Each first sub-trench structure includes one of the shielding gate polysilicon electrodes, and the second sub-trench structure includes a gate polysilicon electrode.

[0010] The shielded gate polysilicon electrode and the gate polysilicon electrode are separated by the isolation dielectric layer, the shielded gate polysilicon electrode and the first conductivity type semiconductor drift region are separated by the shielded gate dielectric layer, and the gate polysilicon electrode and the second conductivity type semiconductor well region are separated by the gate dielectric layer.

[0011] Along the third direction, a second conductivity type region is provided between adjacent first sub-trench structures; along the third direction, the opposing surfaces of adjacent first sub-trench structures are first surfaces, and the surfaces of the first sub-trench structures adjacent to the first conductivity type semiconductor substrate are second surfaces.

[0012] The second conductive type region covers at least the portion of the first surface that intersects with the second surface and / or the second conductive type region covers at least the portion of the second surface that intersects with the first surface.

[0013] Optionally, the second conductivity type region covers the first surface of each of the first sub-trench structures, and the distance between the surface of the second conductivity type region adjacent to the first conductivity type semiconductor substrate and the first conductivity type semiconductor substrate is less than the distance between the second surface and the first conductivity type semiconductor substrate.

[0014] Optionally, the second conductivity type region fills the area between adjacent first sub-trench structures along the third direction.

[0015] Optionally, along the third direction, there is a gap between the second conductivity type regions of the first surface of adjacent first sub-groove structures.

[0016] Optionally, the second conductive type region covers the first surface and the second surface of each of the first sub-trench structures.

[0017] Optionally, the shielding gate polysilicon electrode 7 is connected to the source potential.

[0018] Optionally, at least two shielded gate polysilicon electrodes 7 arranged sequentially along the third direction are electrically connected to each other on the side away from the first conductivity type semiconductor substrate, and are connected to the source potential after electrical connection.

[0019] Optionally, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0020] Optionally, the field-effect transistor also includes:

[0021] The second type of conductivity semiconductor ohmic contact region, the first type of conductivity semiconductor source region, the drain metal layer, the gate-source dielectric layer and the source metal;

[0022] The second type of conductivity semiconductor ohmic contact region and the first type of conductivity semiconductor source region are located on the side of the second type of conductivity semiconductor well region away from the first type of conductivity semiconductor drift region, and the first type of conductivity semiconductor source region is located on both sides of the second type of conductivity semiconductor ohmic contact region along the second direction; the gate polysilicon electrode and the first type of conductivity semiconductor source region are separated by a gate dielectric layer.

[0023] The drain metal layer is located on the side of the first conductivity type semiconductor substrate away from the first conductivity type semiconductor drift region;

[0024] The gate-source dielectric layer is located on the side of the gate polysilicon electrode away from the first conductivity type semiconductor substrate, and the gate-source dielectric layer covers a portion of the first conductivity type semiconductor source region;

[0025] The source metal is located on the side of the second conductivity type semiconductor ohmic contact region away from the first conductivity type semiconductor substrate, and covers another part of the first conductivity type semiconductor source region.

[0026] Optionally, the materials for the shielding gate dielectric layer, the isolation dielectric layer, and the gate dielectric layer include silicon dioxide.

[0027] In this embodiment of the invention, the shielding gate polysilicon electrode directly below the gate polysilicon electrode is fabricated as a segmented structure along the trench extension direction. At least two shielding gate polysilicon electrodes correspond to each gate polysilicon electrode. When the field-effect transistor is in the off state, the segmented shielding gate assists in the depletion of the first conductivity type semiconductor drift region, making the electric field distribution in the first conductivity type semiconductor drift region more uniform. Furthermore, by setting a second conductivity type region between two adjacent first sub-trench structures, the second conductivity type region covers a portion of the first surface and / or the second surface of the first sub-trench structure adjacent to the bottom corner of the first sub-trench structure. The second conductivity type region can reduce the electric field intensity at the bottom corner of the first sub-trench structure, alleviate the phenomenon of electric field concentration at the bottom corner of the trench, better protect the bottom corner of the trench, and improve device reliability.

[0028] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a perspective view of a conventional shielded gate MOSFET structure provided in an embodiment of the present invention;

[0031] Figure 2 This is a three-dimensional view of a field-effect transistor provided in an embodiment of the present invention;

[0032] Figure 3 yes Figure 2 Cross-sectional view of the central trench structure;

[0033] Figure 4 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention;

[0034] Figure 5 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention;

[0035] Figure 6 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention;

[0036] Figure 7 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention;

[0037] Figure 8 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention;

[0038] Figure 9 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] This invention provides a field-effect transistor. Figure 2 This is a three-dimensional view of a field-effect transistor provided in an embodiment of the present invention. Figure 3 yes Figure 2 Cross-sectional view of the central trench structure. Figure 4 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention. Figure 5 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention, with reference to... Figures 2-5 Field-effect transistors include:

[0042] 2. First conductivity type semiconductor substrate, 3. First conductivity type semiconductor drift region, 4. Second conductivity type semiconductor well region, 7. Shielding gate polysilicon electrode, 8. Gate polysilicon electrode, 9. Shielding gate dielectric layer, 10. Isolation dielectric layer, 11. Gate dielectric layer and 14.

[0043] The first type of conductivity semiconductor substrate 2, the first type of conductivity semiconductor drift region 3, and the second type of conductivity semiconductor well region 4 are stacked sequentially along the first direction X;

[0044] The trench structure 100 extends into the first conductivity type semiconductor drift region 3. The trench structure 100 includes a shielded gate polysilicon electrode 7, a gate polysilicon electrode 8, a shielded gate dielectric layer 9, an isolation dielectric layer 10, and a gate dielectric layer 11. The two trench structures 100 are located on both sides of the second conductivity type semiconductor well region 4 along the second direction Y, and the trench structure 100 extends along the third direction Z. The first direction X, the second direction Y, and the third direction Z are perpendicular to each other.

[0045] Each trench structure 100 includes at least two first sub-trench structures 101 and one second sub-trench structure 102. The at least two first sub-trench structures 101 are arranged sequentially along a third direction Z. The second sub-trench structure 102 is located along a first direction X on the side of the first sub-trench structure 101 away from the first conductivity type semiconductor substrate 2, and the second sub-trench structure 102 is interconnected with the first sub-trench structure 101. Each first sub-trench structure 101 includes a shielding gate polysilicon electrode 7, and the second sub-trench structure 102 includes a gate polysilicon electrode 8.

[0046] The shielded gate polysilicon electrode 7 and the gate polysilicon electrode 8 are separated by an isolation dielectric layer 10, the shielded gate polysilicon electrode 7 is separated from the first conductivity type semiconductor drift region 3 by a shielded gate dielectric layer 9, and the gate polysilicon electrode 8 is separated from the second conductivity type semiconductor well region 4 by a gate dielectric layer 11.

[0047] Along the third direction Z, a second conductivity type region 14 is provided between adjacent first sub-trench structures 101; along the third direction Z, the opposing surfaces of adjacent first sub-trench structures 101 are first surfaces 1011, and the surfaces of the first sub-trench structures 101 adjacent to the first conductivity type semiconductor substrate 2 are second surfaces 1012.

[0048] The second conductive type region 14 at least covers the portion of the first surface 1011 that intersects with the second surface 1012 and / or the second conductive type region 14 at least covers the portion of the second surface 1012 that intersects with the first surface 1011.

[0049] The first conductivity type semiconductor substrate 2 can be a heavily doped first conductivity type semiconductor substrate 2. Each trench structure 100 can include two or more first sub-trench structures 101. The specific number of first sub-trench structures 101 can be determined according to the required number of shielding gate polysilicon electrodes 7, and this embodiment does not make a specific limitation. The first sub-trench structure 101 includes a shielding gate polysilicon electrode 7 and a shielding gate dielectric layer 9 that separates the shielding gate polysilicon electrode 7 from the first conductivity type semiconductor drift region 3. The second sub-trench structure 102 includes a gate polysilicon electrode 8 and a gate dielectric layer 11 that separates the gate polysilicon electrode 8 from the second conductivity type semiconductor well region 4. The isolation dielectric layer 10 that separates the shielding gate polysilicon electrode 7 and the gate polysilicon electrode 8 can be partially located in the first sub-trench structure 101 and partially located in the second sub-trench structure 102, or it can be entirely located in the first sub-trench structure 101 or entirely located in the second sub-trench structure 102, and this embodiment does not make a specific limitation. The first sub-trench structure 101 and the second sub-trench structure 102 are connected by an isolation dielectric layer 10. Multiple shielded gate polysilicon electrodes 7 are all located below the gate polysilicon electrode 8. The first preset region can be a portion of the first surface 1011 or the entire region of the first surface 1011; the second preset region can be a portion of the second surface 1012 or the entire region of the second surface 1012. (Reference) Figures 3-5 The second conductive type region 14 may cover only the first preset region, or only the second preset region, or both the first preset region and the second preset region.

[0050] Specifically, when the bias voltage on the gate polysilicon electrode 8 is less than the threshold voltage, the field-effect transistor is in the off state. At this time, the drain-source voltage is borne by the first conductivity type semiconductor drift region 3. The electric field in the shielding gate dielectric layer 9 accumulates at the sharp corner at the bottom of the first sub-trench structure 101. The electric field strength at this location is relatively large, which affects the reliability of the device in long-term operation.

[0051] In this embodiment of the invention, the shielding gate polysilicon electrode 7 directly below the gate polysilicon electrode 8 is fabricated as a segmented structure along the trench extension direction. At least two shielding gate polysilicon electrodes 7 correspond to each gate polysilicon electrode 8. When the field-effect transistor is in the off state, the segmented shielding gate assists in the depletion of the first conductivity type semiconductor drift region 3, making the electric field distribution of the first conductivity type semiconductor drift region 3 more uniform. Furthermore, by setting a second conductivity type region 14 between two adjacent first sub-trench structures 101, the second conductivity type region 14 covers a portion of the first surface 1011 and / or the second surface 1012 of the first sub-trench structure 101 near the bottom corner of the first sub-trench structure 101. The second conductivity type region 14 can reduce the electric field intensity at the bottom corner of the first sub-trench structure 101, alleviate the phenomenon of electric field concentration at the bottom corner of the trench, better protect the bottom corner of the trench, and improve the reliability of the device.

[0052] Figure 6 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention. Optional, refer to... Figure 6 The second conductivity type region 14 covers the first surface 1011 of each first sub-trench structure 101, and the distance between the surface of the second conductivity type region 14 adjacent to the first conductivity type semiconductor substrate 2 and the first conductivity type semiconductor substrate 2 is less than the distance between the second surface 1012 and the first conductivity type semiconductor substrate 2.

[0053] That is, the bottom surface of the second conductivity type region 14 is closer to the first conductivity type semiconductor substrate 2 than the second surface 1012. This arrangement allows the second conductivity type region 14 to reduce the electric field intensity at the bottom corner of the first sub-trench structure 101, alleviating the phenomenon of electric field concentration at the bottom corner of the trench. Furthermore, the second conductivity type region 14 covers the first surface 1011 of each first sub-trench structure 101, meaning that the second conductivity type region 14 is located between adjacent first sub-trench structures 101. The second conductivity type region 14 is easier to manufacture, reducing the process difficulty.

[0054] Optional, continue to refer to Figure 6 The second conductive type region 14 fills the area between the first sub-trench structures 101 adjacent to each other along the third direction Z.

[0055] This configuration can better reduce the electric field strength at the bottom corner of the first sub-trench structure 101, alleviate the phenomenon of electric field concentration at the bottom corner of the trench, and better protect the bottom corner of the trench. In addition, when the device withstands reverse voltage, the second conductivity type region 14 can assist in the depletion of the first conductivity type semiconductor drift region 3. Therefore, the first conductivity type semiconductor drift region 3 can use a higher doping concentration, thereby reducing the specific on-resistance of the device.

[0056] Figure 7 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention. Optional, refer to... Figure 2 and 7 Along the third direction Z, there is a gap between the second conductive type regions 14 of the first surface 1011 of the adjacent first sub-groove structure 101.

[0057] Specifically, along the third direction Z, the gap between the second conductivity type regions 14 of the first surface 1011 of the adjacent first sub-trench structure 101 is the first conductivity type semiconductor drift region 3. When the field-effect transistor is in the conducting state, the current of the device gradually spreads from the end of the channel region into the first conductivity type semiconductor drift region 3. The first conductivity type semiconductor drift region 3 in the gap between the second conductivity type regions 14 can serve as a current extension region, increasing the conductivity path, thereby effectively improving the current capability of the device and reducing the specific on-resistance of the device.

[0058] The embodiments of the present invention can reduce the electric field intensity at the bottom corner of the first sub-trench structure 101, alleviate the phenomenon of electric field concentration at the bottom corner of the trench, and increase the current extension region. Therefore, while improving the reliability of the device, it also increases the current flow region and the auxiliary depletion drift region, and reduces the specific on-resistance of the device.

[0059] Figure 8 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention. Optional, refer to... Figure 8 The second conductive type region 14 covers the first surface 1011 and the second surface 1012 of each first sub-trench structure 101.

[0060] This design can better reduce the electric field intensity at the bottom corner of the first sub-trench structure 101, alleviate the phenomenon of electric field concentration at the bottom corner of the trench, and better protect the bottom corner of the trench.

[0061] Optionally, the shielded gate polysilicon electrode 7 is connected to the source potential.

[0062] Specifically, while floating the potential of the shielded gate polysilicon electrode 7 can reduce the gate-drain capacitance and assist in depleting the drift region during breakdown voltage, the potential of the shielded gate polysilicon electrode 7 may change during device operation, affecting the stability and reliability of the device's electrical characteristics. This embodiment fixes the potential of the shielded gate polysilicon electrode 7 at the source potential, effectively improving the stability and reliability of the device's electrical characteristics.

[0063] Figure 9 This is a cross-sectional view of another trench structure provided in an embodiment of the present invention. Optional, refer to... Figure 9At least two shielded gate polysilicon electrodes 7 arranged sequentially along the third direction Z are electrically connected to each other on the side away from the first conductivity type semiconductor substrate 2, and are connected to the source potential after electrical connection.

[0064] Specifically, after at least two shielded gate polysilicon electrodes 7 are electrically connected to each other, they can be connected to the source potential by leads at the edge.

[0065] Optionally, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0066] Optional, continue to refer to Figure 2 Field-effect transistors also include:

[0067] The second type of semiconductor ohmic contact region 5, the first type of semiconductor source region 6, the drain metal layer 1, the gate-source dielectric layer 12 and the source metal 13;

[0068] The second conductivity type semiconductor ohmic contact region 5 and the first conductivity type semiconductor source region 6 are located on the side of the second conductivity type semiconductor well region 4 away from the first conductivity type semiconductor drift region 3. The first conductivity type semiconductor source region 6 is located on both sides of the second conductivity type semiconductor ohmic contact region 5 along the second direction Y. The gate polysilicon electrode 8 and the first conductivity type semiconductor source region 6 are separated by the gate dielectric layer 11.

[0069] The drain metal layer is located on the side of the first conductivity type semiconductor substrate 2 away from the first conductivity type semiconductor drift region 3;

[0070] The gate-source dielectric layer 12 is located on the side of the gate polysilicon electrode 8 away from the first conductivity type semiconductor substrate 2, and the gate-source dielectric layer 12 covers a portion of the first conductivity type semiconductor source region 6;

[0071] The source metal 13 is located on the side of the second conductivity type semiconductor ohmic contact region 5 away from the first conductivity type semiconductor substrate (2), and covers another part of the first conductivity type semiconductor source region 6.

[0072] The second conductivity type semiconductor ohmic contact region 5 can be a heavily doped second conductivity type semiconductor ohmic contact region 5, and the first conductivity type semiconductor source region 6 can be a heavily doped first conductivity type semiconductor source region 6. The second conductivity type semiconductor ohmic contact region 5 is located above the center of the second conductivity type semiconductor well region 4, and the first conductivity type semiconductor source regions 6 are located on both sides of the second conductivity type semiconductor ohmic contact region 5.

[0073] When the bias voltage on the gate polysilicon electrode 8 is greater than the threshold voltage, an inversion layer is formed in the channel region of the second conductivity type semiconductor well region 4. Under the action of the high drain voltage, electrons flow out from the source, pass through the channel region and the first conductivity type semiconductor drift region 3 in sequence, and then enter the first conductivity type semiconductor substrate 2, forming a complete current path, and the field-effect transistor is in the on state. When the bias voltage on the gate polysilicon electrode 8 is less than the threshold voltage, no inversion layer is formed in the channel region of the second conductivity type semiconductor well region 4, and the field-effect transistor is in the off state.

[0074] Optionally, the materials of the shielding gate dielectric layer 9, the isolation dielectric layer 10, and the gate dielectric layer 11 include silicon dioxide.

[0075] The shielding gate dielectric layer 9, the isolation dielectric layer 10, and the gate dielectric layer 11 can also be made of other high dielectric constant materials (high-K materials) besides silicon dioxide.

[0076] Furthermore, the semiconductor material in the semiconductor structure of this embodiment can be silicon or silicon carbide.

[0077] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is imposed herein.

[0078] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A field-effect transistor, characterized in that, include: A first conductivity type semiconductor substrate, a first conductivity type semiconductor drift region, a second conductivity type semiconductor well region, a shielded gate polysilicon electrode, a gate polysilicon electrode, a shielded gate dielectric layer, an isolation dielectric layer, a gate dielectric layer, and a second conductivity type region. The first type of conductive semiconductor substrate, the first type of conductive semiconductor drift region, and the second type of conductive semiconductor well region are sequentially stacked along a first direction; A trench structure extends into the drift region of a first conductivity type semiconductor. The trench structure includes a shielded gate polysilicon electrode, a gate polysilicon electrode, a shielded gate dielectric layer, an isolation dielectric layer, and a gate dielectric layer. Two trench structures are located on both sides of a second conductivity type semiconductor well region along a second direction. The trench structure extends along a third direction. The first direction, the second direction, and the third direction are perpendicular to each other. Each of the trench structures includes at least two first sub-trench structures and one second sub-trench structure. The at least two first sub-trench structures are arranged sequentially along the third direction. The second sub-trench structure is located on the side of the first sub-trench structure away from the first conductivity type semiconductor substrate along the first direction, and the second sub-trench structure is interconnected with the first sub-trench structure. Each first sub-trench structure includes one of the shielding gate polysilicon electrodes, and the second sub-trench structure includes a gate polysilicon electrode. The shielded gate polysilicon electrode and the gate polysilicon electrode are separated by the isolation dielectric layer, the shielded gate polysilicon electrode and the first conductivity type semiconductor drift region are separated by the shielded gate dielectric layer, and the gate polysilicon electrode and the second conductivity type semiconductor well region are separated by the gate dielectric layer. Along the third direction, a second conductivity type region is provided between adjacent first sub-trench structures; along the third direction, the opposing surfaces of adjacent first sub-trench structures are first surfaces, and the surfaces of the first sub-trench structures adjacent to the first conductivity type semiconductor substrate are second surfaces. The second conductive type region covers at least the portion of the first surface that intersects with the second surface and / or the second conductive type region covers at least the portion of the second surface that intersects with the first surface.

2. The field-effect transistor according to claim 1, characterized in that: The second conductivity type region covers the first surface of each of the first sub-trench structures, and the distance between the surface of the second conductivity type region adjacent to the first conductivity type semiconductor substrate and the first conductivity type semiconductor substrate is less than the distance between the second surface and the first conductivity type semiconductor substrate.

3. The field-effect transistor according to claim 2, characterized in that: The second conductivity type region fills the area between the adjacent first sub-trench structures along the third direction.

4. The field-effect transistor according to claim 2, characterized in that: Along the third direction, there is a gap between the second conductivity type regions of the first surface of the adjacent first sub-groove structures.

5. The field-effect transistor according to claim 1, characterized in that: The second conductive type region covers the first surface and the second surface of each of the first sub-trench structures.

6. The field-effect transistor according to claim 1, characterized in that: The shielding gate polycrystalline silicon electrode 7 is connected to the source potential.

7. The field-effect transistor according to claim 6, characterized in that: At least two shielded gate polysilicon electrodes 7 arranged sequentially along the third direction are electrically connected to each other on the side away from the first conductivity type semiconductor substrate, and are connected to the source potential after electrical connection.

8. The field-effect transistor according to claim 1, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

9. The field-effect transistor according to claim 1, characterized in that, Also includes: The second type of conductivity semiconductor ohmic contact region, the first type of conductivity semiconductor source region, the drain metal layer, the gate-source dielectric layer and the source metal; The second type of conductivity semiconductor ohmic contact region and the first type of conductivity semiconductor source region are located on the side of the second type of conductivity semiconductor well region away from the first type of conductivity semiconductor drift region, and the first type of conductivity semiconductor source region is located on both sides of the second type of conductivity semiconductor ohmic contact region along the second direction; the gate polysilicon electrode and the first type of conductivity semiconductor source region are separated by a gate dielectric layer. The drain metal layer is located on the side of the first conductivity type semiconductor substrate away from the first conductivity type semiconductor drift region; The gate-source dielectric layer is located on the side of the gate polysilicon electrode away from the first conductivity type semiconductor substrate, and the gate-source dielectric layer covers a portion of the first conductivity type semiconductor source region; The source metal is located on the side of the second conductivity type semiconductor ohmic contact region away from the first conductivity type semiconductor substrate, and covers another part of the first conductivity type semiconductor source region.

10. The field-effect transistor according to claim 1, characterized in that: The materials for the shielding gate dielectric layer, the isolation dielectric layer, and the gate dielectric layer include silicon dioxide.

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